root / target-arm / op_iwmmxt.c @ 4373f3ce
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1 | 18c9b560 | balrog | /*
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2 | 18c9b560 | balrog | * iwMMXt micro operations for XScale.
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3 | 5fafdf24 | ths | *
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4 | 18c9b560 | balrog | * Copyright (c) 2007 OpenedHand, Ltd.
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5 | 18c9b560 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 18c9b560 | balrog | *
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7 | 18c9b560 | balrog | * This library is free software; you can redistribute it and/or
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8 | 18c9b560 | balrog | * modify it under the terms of the GNU Lesser General Public
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9 | 18c9b560 | balrog | * License as published by the Free Software Foundation; either
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10 | 18c9b560 | balrog | * version 2 of the License, or (at your option) any later version.
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11 | 18c9b560 | balrog | *
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12 | 18c9b560 | balrog | * This library is distributed in the hope that it will be useful,
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13 | 18c9b560 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 18c9b560 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 18c9b560 | balrog | * Lesser General Public License for more details.
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16 | 18c9b560 | balrog | *
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17 | 18c9b560 | balrog | * You should have received a copy of the GNU Lesser General Public
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18 | 18c9b560 | balrog | * License along with this library; if not, write to the Free Software
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19 | 18c9b560 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 18c9b560 | balrog | */
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21 | 18c9b560 | balrog | |
22 | 18c9b560 | balrog | #define M1 env->iwmmxt.regs[PARAM1]
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23 | 18c9b560 | balrog | |
24 | 18c9b560 | balrog | /* iwMMXt macros extracted from GNU gdb. */
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25 | 18c9b560 | balrog | |
26 | 18c9b560 | balrog | /* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
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27 | 18c9b560 | balrog | #define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n))) |
28 | 18c9b560 | balrog | #define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n))) |
29 | 18c9b560 | balrog | #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) |
30 | 18c9b560 | balrog | #define SIMD64_SET(v, n) ((v != 0) << (32 + (n))) |
31 | 18c9b560 | balrog | /* Flags to pass as "n" above. */
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32 | 18c9b560 | balrog | #define SIMD_NBIT -1 |
33 | 18c9b560 | balrog | #define SIMD_ZBIT -2 |
34 | 18c9b560 | balrog | #define SIMD_CBIT -3 |
35 | 18c9b560 | balrog | #define SIMD_VBIT -4 |
36 | 18c9b560 | balrog | /* Various status bit macros. */
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37 | 18c9b560 | balrog | #define NBIT8(x) ((x) & 0x80) |
38 | 18c9b560 | balrog | #define NBIT16(x) ((x) & 0x8000) |
39 | 18c9b560 | balrog | #define NBIT32(x) ((x) & 0x80000000) |
40 | 18c9b560 | balrog | #define NBIT64(x) ((x) & 0x8000000000000000ULL) |
41 | 18c9b560 | balrog | #define ZBIT8(x) (((x) & 0xff) == 0) |
42 | 18c9b560 | balrog | #define ZBIT16(x) (((x) & 0xffff) == 0) |
43 | 18c9b560 | balrog | #define ZBIT32(x) (((x) & 0xffffffff) == 0) |
44 | 18c9b560 | balrog | #define ZBIT64(x) (x == 0) |
45 | 18c9b560 | balrog | /* Sign extension macros. */
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46 | 18c9b560 | balrog | #define EXTEND8H(a) ((uint16_t) (int8_t) (a))
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47 | 18c9b560 | balrog | #define EXTEND8(a) ((uint32_t) (int8_t) (a))
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48 | 18c9b560 | balrog | #define EXTEND16(a) ((uint32_t) (int16_t) (a))
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49 | 18c9b560 | balrog | #define EXTEND16S(a) ((int32_t) (int16_t) (a))
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50 | 18c9b560 | balrog | #define EXTEND32(a) ((uint64_t) (int32_t) (a))
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51 | 18c9b560 | balrog | |
52 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void) |
53 | 18c9b560 | balrog | { |
54 | 18c9b560 | balrog | T0 = M1 & ~(uint32_t) 0;
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55 | 18c9b560 | balrog | T1 = M1 >> 32;
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56 | 18c9b560 | balrog | } |
57 | 18c9b560 | balrog | |
58 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void) |
59 | 18c9b560 | balrog | { |
60 | 18c9b560 | balrog | M1 = ((uint64_t) T1 << 32) | T0;
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61 | 18c9b560 | balrog | } |
62 | 18c9b560 | balrog | |
63 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movq_M0_wRn(void) |
64 | 18c9b560 | balrog | { |
65 | 18c9b560 | balrog | M0 = M1; |
66 | 18c9b560 | balrog | } |
67 | 18c9b560 | balrog | |
68 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_orq_M0_wRn(void) |
69 | 18c9b560 | balrog | { |
70 | 18c9b560 | balrog | M0 |= M1; |
71 | 18c9b560 | balrog | } |
72 | 18c9b560 | balrog | |
73 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_andq_M0_wRn(void) |
74 | 18c9b560 | balrog | { |
75 | 18c9b560 | balrog | M0 &= M1; |
76 | 18c9b560 | balrog | } |
77 | 18c9b560 | balrog | |
78 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_xorq_M0_wRn(void) |
79 | 18c9b560 | balrog | { |
80 | 18c9b560 | balrog | M0 ^= M1; |
81 | 18c9b560 | balrog | } |
82 | 18c9b560 | balrog | |
83 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_maddsq_M0_wRn(void) |
84 | 18c9b560 | balrog | { |
85 | 18c9b560 | balrog | M0 = (( |
86 | 18c9b560 | balrog | EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) + |
87 | 18c9b560 | balrog | EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff) |
88 | 18c9b560 | balrog | ) & 0xffffffff) | ((uint64_t) (
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89 | 18c9b560 | balrog | EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) + |
90 | 18c9b560 | balrog | EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff) |
91 | 18c9b560 | balrog | ) << 32);
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92 | 18c9b560 | balrog | } |
93 | 18c9b560 | balrog | |
94 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_madduq_M0_wRn(void) |
95 | 18c9b560 | balrog | { |
96 | 18c9b560 | balrog | M0 = (( |
97 | 18c9b560 | balrog | ((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) + |
98 | 18c9b560 | balrog | ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff) |
99 | 18c9b560 | balrog | ) & 0xffffffff) | ((
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100 | 18c9b560 | balrog | ((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) + |
101 | 18c9b560 | balrog | ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff) |
102 | 18c9b560 | balrog | ) << 32);
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103 | 18c9b560 | balrog | } |
104 | 18c9b560 | balrog | |
105 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sadb_M0_wRn(void) |
106 | 18c9b560 | balrog | { |
107 | 18c9b560 | balrog | #define abs(x) (((x) >= 0) ? x : -x) |
108 | 18c9b560 | balrog | #define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff)) |
109 | 18c9b560 | balrog | M0 = |
110 | 18c9b560 | balrog | SADB(0) + SADB(8) + SADB(16) + SADB(24) + |
111 | 18c9b560 | balrog | SADB(32) + SADB(40) + SADB(48) + SADB(56); |
112 | 18c9b560 | balrog | #undef SADB
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113 | 18c9b560 | balrog | } |
114 | 18c9b560 | balrog | |
115 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sadw_M0_wRn(void) |
116 | 18c9b560 | balrog | { |
117 | 18c9b560 | balrog | #define SADW(SHR) \
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118 | 18c9b560 | balrog | abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff)) |
119 | 18c9b560 | balrog | M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48); |
120 | 18c9b560 | balrog | #undef SADW
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121 | 18c9b560 | balrog | } |
122 | 18c9b560 | balrog | |
123 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_addl_M0_wRn(void) |
124 | 18c9b560 | balrog | { |
125 | 18c9b560 | balrog | M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;
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126 | 18c9b560 | balrog | } |
127 | 18c9b560 | balrog | |
128 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_mulsw_M0_wRn(void) |
129 | 18c9b560 | balrog | { |
130 | 18c9b560 | balrog | #define MULS(SHR) ((uint64_t) ((( \
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131 | 18c9b560 | balrog | EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \ |
132 | 18c9b560 | balrog | ) >> PARAM2) & 0xffff) << SHR)
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133 | 18c9b560 | balrog | M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48); |
134 | 18c9b560 | balrog | #undef MULS
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135 | 18c9b560 | balrog | } |
136 | 18c9b560 | balrog | |
137 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_muluw_M0_wRn(void) |
138 | 18c9b560 | balrog | { |
139 | 18c9b560 | balrog | #define MULU(SHR) ((uint64_t) ((( \
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140 | 18c9b560 | balrog | ((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \ |
141 | 18c9b560 | balrog | ) >> PARAM2) & 0xffff) << SHR)
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142 | 18c9b560 | balrog | M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48); |
143 | 18c9b560 | balrog | #undef MULU
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144 | 18c9b560 | balrog | } |
145 | 18c9b560 | balrog | |
146 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_macsw_M0_wRn(void) |
147 | 18c9b560 | balrog | { |
148 | 18c9b560 | balrog | #define MACS(SHR) ( \
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149 | 5fafdf24 | ths | EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff)) |
150 | 18c9b560 | balrog | M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48)); |
151 | 18c9b560 | balrog | #undef MACS
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152 | 18c9b560 | balrog | } |
153 | 18c9b560 | balrog | |
154 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_macuw_M0_wRn(void) |
155 | 18c9b560 | balrog | { |
156 | 18c9b560 | balrog | #define MACU(SHR) ( \
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157 | 18c9b560 | balrog | (uint32_t) ((M0 >> SHR) & 0xffff) * \
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158 | 5fafdf24 | ths | (uint32_t) ((M1 >> SHR) & 0xffff))
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159 | 18c9b560 | balrog | M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48); |
160 | 18c9b560 | balrog | #undef MACU
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161 | 18c9b560 | balrog | } |
162 | 18c9b560 | balrog | |
163 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_addsq_M0_wRn(void) |
164 | 18c9b560 | balrog | { |
165 | 18c9b560 | balrog | M0 = (int64_t) M0 + (int64_t) M1; |
166 | 18c9b560 | balrog | } |
167 | 18c9b560 | balrog | |
168 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_adduq_M0_wRn(void) |
169 | 18c9b560 | balrog | { |
170 | 18c9b560 | balrog | M0 += M1; |
171 | 18c9b560 | balrog | } |
172 | 18c9b560 | balrog | |
173 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movq_wRn_M0(void) |
174 | 18c9b560 | balrog | { |
175 | 18c9b560 | balrog | M1 = M0; |
176 | 18c9b560 | balrog | } |
177 | 18c9b560 | balrog | |
178 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movl_wCx_T0(void) |
179 | 18c9b560 | balrog | { |
180 | 18c9b560 | balrog | env->iwmmxt.cregs[PARAM1] = T0; |
181 | 18c9b560 | balrog | } |
182 | 18c9b560 | balrog | |
183 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movl_T0_wCx(void) |
184 | 18c9b560 | balrog | { |
185 | 18c9b560 | balrog | T0 = env->iwmmxt.cregs[PARAM1]; |
186 | 18c9b560 | balrog | } |
187 | 18c9b560 | balrog | |
188 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_movl_T1_wCx(void) |
189 | 18c9b560 | balrog | { |
190 | 18c9b560 | balrog | T1 = env->iwmmxt.cregs[PARAM1]; |
191 | 18c9b560 | balrog | } |
192 | 18c9b560 | balrog | |
193 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_set_mup(void) |
194 | 18c9b560 | balrog | { |
195 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;
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196 | 18c9b560 | balrog | } |
197 | 18c9b560 | balrog | |
198 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_set_cup(void) |
199 | 18c9b560 | balrog | { |
200 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;
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201 | 18c9b560 | balrog | } |
202 | 18c9b560 | balrog | |
203 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_setpsr_nz(void) |
204 | 18c9b560 | balrog | { |
205 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
206 | 18c9b560 | balrog | SIMD64_SET((M0 == 0), SIMD_ZBIT) |
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207 | 18c9b560 | balrog | SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT); |
208 | 18c9b560 | balrog | } |
209 | 18c9b560 | balrog | |
210 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_negq_M0(void) |
211 | 18c9b560 | balrog | { |
212 | 18c9b560 | balrog | M0 = ~M0; |
213 | 18c9b560 | balrog | } |
214 | 18c9b560 | balrog | |
215 | 18c9b560 | balrog | #define NZBIT8(x, i) \
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216 | 18c9b560 | balrog | SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
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217 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
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218 | 18c9b560 | balrog | #define NZBIT16(x, i) \
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219 | 18c9b560 | balrog | SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
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220 | 18c9b560 | balrog | SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
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221 | 18c9b560 | balrog | #define NZBIT32(x, i) \
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222 | 18c9b560 | balrog | SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
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223 | 18c9b560 | balrog | SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
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224 | 18c9b560 | balrog | #define NZBIT64(x) \
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225 | 18c9b560 | balrog | SIMD64_SET(NBIT64(x), SIMD_NBIT) | \ |
226 | 18c9b560 | balrog | SIMD64_SET(ZBIT64(x), SIMD_ZBIT) |
227 | 18c9b560 | balrog | #define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
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228 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void) \ |
229 | 18c9b560 | balrog | { \ |
230 | 18c9b560 | balrog | M0 = \ |
231 | 18c9b560 | balrog | (((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) | \ |
232 | 18c9b560 | balrog | (((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) | \ |
233 | 18c9b560 | balrog | (((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) | \ |
234 | 18c9b560 | balrog | (((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56); \ |
235 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
236 | 18c9b560 | balrog | NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \ |
237 | 18c9b560 | balrog | NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \ |
238 | 18c9b560 | balrog | NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \ |
239 | 18c9b560 | balrog | NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \ |
240 | 18c9b560 | balrog | } \ |
241 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void) \ |
242 | 18c9b560 | balrog | { \ |
243 | 18c9b560 | balrog | M0 = \ |
244 | 18c9b560 | balrog | (((M0 >> SH0) & 0xffff) << 0) | \ |
245 | 18c9b560 | balrog | (((M1 >> SH0) & 0xffff) << 16) | \ |
246 | 18c9b560 | balrog | (((M0 >> SH2) & 0xffff) << 32) | \ |
247 | 18c9b560 | balrog | (((M1 >> SH2) & 0xffff) << 48); \ |
248 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
249 | 18c9b560 | balrog | NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) | \ |
250 | 18c9b560 | balrog | NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3); \ |
251 | 18c9b560 | balrog | } \ |
252 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void) \ |
253 | 18c9b560 | balrog | { \ |
254 | 18c9b560 | balrog | M0 = \ |
255 | 18c9b560 | balrog | (((M0 >> SH0) & 0xffffffff) << 0) | \ |
256 | 18c9b560 | balrog | (((M1 >> SH0) & 0xffffffff) << 32); \ |
257 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
258 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
259 | 18c9b560 | balrog | } \ |
260 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void) \ |
261 | 18c9b560 | balrog | { \ |
262 | 18c9b560 | balrog | M0 = \ |
263 | 18c9b560 | balrog | (((M0 >> SH0) & 0xff) << 0) | \ |
264 | 18c9b560 | balrog | (((M0 >> SH1) & 0xff) << 16) | \ |
265 | 18c9b560 | balrog | (((M0 >> SH2) & 0xff) << 32) | \ |
266 | 18c9b560 | balrog | (((M0 >> SH3) & 0xff) << 48); \ |
267 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
268 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
269 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
270 | 18c9b560 | balrog | } \ |
271 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void) \ |
272 | 18c9b560 | balrog | { \ |
273 | 18c9b560 | balrog | M0 = \ |
274 | 18c9b560 | balrog | (((M0 >> SH0) & 0xffff) << 0) | \ |
275 | 18c9b560 | balrog | (((M0 >> SH2) & 0xffff) << 32); \ |
276 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
277 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
278 | 18c9b560 | balrog | } \ |
279 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void) \ |
280 | 18c9b560 | balrog | { \ |
281 | 18c9b560 | balrog | M0 = (((M0 >> SH0) & 0xffffffff) << 0); \ |
282 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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283 | 18c9b560 | balrog | } \ |
284 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void) \ |
285 | 18c9b560 | balrog | { \ |
286 | 18c9b560 | balrog | M0 = \ |
287 | 18c9b560 | balrog | ((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) | \ |
288 | 18c9b560 | balrog | ((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) | \ |
289 | 18c9b560 | balrog | ((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) | \ |
290 | 18c9b560 | balrog | ((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48); \ |
291 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
292 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
293 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
294 | 18c9b560 | balrog | } \ |
295 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void) \ |
296 | 18c9b560 | balrog | { \ |
297 | 18c9b560 | balrog | M0 = \ |
298 | 18c9b560 | balrog | ((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) | \ |
299 | 18c9b560 | balrog | ((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32); \ |
300 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
301 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
302 | 18c9b560 | balrog | } \ |
303 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void) \ |
304 | 18c9b560 | balrog | { \ |
305 | 18c9b560 | balrog | M0 = EXTEND32((M0 >> SH0) & 0xffffffff); \
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306 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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307 | 18c9b560 | balrog | } |
308 | 18c9b560 | balrog | IWMMXT_OP_UNPACK(l, 0, 8, 16, 24) |
309 | 18c9b560 | balrog | IWMMXT_OP_UNPACK(h, 32, 40, 48, 56) |
310 | 18c9b560 | balrog | |
311 | 18c9b560 | balrog | #define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
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312 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void) \ |
313 | 18c9b560 | balrog | { \ |
314 | 18c9b560 | balrog | M0 = \ |
315 | 18c9b560 | balrog | CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \ |
316 | 18c9b560 | balrog | CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \ |
317 | 18c9b560 | balrog | CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \ |
318 | 18c9b560 | balrog | CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \ |
319 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
320 | 18c9b560 | balrog | NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \ |
321 | 18c9b560 | balrog | NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \ |
322 | 18c9b560 | balrog | NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \ |
323 | 18c9b560 | balrog | NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \ |
324 | 18c9b560 | balrog | } \ |
325 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void) \ |
326 | 18c9b560 | balrog | { \ |
327 | 18c9b560 | balrog | M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \ |
328 | 18c9b560 | balrog | CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \ |
329 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
330 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
331 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
332 | 18c9b560 | balrog | } \ |
333 | 18c9b560 | balrog | void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void) \ |
334 | 18c9b560 | balrog | { \ |
335 | 18c9b560 | balrog | M0 = CMP(0, Tl, O, 0xffffffff) | \ |
336 | 18c9b560 | balrog | CMP(32, Tl, O, 0xffffffff); \ |
337 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
338 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
339 | 18c9b560 | balrog | } |
340 | 18c9b560 | balrog | #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
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341 | 18c9b560 | balrog | (TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
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342 | 18c9b560 | balrog | IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==) |
343 | 18c9b560 | balrog | IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >) |
344 | 18c9b560 | balrog | IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >) |
345 | 18c9b560 | balrog | #undef CMP
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346 | 18c9b560 | balrog | #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
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347 | 18c9b560 | balrog | (TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR)) |
348 | 18c9b560 | balrog | IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <) |
349 | 18c9b560 | balrog | IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <) |
350 | 18c9b560 | balrog | IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >) |
351 | 18c9b560 | balrog | IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >) |
352 | 18c9b560 | balrog | #undef CMP
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353 | 18c9b560 | balrog | #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
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354 | 18c9b560 | balrog | OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR) |
355 | 18c9b560 | balrog | IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -) |
356 | 18c9b560 | balrog | IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +) |
357 | 18c9b560 | balrog | #undef CMP
|
358 | 18c9b560 | balrog | /* TODO Signed- and Unsigned-Saturation */
|
359 | 18c9b560 | balrog | #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
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360 | 18c9b560 | balrog | OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR) |
361 | 18c9b560 | balrog | IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -) |
362 | 18c9b560 | balrog | IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +) |
363 | 18c9b560 | balrog | IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -) |
364 | 18c9b560 | balrog | IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +) |
365 | 18c9b560 | balrog | #undef CMP
|
366 | 18c9b560 | balrog | #undef IWMMXT_OP_CMP
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367 | 18c9b560 | balrog | |
368 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_avgb_M0_wRn(void) |
369 | 18c9b560 | balrog | { |
370 | 18c9b560 | balrog | #define AVGB(SHR) ((( \
|
371 | 18c9b560 | balrog | ((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR) |
372 | 18c9b560 | balrog | M0 = |
373 | 18c9b560 | balrog | AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | |
374 | 18c9b560 | balrog | AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56); |
375 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
376 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) | |
377 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) | |
378 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) | |
379 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) | |
380 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) | |
381 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) | |
382 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) | |
383 | 18c9b560 | balrog | SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7); |
384 | 18c9b560 | balrog | #undef AVGB
|
385 | 18c9b560 | balrog | } |
386 | 18c9b560 | balrog | |
387 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_avgw_M0_wRn(void) |
388 | 18c9b560 | balrog | { |
389 | 18c9b560 | balrog | #define AVGW(SHR) ((( \
|
390 | 18c9b560 | balrog | ((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR) |
391 | 18c9b560 | balrog | M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); |
392 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
393 | 18c9b560 | balrog | SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) | |
394 | 18c9b560 | balrog | SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) | |
395 | 18c9b560 | balrog | SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) | |
396 | 18c9b560 | balrog | SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3); |
397 | 18c9b560 | balrog | #undef AVGW
|
398 | 18c9b560 | balrog | } |
399 | 18c9b560 | balrog | |
400 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_msadb_M0_wRn(void) |
401 | 18c9b560 | balrog | { |
402 | 18c9b560 | balrog | M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) + |
403 | 18c9b560 | balrog | ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) | |
404 | 18c9b560 | balrog | ((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) + |
405 | 18c9b560 | balrog | ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32); |
406 | 18c9b560 | balrog | } |
407 | 18c9b560 | balrog | |
408 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_align_M0_T0_wRn(void) |
409 | 18c9b560 | balrog | { |
410 | 18c9b560 | balrog | M0 >>= T0 << 3;
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411 | 18c9b560 | balrog | M0 |= M1 << (64 - (T0 << 3)); |
412 | 18c9b560 | balrog | } |
413 | 18c9b560 | balrog | |
414 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_insr_M0_T0_T1(void) |
415 | 18c9b560 | balrog | { |
416 | 18c9b560 | balrog | M0 &= ~((uint64_t) T1 << PARAM1); |
417 | 18c9b560 | balrog | M0 |= (uint64_t) (T0 & T1) << PARAM1; |
418 | 18c9b560 | balrog | } |
419 | 18c9b560 | balrog | |
420 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_extrsb_T0_M0(void) |
421 | 18c9b560 | balrog | { |
422 | 18c9b560 | balrog | T0 = EXTEND8((M0 >> PARAM1) & 0xff);
|
423 | 18c9b560 | balrog | } |
424 | 18c9b560 | balrog | |
425 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_extrsw_T0_M0(void) |
426 | 18c9b560 | balrog | { |
427 | 18c9b560 | balrog | T0 = EXTEND16((M0 >> PARAM1) & 0xffff);
|
428 | 18c9b560 | balrog | } |
429 | 18c9b560 | balrog | |
430 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_extru_T0_M0_T1(void) |
431 | 18c9b560 | balrog | { |
432 | 18c9b560 | balrog | T0 = (M0 >> PARAM1) & T1; |
433 | 18c9b560 | balrog | } |
434 | 18c9b560 | balrog | |
435 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_bcstb_M0_T0(void) |
436 | 18c9b560 | balrog | { |
437 | 18c9b560 | balrog | T0 &= 0xff;
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438 | 18c9b560 | balrog | M0 = |
439 | 18c9b560 | balrog | ((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) | |
440 | 18c9b560 | balrog | ((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) | |
441 | 18c9b560 | balrog | ((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) | |
442 | 18c9b560 | balrog | ((uint64_t) T0 << 48) | ((uint64_t) T0 << 56); |
443 | 18c9b560 | balrog | } |
444 | 18c9b560 | balrog | |
445 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_bcstw_M0_T0(void) |
446 | 18c9b560 | balrog | { |
447 | 18c9b560 | balrog | T0 &= 0xffff;
|
448 | 18c9b560 | balrog | M0 = |
449 | 18c9b560 | balrog | ((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) | |
450 | 18c9b560 | balrog | ((uint64_t) T0 << 32) | ((uint64_t) T0 << 48); |
451 | 18c9b560 | balrog | } |
452 | 18c9b560 | balrog | |
453 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_bcstl_M0_T0(void) |
454 | 18c9b560 | balrog | { |
455 | 18c9b560 | balrog | M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32); |
456 | 18c9b560 | balrog | } |
457 | 18c9b560 | balrog | |
458 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_addcb_M0(void) |
459 | 18c9b560 | balrog | { |
460 | 18c9b560 | balrog | M0 = |
461 | 18c9b560 | balrog | ((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) + |
462 | 18c9b560 | balrog | ((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) + |
463 | 18c9b560 | balrog | ((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) + |
464 | 18c9b560 | balrog | ((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff); |
465 | 18c9b560 | balrog | } |
466 | 18c9b560 | balrog | |
467 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_addcw_M0(void) |
468 | 18c9b560 | balrog | { |
469 | 18c9b560 | balrog | M0 = |
470 | 18c9b560 | balrog | ((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) + |
471 | 18c9b560 | balrog | ((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff); |
472 | 18c9b560 | balrog | } |
473 | 18c9b560 | balrog | |
474 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_addcl_M0(void) |
475 | 18c9b560 | balrog | { |
476 | 18c9b560 | balrog | M0 = (M0 & 0xffffffff) + (M0 >> 32); |
477 | 18c9b560 | balrog | } |
478 | 18c9b560 | balrog | |
479 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_msbb_T0_M0(void) |
480 | 18c9b560 | balrog | { |
481 | 18c9b560 | balrog | T0 = |
482 | 18c9b560 | balrog | ((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) | |
483 | 18c9b560 | balrog | ((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) | |
484 | 18c9b560 | balrog | ((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) | |
485 | 18c9b560 | balrog | ((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80); |
486 | 18c9b560 | balrog | } |
487 | 18c9b560 | balrog | |
488 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_msbw_T0_M0(void) |
489 | 18c9b560 | balrog | { |
490 | 18c9b560 | balrog | T0 = |
491 | 18c9b560 | balrog | ((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) | |
492 | 18c9b560 | balrog | ((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08); |
493 | 18c9b560 | balrog | } |
494 | 18c9b560 | balrog | |
495 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_msbl_T0_M0(void) |
496 | 18c9b560 | balrog | { |
497 | 18c9b560 | balrog | T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02); |
498 | 18c9b560 | balrog | } |
499 | 18c9b560 | balrog | |
500 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_srlw_M0_T0(void) |
501 | 18c9b560 | balrog | { |
502 | 18c9b560 | balrog | M0 = |
503 | 18c9b560 | balrog | (((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) | |
504 | 18c9b560 | balrog | (((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) | |
505 | 18c9b560 | balrog | (((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) | |
506 | 18c9b560 | balrog | (((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48)); |
507 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
508 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
509 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
510 | 18c9b560 | balrog | } |
511 | 18c9b560 | balrog | |
512 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_srll_M0_T0(void) |
513 | 18c9b560 | balrog | { |
514 | 18c9b560 | balrog | M0 = |
515 | 18c9b560 | balrog | ((M0 & (0xffffffffll << 0)) >> T0) | |
516 | 18c9b560 | balrog | ((M0 >> T0) & (0xffffffffll << 32)); |
517 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
518 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
519 | 18c9b560 | balrog | } |
520 | 18c9b560 | balrog | |
521 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_srlq_M0_T0(void) |
522 | 18c9b560 | balrog | { |
523 | 18c9b560 | balrog | M0 >>= T0; |
524 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
525 | 18c9b560 | balrog | } |
526 | 18c9b560 | balrog | |
527 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sllw_M0_T0(void) |
528 | 18c9b560 | balrog | { |
529 | 18c9b560 | balrog | M0 = |
530 | 18c9b560 | balrog | (((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) | |
531 | 18c9b560 | balrog | (((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) | |
532 | 18c9b560 | balrog | (((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) | |
533 | 18c9b560 | balrog | (((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48)); |
534 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
535 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
536 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
537 | 18c9b560 | balrog | } |
538 | 18c9b560 | balrog | |
539 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_slll_M0_T0(void) |
540 | 18c9b560 | balrog | { |
541 | 18c9b560 | balrog | M0 = |
542 | 18c9b560 | balrog | ((M0 << T0) & (0xffffffffll << 0)) | |
543 | 18c9b560 | balrog | ((M0 & (0xffffffffll << 32)) << T0); |
544 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
545 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
546 | 18c9b560 | balrog | } |
547 | 18c9b560 | balrog | |
548 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sllq_M0_T0(void) |
549 | 18c9b560 | balrog | { |
550 | 18c9b560 | balrog | M0 <<= T0; |
551 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
552 | 18c9b560 | balrog | } |
553 | 18c9b560 | balrog | |
554 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sraw_M0_T0(void) |
555 | 18c9b560 | balrog | { |
556 | 18c9b560 | balrog | M0 = |
557 | 18c9b560 | balrog | ((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) | |
558 | 18c9b560 | balrog | ((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) | |
559 | 18c9b560 | balrog | ((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) | |
560 | 18c9b560 | balrog | ((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48); |
561 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
562 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
563 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
564 | 18c9b560 | balrog | } |
565 | 18c9b560 | balrog | |
566 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sral_M0_T0(void) |
567 | 18c9b560 | balrog | { |
568 | 18c9b560 | balrog | M0 = |
569 | 18c9b560 | balrog | (((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) | |
570 | 18c9b560 | balrog | (((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32); |
571 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
572 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
573 | 18c9b560 | balrog | } |
574 | 18c9b560 | balrog | |
575 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_sraq_M0_T0(void) |
576 | 18c9b560 | balrog | { |
577 | 18c9b560 | balrog | M0 = (int64_t) M0 >> T0; |
578 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
579 | 18c9b560 | balrog | } |
580 | 18c9b560 | balrog | |
581 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_rorw_M0_T0(void) |
582 | 18c9b560 | balrog | { |
583 | 18c9b560 | balrog | M0 = |
584 | 18c9b560 | balrog | ((((M0 & (0xffffll << 0)) >> T0) | |
585 | 18c9b560 | balrog | ((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) | |
586 | 18c9b560 | balrog | ((((M0 & (0xffffll << 16)) >> T0) | |
587 | 18c9b560 | balrog | ((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) | |
588 | 18c9b560 | balrog | ((((M0 & (0xffffll << 32)) >> T0) | |
589 | 18c9b560 | balrog | ((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) | |
590 | 18c9b560 | balrog | ((((M0 & (0xffffll << 48)) >> T0) | |
591 | 18c9b560 | balrog | ((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48)); |
592 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
593 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
594 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
595 | 18c9b560 | balrog | } |
596 | 18c9b560 | balrog | |
597 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_rorl_M0_T0(void) |
598 | 18c9b560 | balrog | { |
599 | 18c9b560 | balrog | M0 = |
600 | 18c9b560 | balrog | ((M0 & (0xffffffffll << 0)) >> T0) | |
601 | 18c9b560 | balrog | ((M0 >> T0) & (0xffffffffll << 32)) | |
602 | 18c9b560 | balrog | ((M0 << (32 - T0)) & (0xffffffffll << 0)) | |
603 | 18c9b560 | balrog | ((M0 & (0xffffffffll << 32)) << (32 - T0)); |
604 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
605 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
606 | 18c9b560 | balrog | } |
607 | 18c9b560 | balrog | |
608 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_rorq_M0_T0(void) |
609 | 18c9b560 | balrog | { |
610 | 18c9b560 | balrog | M0 = (M0 >> T0) | (M0 << (64 - T0));
|
611 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
612 | 18c9b560 | balrog | } |
613 | 18c9b560 | balrog | |
614 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_shufh_M0_T0(void) |
615 | 18c9b560 | balrog | { |
616 | 18c9b560 | balrog | M0 = |
617 | 18c9b560 | balrog | (((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) | |
618 | 18c9b560 | balrog | (((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) | |
619 | 18c9b560 | balrog | (((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) | |
620 | 18c9b560 | balrog | (((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48); |
621 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
622 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
623 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
624 | 18c9b560 | balrog | } |
625 | 18c9b560 | balrog | |
626 | 18c9b560 | balrog | /* TODO: Unsigned-Saturation */
|
627 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packuw_M0_wRn(void) |
628 | 18c9b560 | balrog | { |
629 | 18c9b560 | balrog | M0 = |
630 | 18c9b560 | balrog | (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) | |
631 | 18c9b560 | balrog | (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) | |
632 | 18c9b560 | balrog | (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) | |
633 | 18c9b560 | balrog | (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56); |
634 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
635 | 18c9b560 | balrog | NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | |
636 | 18c9b560 | balrog | NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | |
637 | 18c9b560 | balrog | NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | |
638 | 18c9b560 | balrog | NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); |
639 | 18c9b560 | balrog | } |
640 | 18c9b560 | balrog | |
641 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packul_M0_wRn(void) |
642 | 18c9b560 | balrog | { |
643 | 18c9b560 | balrog | M0 = |
644 | 18c9b560 | balrog | (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) | |
645 | 18c9b560 | balrog | (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48); |
646 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
647 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
648 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
649 | 18c9b560 | balrog | } |
650 | 18c9b560 | balrog | |
651 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packuq_M0_wRn(void) |
652 | 18c9b560 | balrog | { |
653 | 18c9b560 | balrog | M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32); |
654 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
655 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
656 | 18c9b560 | balrog | } |
657 | 18c9b560 | balrog | |
658 | 18c9b560 | balrog | /* TODO: Signed-Saturation */
|
659 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packsw_M0_wRn(void) |
660 | 18c9b560 | balrog | { |
661 | 18c9b560 | balrog | M0 = |
662 | 18c9b560 | balrog | (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) | |
663 | 18c9b560 | balrog | (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) | |
664 | 18c9b560 | balrog | (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) | |
665 | 18c9b560 | balrog | (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56); |
666 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
667 | 18c9b560 | balrog | NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | |
668 | 18c9b560 | balrog | NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | |
669 | 18c9b560 | balrog | NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | |
670 | 18c9b560 | balrog | NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); |
671 | 18c9b560 | balrog | } |
672 | 18c9b560 | balrog | |
673 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packsl_M0_wRn(void) |
674 | 18c9b560 | balrog | { |
675 | 18c9b560 | balrog | M0 = |
676 | 18c9b560 | balrog | (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) | |
677 | 18c9b560 | balrog | (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48); |
678 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
679 | 18c9b560 | balrog | NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
680 | 18c9b560 | balrog | NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
681 | 18c9b560 | balrog | } |
682 | 18c9b560 | balrog | |
683 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_packsq_M0_wRn(void) |
684 | 18c9b560 | balrog | { |
685 | 18c9b560 | balrog | M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32); |
686 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
687 | 18c9b560 | balrog | NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
688 | 18c9b560 | balrog | } |
689 | 18c9b560 | balrog | |
690 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void) |
691 | 18c9b560 | balrog | { |
692 | 18c9b560 | balrog | M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1); |
693 | 18c9b560 | balrog | } |
694 | 18c9b560 | balrog | |
695 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void) |
696 | 18c9b560 | balrog | { |
697 | 18c9b560 | balrog | M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) * |
698 | 18c9b560 | balrog | EXTEND16S((T1 >> 0) & 0xffff)); |
699 | 18c9b560 | balrog | M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) * |
700 | 18c9b560 | balrog | EXTEND16S((T1 >> 16) & 0xffff)); |
701 | 18c9b560 | balrog | } |
702 | 18c9b560 | balrog | |
703 | 18c9b560 | balrog | void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void) |
704 | 18c9b560 | balrog | { |
705 | 18c9b560 | balrog | M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *
|
706 | 18c9b560 | balrog | EXTEND16S(T1 & 0xffff));
|
707 | 18c9b560 | balrog | } |