Archipelago » qemu

 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf

 */

    /* Model parameters */

    uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59

    /* Hardware parameters */

typedef struct M48t59ISAState {

    ISADevice busdev;

} M48t59ISAState;

typedef struct M48t59SysBusState {

    SysBusDevice busdev;

} M48t59SysBusState;

/* Fake timer functions */

{

    struct tm tm;

    uint64_t next_time;

    qemu_set_irq(NVRAM->IRQ, 1);

    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&

    qemu_set_irq(NVRAM->IRQ, 0);

}

{

    int diff;

    if (NVRAM->alrm_timer != NULL) {

}

/* RTC management helpers */

{

    qemu_get_timedate(tm, NVRAM->time_offset);

}

{

    NVRAM->time_offset = qemu_timedate_diff(tm);

    set_alarm(NVRAM);

/* Watchdog management */

static void watchdog_cb (void *opaque)

{

    NVRAM->buffer[0x1FF0] |= 0x80;

    if (NVRAM->buffer[0x1FF7] & 0x80) {

    }

}

{

    uint64_t interval; /* in 1/16 seconds */

/* Direct access to NVRAM */

void m48t59_write (void *opaque, uint32_t addr, uint32_t val)

{

    struct tm tm;

    int tmp;

uint32_t m48t59_read (void *opaque, uint32_t addr)

{

    struct tm tm;

    uint32_t retval = 0xFF;

void m48t59_set_addr (void *opaque, uint32_t addr)

{

    NVRAM->addr = addr;

}

void m48t59_toggle_lock (void *opaque, int lock)

{

    NVRAM->lock ^= 1 << lock;

}

/* IO access to NVRAM */

static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)

{

    addr -= NVRAM->io_base;

    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);

static uint32_t NVRAM_readb (void *opaque, uint32_t addr)

{

    uint32_t retval;

    addr -= NVRAM->io_base;

static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    m48t59_write(NVRAM, addr, value & 0xff);

}

static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);

    m48t59_write(NVRAM, addr + 1, value & 0xff);

static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);

    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);

static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)

{

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr);

static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)

{

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 8;

static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)

{

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 24;

static void m48t59_save(QEMUFile *f, void *opaque)

{

    qemu_put_8s(f, &s->lock);

    qemu_put_be16s(f, &s->addr);

static int m48t59_load(QEMUFile *f, void *opaque, int version_id)

{

    if (version_id != 1)

        return -EINVAL;

    return 0;

}

{

    NVRAM->addr = 0;

    NVRAM->lock = 0;

static void m48t59_reset_isa(DeviceState *d)

{

    M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);

    m48t59_reset_common(NVRAM);

}

static void m48t59_reset_sysbus(DeviceState *d)

{

    M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);

    m48t59_reset_common(NVRAM);

}

/* Initialisation routine */

{

    DeviceState *dev;

    SysBusDevice *s;

    return &d->state;

}

{

    M48t59ISAState *d;

    ISADevice *dev;

    dev = isa_create("m48t59_isa");

    qdev_prop_set_uint32(&dev->qdev, "type", type);

    return s;

}

{

    s->buffer = qemu_mallocz(s->size);

    if (s->type == 59) {

static int m48t59_init_isa1(ISADevice *dev)

{

    M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);

    isa_init_irq(dev, &s->IRQ, 8);

    m48t59_init_common(s);

static int m48t59_init1(SysBusDevice *dev)

{

    M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);

    int mem_index;

    sysbus_init_irq(dev, &s->IRQ);

                          uint32_t initrd_image, uint32_t initrd_size,

                          uint32_t NVRAM_image,

                          int width, int height, int depth);

void m48t59_write (void *private, uint32_t addr, uint32_t val);

uint32_t m48t59_read (void *private, uint32_t addr);

void m48t59_toggle_lock (void *private, int lock);

void m48t59_set_addr (void *opaque, uint32_t addr);

#endif /* !NVRAM_H */

/* Fake super-io ports for PREP platform (Intel 82378ZB) */

typedef struct sysctrl_t {

    qemu_irq reset_irq;

    uint8_t state;

    uint8_t syscontrol;

    uint8_t fake_io[2];

    CPUState *env = NULL, *envs[MAX_CPUS];

    char *filename;

    nvram_t nvram;

    int PPC_io_memory;

    int linux_boot, i, nb_nics1, bios_size;

    ram_addr_t ram_offset, bios_offset;

    return 0;

}

                       int width, int height, int depth,

                       int nvram_machine_id, const char *arch)

{

    return 0;

}

{

    unsigned int i;

    uint32_t start, end;

                        const struct hwdef *hwdef)

{

    CPUState *env;

    unsigned int i;

    long initrd_size, kernel_size;

    PCIBus *pci_bus, *pci_bus2, *pci_bus3;