Revision 43ad7e3e hw/e1000.c
| b/hw/e1000.c | ||
|---|---|---|
| 447 | 447 |
// data descriptor |
| 448 | 448 |
tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; |
| 449 | 449 |
tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0; |
| 450 |
} else |
|
| 450 |
} else {
|
|
| 451 | 451 |
// legacy descriptor |
| 452 | 452 |
tp->cptse = 0; |
| 453 |
} |
|
| 453 | 454 |
|
| 454 | 455 |
if (vlan_enabled(s) && is_vlan_txd(txd_lower) && |
| 455 | 456 |
(tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
|
| ... | ... | |
| 685 | 686 |
(void *)(buf + vlan_offset), size); |
| 686 | 687 |
desc.length = cpu_to_le16(size + fcs_len(s)); |
| 687 | 688 |
desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM; |
| 688 |
} else // as per intel docs; skip descriptors with null buf addr |
|
| 689 |
} else { // as per intel docs; skip descriptors with null buf addr
|
|
| 689 | 690 |
DBGOUT(RX, "Null RX descriptor!!\n"); |
| 691 |
} |
|
| 690 | 692 |
cpu_physical_memory_write(base, (void *)&desc, sizeof(desc)); |
| 691 | 693 |
|
| 692 | 694 |
if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) |
| ... | ... | |
| 858 | 860 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 859 | 861 |
val = bswap32(val); |
| 860 | 862 |
#endif |
| 861 |
if (index < NWRITEOPS && macreg_writeops[index]) |
|
| 863 |
if (index < NWRITEOPS && macreg_writeops[index]) {
|
|
| 862 | 864 |
macreg_writeops[index](s, index, val); |
| 863 |
else if (index < NREADOPS && macreg_readops[index])
|
|
| 865 |
} else if (index < NREADOPS && macreg_readops[index]) {
|
|
| 864 | 866 |
DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val); |
| 865 |
else
|
|
| 867 |
} else {
|
|
| 866 | 868 |
DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n", |
| 867 | 869 |
index<<2, val); |
| 870 |
} |
|
| 868 | 871 |
} |
| 869 | 872 |
|
| 870 | 873 |
static void |
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