root / hw / omap_dss.c @ 43bf782b
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1 | 827df9f3 | balrog | /*
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2 | 827df9f3 | balrog | * OMAP2 Display Subsystem.
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3 | 827df9f3 | balrog | *
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4 | 827df9f3 | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | 827df9f3 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 827df9f3 | balrog | *
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7 | 827df9f3 | balrog | * This program is free software; you can redistribute it and/or
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8 | 827df9f3 | balrog | * modify it under the terms of the GNU General Public License as
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9 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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11 | 827df9f3 | balrog | *
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12 | 827df9f3 | balrog | * This program is distributed in the hope that it will be useful,
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13 | 827df9f3 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 827df9f3 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 827df9f3 | balrog | * GNU General Public License for more details.
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16 | 827df9f3 | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 827df9f3 | balrog | */
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20 | 827df9f3 | balrog | #include "hw.h" |
21 | 827df9f3 | balrog | #include "console.h" |
22 | 827df9f3 | balrog | #include "omap.h" |
23 | 827df9f3 | balrog | |
24 | 827df9f3 | balrog | struct omap_dss_s {
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25 | 827df9f3 | balrog | qemu_irq irq; |
26 | 827df9f3 | balrog | qemu_irq drq; |
27 | 827df9f3 | balrog | DisplayState *state; |
28 | 827df9f3 | balrog | |
29 | 827df9f3 | balrog | int autoidle;
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30 | 827df9f3 | balrog | int control;
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31 | 827df9f3 | balrog | int enable;
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32 | 827df9f3 | balrog | |
33 | 827df9f3 | balrog | struct omap_dss_panel_s {
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34 | 827df9f3 | balrog | int enable;
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35 | 827df9f3 | balrog | int nx;
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36 | 827df9f3 | balrog | int ny;
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37 | 827df9f3 | balrog | |
38 | 827df9f3 | balrog | int x;
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39 | 827df9f3 | balrog | int y;
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40 | 827df9f3 | balrog | } dig, lcd; |
41 | 827df9f3 | balrog | |
42 | 827df9f3 | balrog | struct {
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43 | 827df9f3 | balrog | uint32_t idlemode; |
44 | 827df9f3 | balrog | uint32_t irqst; |
45 | 827df9f3 | balrog | uint32_t irqen; |
46 | 827df9f3 | balrog | uint32_t control; |
47 | 827df9f3 | balrog | uint32_t config; |
48 | 827df9f3 | balrog | uint32_t capable; |
49 | f3d8b1eb | aurel32 | uint32_t timing[4];
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50 | 827df9f3 | balrog | int line;
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51 | 827df9f3 | balrog | uint32_t bg[2];
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52 | 827df9f3 | balrog | uint32_t trans[2];
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53 | 827df9f3 | balrog | |
54 | 827df9f3 | balrog | struct omap_dss_plane_s {
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55 | 827df9f3 | balrog | int enable;
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56 | 827df9f3 | balrog | int bpp;
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57 | 827df9f3 | balrog | int posx;
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58 | 827df9f3 | balrog | int posy;
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59 | 827df9f3 | balrog | int nx;
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60 | 827df9f3 | balrog | int ny;
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61 | 827df9f3 | balrog | |
62 | 827df9f3 | balrog | target_phys_addr_t addr[3];
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63 | 827df9f3 | balrog | |
64 | 827df9f3 | balrog | uint32_t attr; |
65 | 827df9f3 | balrog | uint32_t tresh; |
66 | 827df9f3 | balrog | int rowinc;
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67 | 827df9f3 | balrog | int colinc;
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68 | 827df9f3 | balrog | int wininc;
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69 | 827df9f3 | balrog | } l[3];
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70 | 827df9f3 | balrog | |
71 | 827df9f3 | balrog | int invalidate;
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72 | 827df9f3 | balrog | uint16_t palette[256];
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73 | 827df9f3 | balrog | } dispc; |
74 | 827df9f3 | balrog | |
75 | 827df9f3 | balrog | struct {
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76 | 827df9f3 | balrog | int idlemode;
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77 | 827df9f3 | balrog | uint32_t control; |
78 | 827df9f3 | balrog | int enable;
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79 | 827df9f3 | balrog | int pixels;
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80 | 827df9f3 | balrog | int busy;
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81 | 827df9f3 | balrog | int skiplines;
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82 | 827df9f3 | balrog | uint16_t rxbuf; |
83 | 827df9f3 | balrog | uint32_t config[2];
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84 | 827df9f3 | balrog | uint32_t time[4];
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85 | 827df9f3 | balrog | uint32_t data[6];
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86 | 827df9f3 | balrog | uint16_t vsync; |
87 | 827df9f3 | balrog | uint16_t hsync; |
88 | 827df9f3 | balrog | struct rfbi_chip_s *chip[2]; |
89 | 827df9f3 | balrog | } rfbi; |
90 | 827df9f3 | balrog | }; |
91 | 827df9f3 | balrog | |
92 | 827df9f3 | balrog | static void omap_dispc_interrupt_update(struct omap_dss_s *s) |
93 | 827df9f3 | balrog | { |
94 | 827df9f3 | balrog | qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen); |
95 | 827df9f3 | balrog | } |
96 | 827df9f3 | balrog | |
97 | 827df9f3 | balrog | static void omap_rfbi_reset(struct omap_dss_s *s) |
98 | 827df9f3 | balrog | { |
99 | 827df9f3 | balrog | s->rfbi.idlemode = 0;
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100 | 827df9f3 | balrog | s->rfbi.control = 2;
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101 | 827df9f3 | balrog | s->rfbi.enable = 0;
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102 | 827df9f3 | balrog | s->rfbi.pixels = 0;
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103 | 827df9f3 | balrog | s->rfbi.skiplines = 0;
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104 | 827df9f3 | balrog | s->rfbi.busy = 0;
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105 | 827df9f3 | balrog | s->rfbi.config[0] = 0x00310000; |
106 | 827df9f3 | balrog | s->rfbi.config[1] = 0x00310000; |
107 | 827df9f3 | balrog | s->rfbi.time[0] = 0; |
108 | 827df9f3 | balrog | s->rfbi.time[1] = 0; |
109 | 827df9f3 | balrog | s->rfbi.time[2] = 0; |
110 | 827df9f3 | balrog | s->rfbi.time[3] = 0; |
111 | 827df9f3 | balrog | s->rfbi.data[0] = 0; |
112 | 827df9f3 | balrog | s->rfbi.data[1] = 0; |
113 | 827df9f3 | balrog | s->rfbi.data[2] = 0; |
114 | 827df9f3 | balrog | s->rfbi.data[3] = 0; |
115 | 827df9f3 | balrog | s->rfbi.data[4] = 0; |
116 | 827df9f3 | balrog | s->rfbi.data[5] = 0; |
117 | 827df9f3 | balrog | s->rfbi.vsync = 0;
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118 | 827df9f3 | balrog | s->rfbi.hsync = 0;
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119 | 827df9f3 | balrog | } |
120 | 827df9f3 | balrog | |
121 | 827df9f3 | balrog | void omap_dss_reset(struct omap_dss_s *s) |
122 | 827df9f3 | balrog | { |
123 | 827df9f3 | balrog | s->autoidle = 0;
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124 | 827df9f3 | balrog | s->control = 0;
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125 | 827df9f3 | balrog | s->enable = 0;
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126 | 827df9f3 | balrog | |
127 | 827df9f3 | balrog | s->dig.enable = 0;
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128 | 827df9f3 | balrog | s->dig.nx = 1;
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129 | 827df9f3 | balrog | s->dig.ny = 1;
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130 | 827df9f3 | balrog | |
131 | 827df9f3 | balrog | s->lcd.enable = 0;
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132 | 827df9f3 | balrog | s->lcd.nx = 1;
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133 | 827df9f3 | balrog | s->lcd.ny = 1;
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134 | 827df9f3 | balrog | |
135 | 827df9f3 | balrog | s->dispc.idlemode = 0;
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136 | 827df9f3 | balrog | s->dispc.irqst = 0;
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137 | 827df9f3 | balrog | s->dispc.irqen = 0;
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138 | 827df9f3 | balrog | s->dispc.control = 0;
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139 | 827df9f3 | balrog | s->dispc.config = 0;
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140 | 827df9f3 | balrog | s->dispc.capable = 0x161;
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141 | 827df9f3 | balrog | s->dispc.timing[0] = 0; |
142 | 827df9f3 | balrog | s->dispc.timing[1] = 0; |
143 | 827df9f3 | balrog | s->dispc.timing[2] = 0; |
144 | f3d8b1eb | aurel32 | s->dispc.timing[3] = 0; |
145 | 827df9f3 | balrog | s->dispc.line = 0;
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146 | 827df9f3 | balrog | s->dispc.bg[0] = 0; |
147 | 827df9f3 | balrog | s->dispc.bg[1] = 0; |
148 | 827df9f3 | balrog | s->dispc.trans[0] = 0; |
149 | 827df9f3 | balrog | s->dispc.trans[1] = 0; |
150 | 827df9f3 | balrog | |
151 | 827df9f3 | balrog | s->dispc.l[0].enable = 0; |
152 | 827df9f3 | balrog | s->dispc.l[0].bpp = 0; |
153 | 827df9f3 | balrog | s->dispc.l[0].addr[0] = 0; |
154 | 827df9f3 | balrog | s->dispc.l[0].addr[1] = 0; |
155 | 827df9f3 | balrog | s->dispc.l[0].addr[2] = 0; |
156 | 827df9f3 | balrog | s->dispc.l[0].posx = 0; |
157 | 827df9f3 | balrog | s->dispc.l[0].posy = 0; |
158 | 827df9f3 | balrog | s->dispc.l[0].nx = 1; |
159 | 827df9f3 | balrog | s->dispc.l[0].ny = 1; |
160 | 827df9f3 | balrog | s->dispc.l[0].attr = 0; |
161 | 827df9f3 | balrog | s->dispc.l[0].tresh = 0; |
162 | 827df9f3 | balrog | s->dispc.l[0].rowinc = 1; |
163 | 827df9f3 | balrog | s->dispc.l[0].colinc = 1; |
164 | 827df9f3 | balrog | s->dispc.l[0].wininc = 0; |
165 | 827df9f3 | balrog | |
166 | 827df9f3 | balrog | omap_rfbi_reset(s); |
167 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
168 | 827df9f3 | balrog | } |
169 | 827df9f3 | balrog | |
170 | 827df9f3 | balrog | static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) |
171 | 827df9f3 | balrog | { |
172 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
173 | 827df9f3 | balrog | |
174 | 8da3ff18 | pbrook | switch (addr) {
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175 | 827df9f3 | balrog | case 0x00: /* DSS_REVISIONNUMBER */ |
176 | 827df9f3 | balrog | return 0x20; |
177 | 827df9f3 | balrog | |
178 | 827df9f3 | balrog | case 0x10: /* DSS_SYSCONFIG */ |
179 | 827df9f3 | balrog | return s->autoidle;
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180 | 827df9f3 | balrog | |
181 | 827df9f3 | balrog | case 0x14: /* DSS_SYSSTATUS */ |
182 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
183 | 827df9f3 | balrog | |
184 | 827df9f3 | balrog | case 0x40: /* DSS_CONTROL */ |
185 | 827df9f3 | balrog | return s->control;
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186 | 827df9f3 | balrog | |
187 | 827df9f3 | balrog | case 0x50: /* DSS_PSA_LCD_REG_1 */ |
188 | 827df9f3 | balrog | case 0x54: /* DSS_PSA_LCD_REG_2 */ |
189 | 827df9f3 | balrog | case 0x58: /* DSS_PSA_VIDEO_REG */ |
190 | 827df9f3 | balrog | /* TODO: fake some values when appropriate s->control bits are set */
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191 | 827df9f3 | balrog | return 0; |
192 | 827df9f3 | balrog | |
193 | 827df9f3 | balrog | case 0x5c: /* DSS_STATUS */ |
194 | 827df9f3 | balrog | return 1 + (s->control & 1); |
195 | 827df9f3 | balrog | |
196 | 827df9f3 | balrog | default:
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197 | 827df9f3 | balrog | break;
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198 | 827df9f3 | balrog | } |
199 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
200 | 827df9f3 | balrog | return 0; |
201 | 827df9f3 | balrog | } |
202 | 827df9f3 | balrog | |
203 | 827df9f3 | balrog | static void omap_diss_write(void *opaque, target_phys_addr_t addr, |
204 | 827df9f3 | balrog | uint32_t value) |
205 | 827df9f3 | balrog | { |
206 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
207 | 827df9f3 | balrog | |
208 | 8da3ff18 | pbrook | switch (addr) {
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209 | 827df9f3 | balrog | case 0x00: /* DSS_REVISIONNUMBER */ |
210 | 827df9f3 | balrog | case 0x14: /* DSS_SYSSTATUS */ |
211 | 827df9f3 | balrog | case 0x50: /* DSS_PSA_LCD_REG_1 */ |
212 | 827df9f3 | balrog | case 0x54: /* DSS_PSA_LCD_REG_2 */ |
213 | 827df9f3 | balrog | case 0x58: /* DSS_PSA_VIDEO_REG */ |
214 | 827df9f3 | balrog | case 0x5c: /* DSS_STATUS */ |
215 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
216 | 827df9f3 | balrog | break;
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217 | 827df9f3 | balrog | |
218 | 827df9f3 | balrog | case 0x10: /* DSS_SYSCONFIG */ |
219 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
220 | 827df9f3 | balrog | omap_dss_reset(s); |
221 | 827df9f3 | balrog | s->autoidle = value & 1;
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222 | 827df9f3 | balrog | break;
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223 | 827df9f3 | balrog | |
224 | 827df9f3 | balrog | case 0x40: /* DSS_CONTROL */ |
225 | 827df9f3 | balrog | s->control = value & 0x3dd;
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226 | 827df9f3 | balrog | break;
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227 | 827df9f3 | balrog | |
228 | 827df9f3 | balrog | default:
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229 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
230 | 827df9f3 | balrog | } |
231 | 827df9f3 | balrog | } |
232 | 827df9f3 | balrog | |
233 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_diss1_readfn[] = { |
234 | 827df9f3 | balrog | omap_badwidth_read32, |
235 | 827df9f3 | balrog | omap_badwidth_read32, |
236 | 827df9f3 | balrog | omap_diss_read, |
237 | 827df9f3 | balrog | }; |
238 | 827df9f3 | balrog | |
239 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_diss1_writefn[] = { |
240 | 827df9f3 | balrog | omap_badwidth_write32, |
241 | 827df9f3 | balrog | omap_badwidth_write32, |
242 | 827df9f3 | balrog | omap_diss_write, |
243 | 827df9f3 | balrog | }; |
244 | 827df9f3 | balrog | |
245 | 827df9f3 | balrog | static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) |
246 | 827df9f3 | balrog | { |
247 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
248 | 827df9f3 | balrog | |
249 | 8da3ff18 | pbrook | switch (addr) {
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250 | 827df9f3 | balrog | case 0x000: /* DISPC_REVISION */ |
251 | 827df9f3 | balrog | return 0x20; |
252 | 827df9f3 | balrog | |
253 | 827df9f3 | balrog | case 0x010: /* DISPC_SYSCONFIG */ |
254 | 827df9f3 | balrog | return s->dispc.idlemode;
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255 | 827df9f3 | balrog | |
256 | 827df9f3 | balrog | case 0x014: /* DISPC_SYSSTATUS */ |
257 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
258 | 827df9f3 | balrog | |
259 | 827df9f3 | balrog | case 0x018: /* DISPC_IRQSTATUS */ |
260 | 827df9f3 | balrog | return s->dispc.irqst;
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261 | 827df9f3 | balrog | |
262 | 827df9f3 | balrog | case 0x01c: /* DISPC_IRQENABLE */ |
263 | 827df9f3 | balrog | return s->dispc.irqen;
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264 | 827df9f3 | balrog | |
265 | 827df9f3 | balrog | case 0x040: /* DISPC_CONTROL */ |
266 | 827df9f3 | balrog | return s->dispc.control;
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267 | 827df9f3 | balrog | |
268 | 827df9f3 | balrog | case 0x044: /* DISPC_CONFIG */ |
269 | 827df9f3 | balrog | return s->dispc.config;
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270 | 827df9f3 | balrog | |
271 | 827df9f3 | balrog | case 0x048: /* DISPC_CAPABLE */ |
272 | 827df9f3 | balrog | return s->dispc.capable;
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273 | 827df9f3 | balrog | |
274 | 827df9f3 | balrog | case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
275 | 827df9f3 | balrog | return s->dispc.bg[0]; |
276 | 827df9f3 | balrog | case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
277 | 827df9f3 | balrog | return s->dispc.bg[1]; |
278 | 827df9f3 | balrog | case 0x054: /* DISPC_TRANS_COLOR0 */ |
279 | 827df9f3 | balrog | return s->dispc.trans[0]; |
280 | 827df9f3 | balrog | case 0x058: /* DISPC_TRANS_COLOR1 */ |
281 | 827df9f3 | balrog | return s->dispc.trans[1]; |
282 | 827df9f3 | balrog | |
283 | 827df9f3 | balrog | case 0x05c: /* DISPC_LINE_STATUS */ |
284 | 827df9f3 | balrog | return 0x7ff; |
285 | 827df9f3 | balrog | case 0x060: /* DISPC_LINE_NUMBER */ |
286 | 827df9f3 | balrog | return s->dispc.line;
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287 | 827df9f3 | balrog | |
288 | 827df9f3 | balrog | case 0x064: /* DISPC_TIMING_H */ |
289 | 827df9f3 | balrog | return s->dispc.timing[0]; |
290 | 827df9f3 | balrog | case 0x068: /* DISPC_TIMING_V */ |
291 | 827df9f3 | balrog | return s->dispc.timing[1]; |
292 | 827df9f3 | balrog | case 0x06c: /* DISPC_POL_FREQ */ |
293 | 827df9f3 | balrog | return s->dispc.timing[2]; |
294 | 827df9f3 | balrog | case 0x070: /* DISPC_DIVISOR */ |
295 | 827df9f3 | balrog | return s->dispc.timing[3]; |
296 | 827df9f3 | balrog | |
297 | 827df9f3 | balrog | case 0x078: /* DISPC_SIZE_DIG */ |
298 | 827df9f3 | balrog | return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1); |
299 | 827df9f3 | balrog | case 0x07c: /* DISPC_SIZE_LCD */ |
300 | 827df9f3 | balrog | return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1); |
301 | 827df9f3 | balrog | |
302 | 827df9f3 | balrog | case 0x080: /* DISPC_GFX_BA0 */ |
303 | 827df9f3 | balrog | return s->dispc.l[0].addr[0]; |
304 | 827df9f3 | balrog | case 0x084: /* DISPC_GFX_BA1 */ |
305 | 827df9f3 | balrog | return s->dispc.l[0].addr[1]; |
306 | 827df9f3 | balrog | case 0x088: /* DISPC_GFX_POSITION */ |
307 | 827df9f3 | balrog | return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx; |
308 | 827df9f3 | balrog | case 0x08c: /* DISPC_GFX_SIZE */ |
309 | 827df9f3 | balrog | return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1); |
310 | 827df9f3 | balrog | case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
311 | 827df9f3 | balrog | return s->dispc.l[0].attr; |
312 | 827df9f3 | balrog | case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
313 | 827df9f3 | balrog | return s->dispc.l[0].tresh; |
314 | 827df9f3 | balrog | case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */ |
315 | 827df9f3 | balrog | return 256; |
316 | 827df9f3 | balrog | case 0x0ac: /* DISPC_GFX_ROW_INC */ |
317 | 827df9f3 | balrog | return s->dispc.l[0].rowinc; |
318 | 827df9f3 | balrog | case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
319 | 827df9f3 | balrog | return s->dispc.l[0].colinc; |
320 | 827df9f3 | balrog | case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
321 | 827df9f3 | balrog | return s->dispc.l[0].wininc; |
322 | 827df9f3 | balrog | case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
323 | 827df9f3 | balrog | return s->dispc.l[0].addr[2]; |
324 | 827df9f3 | balrog | |
325 | 827df9f3 | balrog | case 0x0bc: /* DISPC_VID1_BA0 */ |
326 | 827df9f3 | balrog | case 0x0c0: /* DISPC_VID1_BA1 */ |
327 | 827df9f3 | balrog | case 0x0c4: /* DISPC_VID1_POSITION */ |
328 | 827df9f3 | balrog | case 0x0c8: /* DISPC_VID1_SIZE */ |
329 | 827df9f3 | balrog | case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
330 | 827df9f3 | balrog | case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
331 | 827df9f3 | balrog | case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */ |
332 | 827df9f3 | balrog | case 0x0d8: /* DISPC_VID1_ROW_INC */ |
333 | 827df9f3 | balrog | case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
334 | 827df9f3 | balrog | case 0x0e0: /* DISPC_VID1_FIR */ |
335 | 827df9f3 | balrog | case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
336 | 827df9f3 | balrog | case 0x0e8: /* DISPC_VID1_ACCU0 */ |
337 | 827df9f3 | balrog | case 0x0ec: /* DISPC_VID1_ACCU1 */ |
338 | 827df9f3 | balrog | case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
339 | 827df9f3 | balrog | case 0x14c: /* DISPC_VID2_BA0 */ |
340 | 827df9f3 | balrog | case 0x150: /* DISPC_VID2_BA1 */ |
341 | 827df9f3 | balrog | case 0x154: /* DISPC_VID2_POSITION */ |
342 | 827df9f3 | balrog | case 0x158: /* DISPC_VID2_SIZE */ |
343 | 827df9f3 | balrog | case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
344 | 827df9f3 | balrog | case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
345 | 827df9f3 | balrog | case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */ |
346 | 827df9f3 | balrog | case 0x168: /* DISPC_VID2_ROW_INC */ |
347 | 827df9f3 | balrog | case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
348 | 827df9f3 | balrog | case 0x170: /* DISPC_VID2_FIR */ |
349 | 827df9f3 | balrog | case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
350 | 827df9f3 | balrog | case 0x178: /* DISPC_VID2_ACCU0 */ |
351 | 827df9f3 | balrog | case 0x17c: /* DISPC_VID2_ACCU1 */ |
352 | 827df9f3 | balrog | case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
353 | 827df9f3 | balrog | case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
354 | 827df9f3 | balrog | case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
355 | 827df9f3 | balrog | case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
356 | 827df9f3 | balrog | return 0; |
357 | 827df9f3 | balrog | |
358 | 827df9f3 | balrog | default:
|
359 | 827df9f3 | balrog | break;
|
360 | 827df9f3 | balrog | } |
361 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
362 | 827df9f3 | balrog | return 0; |
363 | 827df9f3 | balrog | } |
364 | 827df9f3 | balrog | |
365 | 827df9f3 | balrog | static void omap_disc_write(void *opaque, target_phys_addr_t addr, |
366 | 827df9f3 | balrog | uint32_t value) |
367 | 827df9f3 | balrog | { |
368 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
369 | 827df9f3 | balrog | |
370 | 8da3ff18 | pbrook | switch (addr) {
|
371 | 827df9f3 | balrog | case 0x010: /* DISPC_SYSCONFIG */ |
372 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
373 | 827df9f3 | balrog | omap_dss_reset(s); |
374 | 827df9f3 | balrog | s->dispc.idlemode = value & 0x301b;
|
375 | 827df9f3 | balrog | break;
|
376 | 827df9f3 | balrog | |
377 | 827df9f3 | balrog | case 0x018: /* DISPC_IRQSTATUS */ |
378 | 827df9f3 | balrog | s->dispc.irqst &= ~value; |
379 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
380 | 827df9f3 | balrog | break;
|
381 | 827df9f3 | balrog | |
382 | 827df9f3 | balrog | case 0x01c: /* DISPC_IRQENABLE */ |
383 | 827df9f3 | balrog | s->dispc.irqen = value & 0xffff;
|
384 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
385 | 827df9f3 | balrog | break;
|
386 | 827df9f3 | balrog | |
387 | 827df9f3 | balrog | case 0x040: /* DISPC_CONTROL */ |
388 | 827df9f3 | balrog | s->dispc.control = value & 0x07ff9fff;
|
389 | 827df9f3 | balrog | s->dig.enable = (value >> 1) & 1; |
390 | 827df9f3 | balrog | s->lcd.enable = (value >> 0) & 1; |
391 | 827df9f3 | balrog | if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */ |
392 | 827df9f3 | balrog | if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) |
393 | 827df9f3 | balrog | fprintf(stderr, "%s: Overlay Optimization when no overlay "
|
394 | 827df9f3 | balrog | "region effectively exists leads to "
|
395 | 827df9f3 | balrog | "unpredictable behaviour!\n", __FUNCTION__);
|
396 | 827df9f3 | balrog | if (value & (1 << 6)) { /* GODIGITAL */ |
397 | 827df9f3 | balrog | /* XXX: Shadowed fields are:
|
398 | 827df9f3 | balrog | * s->dispc.config
|
399 | 827df9f3 | balrog | * s->dispc.capable
|
400 | 827df9f3 | balrog | * s->dispc.bg[0]
|
401 | 827df9f3 | balrog | * s->dispc.bg[1]
|
402 | 827df9f3 | balrog | * s->dispc.trans[0]
|
403 | 827df9f3 | balrog | * s->dispc.trans[1]
|
404 | 827df9f3 | balrog | * s->dispc.line
|
405 | 827df9f3 | balrog | * s->dispc.timing[0]
|
406 | 827df9f3 | balrog | * s->dispc.timing[1]
|
407 | 827df9f3 | balrog | * s->dispc.timing[2]
|
408 | 827df9f3 | balrog | * s->dispc.timing[3]
|
409 | 827df9f3 | balrog | * s->lcd.nx
|
410 | 827df9f3 | balrog | * s->lcd.ny
|
411 | 827df9f3 | balrog | * s->dig.nx
|
412 | 827df9f3 | balrog | * s->dig.ny
|
413 | 827df9f3 | balrog | * s->dispc.l[0].addr[0]
|
414 | 827df9f3 | balrog | * s->dispc.l[0].addr[1]
|
415 | 827df9f3 | balrog | * s->dispc.l[0].addr[2]
|
416 | 827df9f3 | balrog | * s->dispc.l[0].posx
|
417 | 827df9f3 | balrog | * s->dispc.l[0].posy
|
418 | 827df9f3 | balrog | * s->dispc.l[0].nx
|
419 | 827df9f3 | balrog | * s->dispc.l[0].ny
|
420 | 827df9f3 | balrog | * s->dispc.l[0].tresh
|
421 | 827df9f3 | balrog | * s->dispc.l[0].rowinc
|
422 | 827df9f3 | balrog | * s->dispc.l[0].colinc
|
423 | 827df9f3 | balrog | * s->dispc.l[0].wininc
|
424 | 827df9f3 | balrog | * All they need to be loaded here from their shadow registers.
|
425 | 827df9f3 | balrog | */
|
426 | 827df9f3 | balrog | } |
427 | 827df9f3 | balrog | if (value & (1 << 5)) { /* GOLCD */ |
428 | 827df9f3 | balrog | /* XXX: Likewise for LCD here. */
|
429 | 827df9f3 | balrog | } |
430 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
431 | 827df9f3 | balrog | break;
|
432 | 827df9f3 | balrog | |
433 | 827df9f3 | balrog | case 0x044: /* DISPC_CONFIG */ |
434 | 827df9f3 | balrog | s->dispc.config = value & 0x3fff;
|
435 | 827df9f3 | balrog | /* XXX:
|
436 | 827df9f3 | balrog | * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
|
437 | 827df9f3 | balrog | * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
|
438 | 827df9f3 | balrog | */
|
439 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
440 | 827df9f3 | balrog | break;
|
441 | 827df9f3 | balrog | |
442 | 827df9f3 | balrog | case 0x048: /* DISPC_CAPABLE */ |
443 | 827df9f3 | balrog | s->dispc.capable = value & 0x3ff;
|
444 | 827df9f3 | balrog | break;
|
445 | 827df9f3 | balrog | |
446 | 827df9f3 | balrog | case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
447 | 827df9f3 | balrog | s->dispc.bg[0] = value & 0xffffff; |
448 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
449 | 827df9f3 | balrog | break;
|
450 | 827df9f3 | balrog | case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
451 | 827df9f3 | balrog | s->dispc.bg[1] = value & 0xffffff; |
452 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
453 | 827df9f3 | balrog | break;
|
454 | 827df9f3 | balrog | case 0x054: /* DISPC_TRANS_COLOR0 */ |
455 | 827df9f3 | balrog | s->dispc.trans[0] = value & 0xffffff; |
456 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
457 | 827df9f3 | balrog | break;
|
458 | 827df9f3 | balrog | case 0x058: /* DISPC_TRANS_COLOR1 */ |
459 | 827df9f3 | balrog | s->dispc.trans[1] = value & 0xffffff; |
460 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
461 | 827df9f3 | balrog | break;
|
462 | 827df9f3 | balrog | |
463 | 827df9f3 | balrog | case 0x060: /* DISPC_LINE_NUMBER */ |
464 | 827df9f3 | balrog | s->dispc.line = value & 0x7ff;
|
465 | 827df9f3 | balrog | break;
|
466 | 827df9f3 | balrog | |
467 | 827df9f3 | balrog | case 0x064: /* DISPC_TIMING_H */ |
468 | 827df9f3 | balrog | s->dispc.timing[0] = value & 0x0ff0ff3f; |
469 | 827df9f3 | balrog | break;
|
470 | 827df9f3 | balrog | case 0x068: /* DISPC_TIMING_V */ |
471 | 827df9f3 | balrog | s->dispc.timing[1] = value & 0x0ff0ff3f; |
472 | 827df9f3 | balrog | break;
|
473 | 827df9f3 | balrog | case 0x06c: /* DISPC_POL_FREQ */ |
474 | 827df9f3 | balrog | s->dispc.timing[2] = value & 0x0003ffff; |
475 | 827df9f3 | balrog | break;
|
476 | 827df9f3 | balrog | case 0x070: /* DISPC_DIVISOR */ |
477 | 827df9f3 | balrog | s->dispc.timing[3] = value & 0x00ff00ff; |
478 | 827df9f3 | balrog | break;
|
479 | 827df9f3 | balrog | |
480 | 827df9f3 | balrog | case 0x078: /* DISPC_SIZE_DIG */ |
481 | 827df9f3 | balrog | s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
482 | 827df9f3 | balrog | s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
483 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
484 | 827df9f3 | balrog | break;
|
485 | 827df9f3 | balrog | case 0x07c: /* DISPC_SIZE_LCD */ |
486 | 827df9f3 | balrog | s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
487 | 827df9f3 | balrog | s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
488 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
489 | 827df9f3 | balrog | break;
|
490 | 827df9f3 | balrog | case 0x080: /* DISPC_GFX_BA0 */ |
491 | 827df9f3 | balrog | s->dispc.l[0].addr[0] = (target_phys_addr_t) value; |
492 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
493 | 827df9f3 | balrog | break;
|
494 | 827df9f3 | balrog | case 0x084: /* DISPC_GFX_BA1 */ |
495 | 827df9f3 | balrog | s->dispc.l[0].addr[1] = (target_phys_addr_t) value; |
496 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
497 | 827df9f3 | balrog | break;
|
498 | 827df9f3 | balrog | case 0x088: /* DISPC_GFX_POSITION */ |
499 | 827df9f3 | balrog | s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */ |
500 | 827df9f3 | balrog | s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */ |
501 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
502 | 827df9f3 | balrog | break;
|
503 | 827df9f3 | balrog | case 0x08c: /* DISPC_GFX_SIZE */ |
504 | 827df9f3 | balrog | s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */ |
505 | 827df9f3 | balrog | s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */ |
506 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
507 | 827df9f3 | balrog | break;
|
508 | 827df9f3 | balrog | case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
509 | 827df9f3 | balrog | s->dispc.l[0].attr = value & 0x7ff; |
510 | 827df9f3 | balrog | if (value & (3 << 9)) |
511 | 827df9f3 | balrog | fprintf(stderr, "%s: Big-endian pixel format not supported\n",
|
512 | 827df9f3 | balrog | __FUNCTION__); |
513 | 827df9f3 | balrog | s->dispc.l[0].enable = value & 1; |
514 | 827df9f3 | balrog | s->dispc.l[0].bpp = (value >> 1) & 0xf; |
515 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
516 | 827df9f3 | balrog | break;
|
517 | 827df9f3 | balrog | case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
518 | 827df9f3 | balrog | s->dispc.l[0].tresh = value & 0x01ff01ff; |
519 | 827df9f3 | balrog | break;
|
520 | 827df9f3 | balrog | case 0x0ac: /* DISPC_GFX_ROW_INC */ |
521 | 827df9f3 | balrog | s->dispc.l[0].rowinc = value;
|
522 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
523 | 827df9f3 | balrog | break;
|
524 | 827df9f3 | balrog | case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
525 | 827df9f3 | balrog | s->dispc.l[0].colinc = value;
|
526 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
527 | 827df9f3 | balrog | break;
|
528 | 827df9f3 | balrog | case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
529 | 827df9f3 | balrog | s->dispc.l[0].wininc = value;
|
530 | 827df9f3 | balrog | break;
|
531 | 827df9f3 | balrog | case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
532 | 827df9f3 | balrog | s->dispc.l[0].addr[2] = (target_phys_addr_t) value; |
533 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
534 | 827df9f3 | balrog | break;
|
535 | 827df9f3 | balrog | |
536 | 827df9f3 | balrog | case 0x0bc: /* DISPC_VID1_BA0 */ |
537 | 827df9f3 | balrog | case 0x0c0: /* DISPC_VID1_BA1 */ |
538 | 827df9f3 | balrog | case 0x0c4: /* DISPC_VID1_POSITION */ |
539 | 827df9f3 | balrog | case 0x0c8: /* DISPC_VID1_SIZE */ |
540 | 827df9f3 | balrog | case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
541 | 827df9f3 | balrog | case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
542 | 827df9f3 | balrog | case 0x0d8: /* DISPC_VID1_ROW_INC */ |
543 | 827df9f3 | balrog | case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
544 | 827df9f3 | balrog | case 0x0e0: /* DISPC_VID1_FIR */ |
545 | 827df9f3 | balrog | case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
546 | 827df9f3 | balrog | case 0x0e8: /* DISPC_VID1_ACCU0 */ |
547 | 827df9f3 | balrog | case 0x0ec: /* DISPC_VID1_ACCU1 */ |
548 | 827df9f3 | balrog | case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
549 | 827df9f3 | balrog | case 0x14c: /* DISPC_VID2_BA0 */ |
550 | 827df9f3 | balrog | case 0x150: /* DISPC_VID2_BA1 */ |
551 | 827df9f3 | balrog | case 0x154: /* DISPC_VID2_POSITION */ |
552 | 827df9f3 | balrog | case 0x158: /* DISPC_VID2_SIZE */ |
553 | 827df9f3 | balrog | case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
554 | 827df9f3 | balrog | case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
555 | 827df9f3 | balrog | case 0x168: /* DISPC_VID2_ROW_INC */ |
556 | 827df9f3 | balrog | case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
557 | 827df9f3 | balrog | case 0x170: /* DISPC_VID2_FIR */ |
558 | 827df9f3 | balrog | case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
559 | 827df9f3 | balrog | case 0x178: /* DISPC_VID2_ACCU0 */ |
560 | 827df9f3 | balrog | case 0x17c: /* DISPC_VID2_ACCU1 */ |
561 | 827df9f3 | balrog | case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
562 | 827df9f3 | balrog | case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
563 | 827df9f3 | balrog | case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
564 | 827df9f3 | balrog | case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
565 | 827df9f3 | balrog | break;
|
566 | 827df9f3 | balrog | |
567 | 827df9f3 | balrog | default:
|
568 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
569 | 827df9f3 | balrog | } |
570 | 827df9f3 | balrog | } |
571 | 827df9f3 | balrog | |
572 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_disc1_readfn[] = { |
573 | 827df9f3 | balrog | omap_badwidth_read32, |
574 | 827df9f3 | balrog | omap_badwidth_read32, |
575 | 827df9f3 | balrog | omap_disc_read, |
576 | 827df9f3 | balrog | }; |
577 | 827df9f3 | balrog | |
578 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_disc1_writefn[] = { |
579 | 827df9f3 | balrog | omap_badwidth_write32, |
580 | 827df9f3 | balrog | omap_badwidth_write32, |
581 | 827df9f3 | balrog | omap_disc_write, |
582 | 827df9f3 | balrog | }; |
583 | 827df9f3 | balrog | |
584 | 827df9f3 | balrog | static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
585 | 827df9f3 | balrog | { |
586 | 827df9f3 | balrog | if (!s->rfbi.busy)
|
587 | 827df9f3 | balrog | return;
|
588 | 827df9f3 | balrog | |
589 | 827df9f3 | balrog | /* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
|
590 | 827df9f3 | balrog | |
591 | 827df9f3 | balrog | s->rfbi.busy = 0;
|
592 | 827df9f3 | balrog | } |
593 | 827df9f3 | balrog | |
594 | 827df9f3 | balrog | static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
595 | 827df9f3 | balrog | { |
596 | 827df9f3 | balrog | void *data;
|
597 | 5c130f65 | pbrook | target_phys_addr_t len; |
598 | 5c130f65 | pbrook | target_phys_addr_t data_addr; |
599 | 827df9f3 | balrog | int pitch;
|
600 | 5c130f65 | pbrook | static void *bounce_buffer; |
601 | 5c130f65 | pbrook | static target_phys_addr_t bounce_len;
|
602 | 827df9f3 | balrog | |
603 | 827df9f3 | balrog | if (!s->rfbi.enable || s->rfbi.busy)
|
604 | 827df9f3 | balrog | return;
|
605 | 827df9f3 | balrog | |
606 | 827df9f3 | balrog | if (s->rfbi.control & (1 << 1)) { /* BYPASS */ |
607 | 827df9f3 | balrog | /* TODO: in non-Bypass mode we probably need to just assert the
|
608 | 827df9f3 | balrog | * DRQ and wait for DMA to write the pixels. */
|
609 | 827df9f3 | balrog | fprintf(stderr, "%s: Bypass mode unimplemented\n", __FUNCTION__);
|
610 | 827df9f3 | balrog | return;
|
611 | 827df9f3 | balrog | } |
612 | 827df9f3 | balrog | |
613 | 827df9f3 | balrog | if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */ |
614 | 827df9f3 | balrog | return;
|
615 | 827df9f3 | balrog | /* TODO: check that LCD output is enabled in DISPC. */
|
616 | 827df9f3 | balrog | |
617 | 827df9f3 | balrog | s->rfbi.busy = 1;
|
618 | 827df9f3 | balrog | |
619 | 5c130f65 | pbrook | len = s->rfbi.pixels * 2;
|
620 | 5c130f65 | pbrook | |
621 | 5c130f65 | pbrook | data_addr = s->dispc.l[0].addr[0]; |
622 | 5c130f65 | pbrook | data = cpu_physical_memory_map(data_addr, &len, 0);
|
623 | 5c130f65 | pbrook | if (data && len != s->rfbi.pixels * 2) { |
624 | 5c130f65 | pbrook | cpu_physical_memory_unmap(data, len, 0, 0); |
625 | 5c130f65 | pbrook | data = NULL;
|
626 | 5c130f65 | pbrook | len = s->rfbi.pixels * 2;
|
627 | 5c130f65 | pbrook | } |
628 | 5c130f65 | pbrook | if (!data) {
|
629 | 5c130f65 | pbrook | if (len > bounce_len) {
|
630 | 5c130f65 | pbrook | bounce_buffer = qemu_realloc(bounce_buffer, len); |
631 | 5c130f65 | pbrook | } |
632 | 5c130f65 | pbrook | data = bounce_buffer; |
633 | 5c130f65 | pbrook | cpu_physical_memory_read(data_addr, data, len); |
634 | 5c130f65 | pbrook | } |
635 | 827df9f3 | balrog | |
636 | 827df9f3 | balrog | /* TODO bpp */
|
637 | 827df9f3 | balrog | s->rfbi.pixels = 0;
|
638 | 827df9f3 | balrog | |
639 | 827df9f3 | balrog | /* TODO: negative values */
|
640 | 827df9f3 | balrog | pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2; |
641 | 827df9f3 | balrog | |
642 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
643 | 827df9f3 | balrog | s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch); |
644 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
645 | 827df9f3 | balrog | s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); |
646 | 827df9f3 | balrog | |
647 | 5c130f65 | pbrook | if (data != bounce_buffer) {
|
648 | 5c130f65 | pbrook | cpu_physical_memory_unmap(data, len, 0, len);
|
649 | 5c130f65 | pbrook | } |
650 | 5c130f65 | pbrook | |
651 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
652 | 827df9f3 | balrog | |
653 | 827df9f3 | balrog | /* TODO */
|
654 | 827df9f3 | balrog | s->dispc.irqst |= 1; /* FRAMEDONE */ |
655 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
656 | 827df9f3 | balrog | } |
657 | 827df9f3 | balrog | |
658 | 827df9f3 | balrog | static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) |
659 | 827df9f3 | balrog | { |
660 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
661 | 827df9f3 | balrog | |
662 | 8da3ff18 | pbrook | switch (addr) {
|
663 | 827df9f3 | balrog | case 0x00: /* RFBI_REVISION */ |
664 | 827df9f3 | balrog | return 0x10; |
665 | 827df9f3 | balrog | |
666 | 827df9f3 | balrog | case 0x10: /* RFBI_SYSCONFIG */ |
667 | 827df9f3 | balrog | return s->rfbi.idlemode;
|
668 | 827df9f3 | balrog | |
669 | 827df9f3 | balrog | case 0x14: /* RFBI_SYSSTATUS */ |
670 | 827df9f3 | balrog | return 1 | (s->rfbi.busy << 8); /* RESETDONE */ |
671 | 827df9f3 | balrog | |
672 | 827df9f3 | balrog | case 0x40: /* RFBI_CONTROL */ |
673 | 827df9f3 | balrog | return s->rfbi.control;
|
674 | 827df9f3 | balrog | |
675 | 827df9f3 | balrog | case 0x44: /* RFBI_PIXELCNT */ |
676 | 827df9f3 | balrog | return s->rfbi.pixels;
|
677 | 827df9f3 | balrog | |
678 | 827df9f3 | balrog | case 0x48: /* RFBI_LINE_NUMBER */ |
679 | 827df9f3 | balrog | return s->rfbi.skiplines;
|
680 | 827df9f3 | balrog | |
681 | 827df9f3 | balrog | case 0x58: /* RFBI_READ */ |
682 | 827df9f3 | balrog | case 0x5c: /* RFBI_STATUS */ |
683 | 827df9f3 | balrog | return s->rfbi.rxbuf;
|
684 | 827df9f3 | balrog | |
685 | 827df9f3 | balrog | case 0x60: /* RFBI_CONFIG0 */ |
686 | 827df9f3 | balrog | return s->rfbi.config[0]; |
687 | 827df9f3 | balrog | case 0x64: /* RFBI_ONOFF_TIME0 */ |
688 | 827df9f3 | balrog | return s->rfbi.time[0]; |
689 | 827df9f3 | balrog | case 0x68: /* RFBI_CYCLE_TIME0 */ |
690 | 827df9f3 | balrog | return s->rfbi.time[1]; |
691 | 827df9f3 | balrog | case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
692 | 827df9f3 | balrog | return s->rfbi.data[0]; |
693 | 827df9f3 | balrog | case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
694 | 827df9f3 | balrog | return s->rfbi.data[1]; |
695 | 827df9f3 | balrog | case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
696 | 827df9f3 | balrog | return s->rfbi.data[2]; |
697 | 827df9f3 | balrog | |
698 | 827df9f3 | balrog | case 0x78: /* RFBI_CONFIG1 */ |
699 | 827df9f3 | balrog | return s->rfbi.config[1]; |
700 | 827df9f3 | balrog | case 0x7c: /* RFBI_ONOFF_TIME1 */ |
701 | 827df9f3 | balrog | return s->rfbi.time[2]; |
702 | 827df9f3 | balrog | case 0x80: /* RFBI_CYCLE_TIME1 */ |
703 | 827df9f3 | balrog | return s->rfbi.time[3]; |
704 | 827df9f3 | balrog | case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
705 | 827df9f3 | balrog | return s->rfbi.data[3]; |
706 | 827df9f3 | balrog | case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
707 | 827df9f3 | balrog | return s->rfbi.data[4]; |
708 | 827df9f3 | balrog | case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
709 | 827df9f3 | balrog | return s->rfbi.data[5]; |
710 | 827df9f3 | balrog | |
711 | 827df9f3 | balrog | case 0x90: /* RFBI_VSYNC_WIDTH */ |
712 | 827df9f3 | balrog | return s->rfbi.vsync;
|
713 | 827df9f3 | balrog | case 0x94: /* RFBI_HSYNC_WIDTH */ |
714 | 827df9f3 | balrog | return s->rfbi.hsync;
|
715 | 827df9f3 | balrog | } |
716 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
717 | 827df9f3 | balrog | return 0; |
718 | 827df9f3 | balrog | } |
719 | 827df9f3 | balrog | |
720 | 827df9f3 | balrog | static void omap_rfbi_write(void *opaque, target_phys_addr_t addr, |
721 | 827df9f3 | balrog | uint32_t value) |
722 | 827df9f3 | balrog | { |
723 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
724 | 827df9f3 | balrog | |
725 | 8da3ff18 | pbrook | switch (addr) {
|
726 | 827df9f3 | balrog | case 0x10: /* RFBI_SYSCONFIG */ |
727 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
728 | 827df9f3 | balrog | omap_rfbi_reset(s); |
729 | 827df9f3 | balrog | s->rfbi.idlemode = value & 0x19;
|
730 | 827df9f3 | balrog | break;
|
731 | 827df9f3 | balrog | |
732 | 827df9f3 | balrog | case 0x40: /* RFBI_CONTROL */ |
733 | 827df9f3 | balrog | s->rfbi.control = value & 0xf;
|
734 | 827df9f3 | balrog | s->rfbi.enable = value & 1;
|
735 | 827df9f3 | balrog | if (value & (1 << 4) && /* ITE */ |
736 | 827df9f3 | balrog | !(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) |
737 | 827df9f3 | balrog | omap_rfbi_transfer_start(s); |
738 | 827df9f3 | balrog | break;
|
739 | 827df9f3 | balrog | |
740 | 827df9f3 | balrog | case 0x44: /* RFBI_PIXELCNT */ |
741 | 827df9f3 | balrog | s->rfbi.pixels = value; |
742 | 827df9f3 | balrog | break;
|
743 | 827df9f3 | balrog | |
744 | 827df9f3 | balrog | case 0x48: /* RFBI_LINE_NUMBER */ |
745 | 827df9f3 | balrog | s->rfbi.skiplines = value & 0x7ff;
|
746 | 827df9f3 | balrog | break;
|
747 | 827df9f3 | balrog | |
748 | 827df9f3 | balrog | case 0x4c: /* RFBI_CMD */ |
749 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
750 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff); |
751 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
752 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff); |
753 | 827df9f3 | balrog | break;
|
754 | 827df9f3 | balrog | case 0x50: /* RFBI_PARAM */ |
755 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
756 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
757 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
758 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
759 | 827df9f3 | balrog | break;
|
760 | 827df9f3 | balrog | case 0x54: /* RFBI_DATA */ |
761 | 827df9f3 | balrog | /* TODO: take into account the format set up in s->rfbi.config[?] and
|
762 | 827df9f3 | balrog | * s->rfbi.data[?], but special-case the most usual scenario so that
|
763 | 827df9f3 | balrog | * speed doesn't suffer. */
|
764 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) { |
765 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
766 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16); |
767 | 827df9f3 | balrog | } |
768 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) { |
769 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
770 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16); |
771 | 827df9f3 | balrog | } |
772 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
773 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
774 | 827df9f3 | balrog | break;
|
775 | 827df9f3 | balrog | case 0x58: /* RFBI_READ */ |
776 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
777 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
778 | 827df9f3 | balrog | else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
779 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
780 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
781 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
782 | 827df9f3 | balrog | break;
|
783 | 827df9f3 | balrog | |
784 | 827df9f3 | balrog | case 0x5c: /* RFBI_STATUS */ |
785 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
786 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
787 | 827df9f3 | balrog | else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
788 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
789 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
790 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
791 | 827df9f3 | balrog | break;
|
792 | 827df9f3 | balrog | |
793 | 827df9f3 | balrog | case 0x60: /* RFBI_CONFIG0 */ |
794 | 827df9f3 | balrog | s->rfbi.config[0] = value & 0x003f1fff; |
795 | 827df9f3 | balrog | break;
|
796 | 827df9f3 | balrog | |
797 | 827df9f3 | balrog | case 0x64: /* RFBI_ONOFF_TIME0 */ |
798 | 827df9f3 | balrog | s->rfbi.time[0] = value & 0x3fffffff; |
799 | 827df9f3 | balrog | break;
|
800 | 827df9f3 | balrog | case 0x68: /* RFBI_CYCLE_TIME0 */ |
801 | 827df9f3 | balrog | s->rfbi.time[1] = value & 0x0fffffff; |
802 | 827df9f3 | balrog | break;
|
803 | 827df9f3 | balrog | case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
804 | 827df9f3 | balrog | s->rfbi.data[0] = value & 0x0f1f0f1f; |
805 | 827df9f3 | balrog | break;
|
806 | 827df9f3 | balrog | case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
807 | 827df9f3 | balrog | s->rfbi.data[1] = value & 0x0f1f0f1f; |
808 | 827df9f3 | balrog | break;
|
809 | 827df9f3 | balrog | case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
810 | 827df9f3 | balrog | s->rfbi.data[2] = value & 0x0f1f0f1f; |
811 | 827df9f3 | balrog | break;
|
812 | 827df9f3 | balrog | case 0x78: /* RFBI_CONFIG1 */ |
813 | 827df9f3 | balrog | s->rfbi.config[1] = value & 0x003f1fff; |
814 | 827df9f3 | balrog | break;
|
815 | 827df9f3 | balrog | |
816 | 827df9f3 | balrog | case 0x7c: /* RFBI_ONOFF_TIME1 */ |
817 | 827df9f3 | balrog | s->rfbi.time[2] = value & 0x3fffffff; |
818 | 827df9f3 | balrog | break;
|
819 | 827df9f3 | balrog | case 0x80: /* RFBI_CYCLE_TIME1 */ |
820 | 827df9f3 | balrog | s->rfbi.time[3] = value & 0x0fffffff; |
821 | 827df9f3 | balrog | break;
|
822 | 827df9f3 | balrog | case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
823 | 827df9f3 | balrog | s->rfbi.data[3] = value & 0x0f1f0f1f; |
824 | 827df9f3 | balrog | break;
|
825 | 827df9f3 | balrog | case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
826 | 827df9f3 | balrog | s->rfbi.data[4] = value & 0x0f1f0f1f; |
827 | 827df9f3 | balrog | break;
|
828 | 827df9f3 | balrog | case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
829 | 827df9f3 | balrog | s->rfbi.data[5] = value & 0x0f1f0f1f; |
830 | 827df9f3 | balrog | break;
|
831 | 827df9f3 | balrog | |
832 | 827df9f3 | balrog | case 0x90: /* RFBI_VSYNC_WIDTH */ |
833 | 827df9f3 | balrog | s->rfbi.vsync = value & 0xffff;
|
834 | 827df9f3 | balrog | break;
|
835 | 827df9f3 | balrog | case 0x94: /* RFBI_HSYNC_WIDTH */ |
836 | 827df9f3 | balrog | s->rfbi.hsync = value & 0xffff;
|
837 | 827df9f3 | balrog | break;
|
838 | 827df9f3 | balrog | |
839 | 827df9f3 | balrog | default:
|
840 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
841 | 827df9f3 | balrog | } |
842 | 827df9f3 | balrog | } |
843 | 827df9f3 | balrog | |
844 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_rfbi1_readfn[] = { |
845 | 827df9f3 | balrog | omap_badwidth_read32, |
846 | 827df9f3 | balrog | omap_badwidth_read32, |
847 | 827df9f3 | balrog | omap_rfbi_read, |
848 | 827df9f3 | balrog | }; |
849 | 827df9f3 | balrog | |
850 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = { |
851 | 827df9f3 | balrog | omap_badwidth_write32, |
852 | 827df9f3 | balrog | omap_badwidth_write32, |
853 | 827df9f3 | balrog | omap_rfbi_write, |
854 | 827df9f3 | balrog | }; |
855 | 827df9f3 | balrog | |
856 | 827df9f3 | balrog | static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) |
857 | 827df9f3 | balrog | { |
858 | 8da3ff18 | pbrook | switch (addr) {
|
859 | 827df9f3 | balrog | case 0x00: /* REV_ID */ |
860 | 827df9f3 | balrog | case 0x04: /* STATUS */ |
861 | 827df9f3 | balrog | case 0x08: /* F_CONTROL */ |
862 | 827df9f3 | balrog | case 0x10: /* VIDOUT_CTRL */ |
863 | 827df9f3 | balrog | case 0x14: /* SYNC_CTRL */ |
864 | 827df9f3 | balrog | case 0x1c: /* LLEN */ |
865 | 827df9f3 | balrog | case 0x20: /* FLENS */ |
866 | 827df9f3 | balrog | case 0x24: /* HFLTR_CTRL */ |
867 | 827df9f3 | balrog | case 0x28: /* CC_CARR_WSS_CARR */ |
868 | 827df9f3 | balrog | case 0x2c: /* C_PHASE */ |
869 | 827df9f3 | balrog | case 0x30: /* GAIN_U */ |
870 | 827df9f3 | balrog | case 0x34: /* GAIN_V */ |
871 | 827df9f3 | balrog | case 0x38: /* GAIN_Y */ |
872 | 827df9f3 | balrog | case 0x3c: /* BLACK_LEVEL */ |
873 | 827df9f3 | balrog | case 0x40: /* BLANK_LEVEL */ |
874 | 827df9f3 | balrog | case 0x44: /* X_COLOR */ |
875 | 827df9f3 | balrog | case 0x48: /* M_CONTROL */ |
876 | 827df9f3 | balrog | case 0x4c: /* BSTAMP_WSS_DATA */ |
877 | 827df9f3 | balrog | case 0x50: /* S_CARR */ |
878 | 827df9f3 | balrog | case 0x54: /* LINE21 */ |
879 | 827df9f3 | balrog | case 0x58: /* LN_SEL */ |
880 | 827df9f3 | balrog | case 0x5c: /* L21__WC_CTL */ |
881 | 827df9f3 | balrog | case 0x60: /* HTRIGGER_VTRIGGER */ |
882 | 827df9f3 | balrog | case 0x64: /* SAVID__EAVID */ |
883 | 827df9f3 | balrog | case 0x68: /* FLEN__FAL */ |
884 | 827df9f3 | balrog | case 0x6c: /* LAL__PHASE_RESET */ |
885 | 827df9f3 | balrog | case 0x70: /* HS_INT_START_STOP_X */ |
886 | 827df9f3 | balrog | case 0x74: /* HS_EXT_START_STOP_X */ |
887 | 827df9f3 | balrog | case 0x78: /* VS_INT_START_X */ |
888 | 827df9f3 | balrog | case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
889 | 827df9f3 | balrog | case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
890 | 827df9f3 | balrog | case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
891 | 827df9f3 | balrog | case 0x88: /* VS_EXT_STOP_Y */ |
892 | 827df9f3 | balrog | case 0x90: /* AVID_START_STOP_X */ |
893 | 827df9f3 | balrog | case 0x94: /* AVID_START_STOP_Y */ |
894 | 827df9f3 | balrog | case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
895 | 827df9f3 | balrog | case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
896 | 827df9f3 | balrog | case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
897 | 827df9f3 | balrog | case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
898 | 827df9f3 | balrog | case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
899 | 827df9f3 | balrog | case 0xb8: /* GEN_CTRL */ |
900 | 827df9f3 | balrog | case 0xc4: /* DAC_TST__DAC_A */ |
901 | 827df9f3 | balrog | case 0xc8: /* DAC_B__DAC_C */ |
902 | 827df9f3 | balrog | return 0; |
903 | 827df9f3 | balrog | |
904 | 827df9f3 | balrog | default:
|
905 | 827df9f3 | balrog | break;
|
906 | 827df9f3 | balrog | } |
907 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
908 | 827df9f3 | balrog | return 0; |
909 | 827df9f3 | balrog | } |
910 | 827df9f3 | balrog | |
911 | 827df9f3 | balrog | static void omap_venc_write(void *opaque, target_phys_addr_t addr, |
912 | 827df9f3 | balrog | uint32_t value) |
913 | 827df9f3 | balrog | { |
914 | 8da3ff18 | pbrook | switch (addr) {
|
915 | 827df9f3 | balrog | case 0x08: /* F_CONTROL */ |
916 | 827df9f3 | balrog | case 0x10: /* VIDOUT_CTRL */ |
917 | 827df9f3 | balrog | case 0x14: /* SYNC_CTRL */ |
918 | 827df9f3 | balrog | case 0x1c: /* LLEN */ |
919 | 827df9f3 | balrog | case 0x20: /* FLENS */ |
920 | 827df9f3 | balrog | case 0x24: /* HFLTR_CTRL */ |
921 | 827df9f3 | balrog | case 0x28: /* CC_CARR_WSS_CARR */ |
922 | 827df9f3 | balrog | case 0x2c: /* C_PHASE */ |
923 | 827df9f3 | balrog | case 0x30: /* GAIN_U */ |
924 | 827df9f3 | balrog | case 0x34: /* GAIN_V */ |
925 | 827df9f3 | balrog | case 0x38: /* GAIN_Y */ |
926 | 827df9f3 | balrog | case 0x3c: /* BLACK_LEVEL */ |
927 | 827df9f3 | balrog | case 0x40: /* BLANK_LEVEL */ |
928 | 827df9f3 | balrog | case 0x44: /* X_COLOR */ |
929 | 827df9f3 | balrog | case 0x48: /* M_CONTROL */ |
930 | 827df9f3 | balrog | case 0x4c: /* BSTAMP_WSS_DATA */ |
931 | 827df9f3 | balrog | case 0x50: /* S_CARR */ |
932 | 827df9f3 | balrog | case 0x54: /* LINE21 */ |
933 | 827df9f3 | balrog | case 0x58: /* LN_SEL */ |
934 | 827df9f3 | balrog | case 0x5c: /* L21__WC_CTL */ |
935 | 827df9f3 | balrog | case 0x60: /* HTRIGGER_VTRIGGER */ |
936 | 827df9f3 | balrog | case 0x64: /* SAVID__EAVID */ |
937 | 827df9f3 | balrog | case 0x68: /* FLEN__FAL */ |
938 | 827df9f3 | balrog | case 0x6c: /* LAL__PHASE_RESET */ |
939 | 827df9f3 | balrog | case 0x70: /* HS_INT_START_STOP_X */ |
940 | 827df9f3 | balrog | case 0x74: /* HS_EXT_START_STOP_X */ |
941 | 827df9f3 | balrog | case 0x78: /* VS_INT_START_X */ |
942 | 827df9f3 | balrog | case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
943 | 827df9f3 | balrog | case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
944 | 827df9f3 | balrog | case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
945 | 827df9f3 | balrog | case 0x88: /* VS_EXT_STOP_Y */ |
946 | 827df9f3 | balrog | case 0x90: /* AVID_START_STOP_X */ |
947 | 827df9f3 | balrog | case 0x94: /* AVID_START_STOP_Y */ |
948 | 827df9f3 | balrog | case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
949 | 827df9f3 | balrog | case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
950 | 827df9f3 | balrog | case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
951 | 827df9f3 | balrog | case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
952 | 827df9f3 | balrog | case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
953 | 827df9f3 | balrog | case 0xb8: /* GEN_CTRL */ |
954 | 827df9f3 | balrog | case 0xc4: /* DAC_TST__DAC_A */ |
955 | 827df9f3 | balrog | case 0xc8: /* DAC_B__DAC_C */ |
956 | 827df9f3 | balrog | break;
|
957 | 827df9f3 | balrog | |
958 | 827df9f3 | balrog | default:
|
959 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
960 | 827df9f3 | balrog | } |
961 | 827df9f3 | balrog | } |
962 | 827df9f3 | balrog | |
963 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_venc1_readfn[] = { |
964 | 827df9f3 | balrog | omap_badwidth_read32, |
965 | 827df9f3 | balrog | omap_badwidth_read32, |
966 | 827df9f3 | balrog | omap_venc_read, |
967 | 827df9f3 | balrog | }; |
968 | 827df9f3 | balrog | |
969 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_venc1_writefn[] = { |
970 | 827df9f3 | balrog | omap_badwidth_write32, |
971 | 827df9f3 | balrog | omap_badwidth_write32, |
972 | 827df9f3 | balrog | omap_venc_write, |
973 | 827df9f3 | balrog | }; |
974 | 827df9f3 | balrog | |
975 | 827df9f3 | balrog | static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) |
976 | 827df9f3 | balrog | { |
977 | 8da3ff18 | pbrook | switch (addr) {
|
978 | 827df9f3 | balrog | case 0x0a8: /* SBIMERRLOGA */ |
979 | 827df9f3 | balrog | case 0x0b0: /* SBIMERRLOG */ |
980 | 827df9f3 | balrog | case 0x190: /* SBIMSTATE */ |
981 | 827df9f3 | balrog | case 0x198: /* SBTMSTATE_L */ |
982 | 827df9f3 | balrog | case 0x19c: /* SBTMSTATE_H */ |
983 | 827df9f3 | balrog | case 0x1a8: /* SBIMCONFIG_L */ |
984 | 827df9f3 | balrog | case 0x1ac: /* SBIMCONFIG_H */ |
985 | 827df9f3 | balrog | case 0x1f8: /* SBID_L */ |
986 | 827df9f3 | balrog | case 0x1fc: /* SBID_H */ |
987 | 827df9f3 | balrog | return 0; |
988 | 827df9f3 | balrog | |
989 | 827df9f3 | balrog | default:
|
990 | 827df9f3 | balrog | break;
|
991 | 827df9f3 | balrog | } |
992 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
993 | 827df9f3 | balrog | return 0; |
994 | 827df9f3 | balrog | } |
995 | 827df9f3 | balrog | |
996 | 827df9f3 | balrog | static void omap_im3_write(void *opaque, target_phys_addr_t addr, |
997 | 827df9f3 | balrog | uint32_t value) |
998 | 827df9f3 | balrog | { |
999 | 8da3ff18 | pbrook | switch (addr) {
|
1000 | 827df9f3 | balrog | case 0x0b0: /* SBIMERRLOG */ |
1001 | 827df9f3 | balrog | case 0x190: /* SBIMSTATE */ |
1002 | 827df9f3 | balrog | case 0x198: /* SBTMSTATE_L */ |
1003 | 827df9f3 | balrog | case 0x19c: /* SBTMSTATE_H */ |
1004 | 827df9f3 | balrog | case 0x1a8: /* SBIMCONFIG_L */ |
1005 | 827df9f3 | balrog | case 0x1ac: /* SBIMCONFIG_H */ |
1006 | 827df9f3 | balrog | break;
|
1007 | 827df9f3 | balrog | |
1008 | 827df9f3 | balrog | default:
|
1009 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1010 | 827df9f3 | balrog | } |
1011 | 827df9f3 | balrog | } |
1012 | 827df9f3 | balrog | |
1013 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_im3_readfn[] = { |
1014 | 827df9f3 | balrog | omap_badwidth_read32, |
1015 | 827df9f3 | balrog | omap_badwidth_read32, |
1016 | 827df9f3 | balrog | omap_im3_read, |
1017 | 827df9f3 | balrog | }; |
1018 | 827df9f3 | balrog | |
1019 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_im3_writefn[] = { |
1020 | 827df9f3 | balrog | omap_badwidth_write32, |
1021 | 827df9f3 | balrog | omap_badwidth_write32, |
1022 | 827df9f3 | balrog | omap_im3_write, |
1023 | 827df9f3 | balrog | }; |
1024 | 827df9f3 | balrog | |
1025 | 827df9f3 | balrog | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
1026 | 3023f332 | aliguori | target_phys_addr_t l3_base, |
1027 | 827df9f3 | balrog | qemu_irq irq, qemu_irq drq, |
1028 | 827df9f3 | balrog | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
1029 | 827df9f3 | balrog | omap_clk ick1, omap_clk ick2) |
1030 | 827df9f3 | balrog | { |
1031 | 827df9f3 | balrog | int iomemtype[5]; |
1032 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) |
1033 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_dss_s)); |
1034 | 827df9f3 | balrog | |
1035 | 827df9f3 | balrog | s->irq = irq; |
1036 | 827df9f3 | balrog | s->drq = drq; |
1037 | 827df9f3 | balrog | omap_dss_reset(s); |
1038 | 827df9f3 | balrog | |
1039 | 1eed09cb | Avi Kivity | iomemtype[0] = l4_register_io_memory(omap_diss1_readfn,
|
1040 | 827df9f3 | balrog | omap_diss1_writefn, s); |
1041 | 1eed09cb | Avi Kivity | iomemtype[1] = l4_register_io_memory(omap_disc1_readfn,
|
1042 | 827df9f3 | balrog | omap_disc1_writefn, s); |
1043 | 1eed09cb | Avi Kivity | iomemtype[2] = l4_register_io_memory(omap_rfbi1_readfn,
|
1044 | 827df9f3 | balrog | omap_rfbi1_writefn, s); |
1045 | 1eed09cb | Avi Kivity | iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
|
1046 | 827df9f3 | balrog | omap_venc1_writefn, s); |
1047 | 1eed09cb | Avi Kivity | iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
|
1048 | 827df9f3 | balrog | omap_im3_writefn, s); |
1049 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype[0]); |
1050 | 8da3ff18 | pbrook | omap_l4_attach(ta, 1, iomemtype[1]); |
1051 | 9e7d11ff | balrog | omap_l4_attach(ta, 2, iomemtype[2]); |
1052 | 8da3ff18 | pbrook | omap_l4_attach(ta, 3, iomemtype[3]); |
1053 | 8da3ff18 | pbrook | cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]); |
1054 | 827df9f3 | balrog | |
1055 | 827df9f3 | balrog | #if 0
|
1056 | 3023f332 | aliguori | s->state = graphic_console_init(omap_update_display,
|
1057 | 3023f332 | aliguori | omap_invalidate_display, omap_screen_dump, s);
|
1058 | 827df9f3 | balrog | #endif
|
1059 | 827df9f3 | balrog | |
1060 | 827df9f3 | balrog | return s;
|
1061 | 827df9f3 | balrog | } |
1062 | 827df9f3 | balrog | |
1063 | 827df9f3 | balrog | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip) |
1064 | 827df9f3 | balrog | { |
1065 | 827df9f3 | balrog | if (cs < 0 || cs > 1) |
1066 | 2ac71179 | Paul Brook | hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
|
1067 | 827df9f3 | balrog | s->rfbi.chip[cs] = chip; |
1068 | 827df9f3 | balrog | } |