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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | #include <stdarg.h> |
23 | 7a3f1944 | bellard | #include <stdlib.h> |
24 | 7a3f1944 | bellard | #include <stdio.h> |
25 | 7a3f1944 | bellard | #include <string.h> |
26 | 7a3f1944 | bellard | #include <inttypes.h> |
27 | 7a3f1944 | bellard | |
28 | 7a3f1944 | bellard | #include "cpu.h" |
29 | 7a3f1944 | bellard | #include "exec-all.h" |
30 | 7a3f1944 | bellard | #include "disas.h" |
31 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | 7a3f1944 | bellard | |
34 | 7a3f1944 | bellard | #define DEBUG_DISAS
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35 | 7a3f1944 | bellard | |
36 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
37 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
38 | 72cbca10 | bellard | according to jump_pc[T2] */
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39 | 72cbca10 | bellard | |
40 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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41 | d987963a | blueswir1 | static TCGv cpu_env, cpu_regwptr;
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42 | 77f193da | blueswir1 | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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43 | 48d5c82b | blueswir1 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
44 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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45 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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46 | dc99a3f2 | blueswir1 | static TCGv cpu_xcc;
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47 | dc99a3f2 | blueswir1 | #endif
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48 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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49 | 8911f501 | blueswir1 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
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50 | 1a2fb1c0 | blueswir1 | |
51 | 2e70f6ef | pbrook | #include "gen-icount.h" |
52 | 2e70f6ef | pbrook | |
53 | 7a3f1944 | bellard | typedef struct DisasContext { |
54 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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55 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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56 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
57 | cf495bcf | bellard | int is_br;
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58 | e8af50a3 | bellard | int mem_idx;
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59 | a80dde08 | bellard | int fpu_enabled;
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60 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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61 | cf495bcf | bellard | struct TranslationBlock *tb;
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62 | 64a88d5d | blueswir1 | uint32_t features; |
63 | 7a3f1944 | bellard | } DisasContext; |
64 | 7a3f1944 | bellard | |
65 | 3475187d | bellard | // This function uses non-native bit order
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66 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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67 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
68 | 7a3f1944 | bellard | |
69 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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70 | 3475187d | bellard | #define GET_FIELD_SP(X, FROM, TO) \
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71 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
72 | 3475187d | bellard | |
73 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
74 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
75 | 3475187d | bellard | |
76 | 3475187d | bellard | #ifdef TARGET_SPARC64
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77 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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78 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
79 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
80 | 3475187d | bellard | #else
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81 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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82 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
83 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
84 | 3475187d | bellard | #endif
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85 | 3475187d | bellard | |
86 | 3475187d | bellard | static int sign_extend(int x, int len) |
87 | 3475187d | bellard | { |
88 | 3475187d | bellard | len = 32 - len;
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89 | 3475187d | bellard | return (x << len) >> len;
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90 | 3475187d | bellard | } |
91 | 3475187d | bellard | |
92 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
93 | 7a3f1944 | bellard | |
94 | ff07ec83 | blueswir1 | /* floating point registers moves */
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95 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT0(unsigned int src) |
96 | ff07ec83 | blueswir1 | { |
97 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
98 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
99 | 3475187d | bellard | } |
100 | ff07ec83 | blueswir1 | |
101 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT1(unsigned int src) |
102 | ff07ec83 | blueswir1 | { |
103 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
104 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1)); |
105 | e8af50a3 | bellard | } |
106 | e8af50a3 | bellard | |
107 | ff07ec83 | blueswir1 | static void gen_op_store_FT0_fpr(unsigned int dst) |
108 | ff07ec83 | blueswir1 | { |
109 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
110 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
111 | ff07ec83 | blueswir1 | } |
112 | ff07ec83 | blueswir1 | |
113 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
114 | ff07ec83 | blueswir1 | { |
115 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
116 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
117 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
118 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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119 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
120 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
121 | ff07ec83 | blueswir1 | } |
122 | ff07ec83 | blueswir1 | |
123 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
124 | ff07ec83 | blueswir1 | { |
125 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
126 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
127 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
128 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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129 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
130 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
131 | ff07ec83 | blueswir1 | } |
132 | ff07ec83 | blueswir1 | |
133 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
134 | ff07ec83 | blueswir1 | { |
135 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
136 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
137 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
138 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
139 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
140 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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141 | ff07ec83 | blueswir1 | } |
142 | ff07ec83 | blueswir1 | |
143 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
144 | ff07ec83 | blueswir1 | { |
145 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
146 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
147 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
148 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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149 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
150 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
151 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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152 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
153 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
154 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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155 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
156 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
157 | ff07ec83 | blueswir1 | } |
158 | ff07ec83 | blueswir1 | |
159 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
160 | ff07ec83 | blueswir1 | { |
161 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
162 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
163 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
164 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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165 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
166 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
167 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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168 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
169 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
170 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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171 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
172 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
173 | ff07ec83 | blueswir1 | } |
174 | ff07ec83 | blueswir1 | |
175 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
176 | ff07ec83 | blueswir1 | { |
177 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
178 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
179 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
180 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
181 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
182 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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183 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
184 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
185 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
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186 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
187 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
188 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
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189 | ff07ec83 | blueswir1 | } |
190 | 1f587329 | blueswir1 | |
191 | 81ad8ba2 | blueswir1 | /* moves */
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192 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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193 | 3475187d | bellard | #define supervisor(dc) 0 |
194 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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195 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
196 | 81ad8ba2 | blueswir1 | #endif
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197 | 3475187d | bellard | #else
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198 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
199 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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200 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
201 | 6f27aba6 | blueswir1 | #else
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202 | 3475187d | bellard | #endif
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203 | 81ad8ba2 | blueswir1 | #endif
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204 | 81ad8ba2 | blueswir1 | |
205 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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206 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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207 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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208 | 1a2fb1c0 | blueswir1 | #else
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209 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
210 | 2cade6a3 | blueswir1 | #endif
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211 | 1a2fb1c0 | blueswir1 | #endif
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212 | 3391c818 | blueswir1 | |
213 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
214 | 2cade6a3 | blueswir1 | { |
215 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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216 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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217 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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218 | 2cade6a3 | blueswir1 | #endif
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219 | 2cade6a3 | blueswir1 | } |
220 | 2cade6a3 | blueswir1 | |
221 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
222 | 81ad8ba2 | blueswir1 | { |
223 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
224 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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225 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
226 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
227 | 1a2fb1c0 | blueswir1 | else {
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228 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
229 | 81ad8ba2 | blueswir1 | } |
230 | 81ad8ba2 | blueswir1 | } |
231 | 81ad8ba2 | blueswir1 | |
232 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
233 | 81ad8ba2 | blueswir1 | { |
234 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
235 | 1a2fb1c0 | blueswir1 | return;
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236 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
237 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
238 | 1a2fb1c0 | blueswir1 | else {
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239 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
240 | 81ad8ba2 | blueswir1 | } |
241 | 81ad8ba2 | blueswir1 | } |
242 | 81ad8ba2 | blueswir1 | |
243 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
244 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
245 | 6e256c93 | bellard | { |
246 | 6e256c93 | bellard | TranslationBlock *tb; |
247 | 6e256c93 | bellard | |
248 | 6e256c93 | bellard | tb = s->tb; |
249 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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250 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
251 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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252 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
253 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
254 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
255 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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256 | 6e256c93 | bellard | } else {
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257 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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258 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
259 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
260 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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261 | 6e256c93 | bellard | } |
262 | 6e256c93 | bellard | } |
263 | 6e256c93 | bellard | |
264 | 19f329ad | blueswir1 | // XXX suboptimal
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265 | 19f329ad | blueswir1 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
266 | 19f329ad | blueswir1 | { |
267 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
268 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
269 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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270 | 19f329ad | blueswir1 | } |
271 | 19f329ad | blueswir1 | |
272 | 19f329ad | blueswir1 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
273 | 19f329ad | blueswir1 | { |
274 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
275 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
276 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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277 | 19f329ad | blueswir1 | } |
278 | 19f329ad | blueswir1 | |
279 | 19f329ad | blueswir1 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
280 | 19f329ad | blueswir1 | { |
281 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
282 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
283 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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284 | 19f329ad | blueswir1 | } |
285 | 19f329ad | blueswir1 | |
286 | 19f329ad | blueswir1 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
287 | 19f329ad | blueswir1 | { |
288 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
289 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
290 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
291 | 19f329ad | blueswir1 | } |
292 | 19f329ad | blueswir1 | |
293 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_icc(void) |
294 | dc99a3f2 | blueswir1 | { |
295 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_psr, 0);
|
296 | ce5b3c3d | blueswir1 | } |
297 | ce5b3c3d | blueswir1 | |
298 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
299 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_xcc(void) |
300 | ce5b3c3d | blueswir1 | { |
301 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_xcc, 0);
|
302 | dc99a3f2 | blueswir1 | } |
303 | ce5b3c3d | blueswir1 | #endif
|
304 | dc99a3f2 | blueswir1 | |
305 | dc99a3f2 | blueswir1 | /* old op:
|
306 | dc99a3f2 | blueswir1 | if (!T0)
|
307 | dc99a3f2 | blueswir1 | env->psr |= PSR_ZERO;
|
308 | dc99a3f2 | blueswir1 | if ((int32_t) T0 < 0)
|
309 | dc99a3f2 | blueswir1 | env->psr |= PSR_NEG;
|
310 | dc99a3f2 | blueswir1 | */
|
311 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_icc(TCGv dst) |
312 | dc99a3f2 | blueswir1 | { |
313 | 8911f501 | blueswir1 | TCGv r_temp; |
314 | dc99a3f2 | blueswir1 | int l1, l2;
|
315 | dc99a3f2 | blueswir1 | |
316 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
317 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
318 | 8911f501 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
319 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
|
320 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
321 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
322 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
323 | bdf46ea2 | blueswir1 | tcg_gen_ext_i32_tl(r_temp, dst); |
324 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
|
325 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
326 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
327 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
328 | ce5b3c3d | blueswir1 | } |
329 | ce5b3c3d | blueswir1 | |
330 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
331 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_xcc(TCGv dst) |
332 | ce5b3c3d | blueswir1 | { |
333 | ce5b3c3d | blueswir1 | int l1, l2;
|
334 | ce5b3c3d | blueswir1 | |
335 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
336 | ce5b3c3d | blueswir1 | l2 = gen_new_label(); |
337 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
|
338 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
339 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
340 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
|
341 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
342 | ce5b3c3d | blueswir1 | gen_set_label(l2); |
343 | dc99a3f2 | blueswir1 | } |
344 | ce5b3c3d | blueswir1 | #endif
|
345 | dc99a3f2 | blueswir1 | |
346 | dc99a3f2 | blueswir1 | /* old op:
|
347 | dc99a3f2 | blueswir1 | if (T0 < src1)
|
348 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
349 | dc99a3f2 | blueswir1 | */
|
350 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
351 | dc99a3f2 | blueswir1 | { |
352 | 8911f501 | blueswir1 | TCGv r_temp; |
353 | dc99a3f2 | blueswir1 | int l1;
|
354 | dc99a3f2 | blueswir1 | |
355 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
356 | 8911f501 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
357 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
|
358 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
359 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
360 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
361 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
362 | ce5b3c3d | blueswir1 | } |
363 | ce5b3c3d | blueswir1 | |
364 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
365 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
366 | ce5b3c3d | blueswir1 | { |
367 | ce5b3c3d | blueswir1 | int l1;
|
368 | dc99a3f2 | blueswir1 | |
369 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
370 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
371 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
372 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
373 | dc99a3f2 | blueswir1 | } |
374 | ce5b3c3d | blueswir1 | #endif
|
375 | dc99a3f2 | blueswir1 | |
376 | dc99a3f2 | blueswir1 | /* old op:
|
377 | dc99a3f2 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
|
378 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
379 | dc99a3f2 | blueswir1 | */
|
380 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
381 | dc99a3f2 | blueswir1 | { |
382 | 0425bee5 | blueswir1 | TCGv r_temp; |
383 | dc99a3f2 | blueswir1 | |
384 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
385 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
386 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
387 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
388 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
389 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
390 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
391 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
392 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
393 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
394 | ce5b3c3d | blueswir1 | } |
395 | ce5b3c3d | blueswir1 | |
396 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
397 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
398 | ce5b3c3d | blueswir1 | { |
399 | ce5b3c3d | blueswir1 | TCGv r_temp; |
400 | ce5b3c3d | blueswir1 | |
401 | ce5b3c3d | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
402 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
403 | ce5b3c3d | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
404 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
405 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
406 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
407 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
408 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
409 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
410 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
411 | dc99a3f2 | blueswir1 | } |
412 | ce5b3c3d | blueswir1 | #endif
|
413 | dc99a3f2 | blueswir1 | |
414 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
415 | dc99a3f2 | blueswir1 | { |
416 | 2ea815ca | blueswir1 | TCGv r_temp, r_const; |
417 | dc99a3f2 | blueswir1 | int l1;
|
418 | dc99a3f2 | blueswir1 | |
419 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
420 | dc99a3f2 | blueswir1 | |
421 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
422 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
423 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
424 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
425 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
426 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
427 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
428 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
429 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
430 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
431 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
432 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
433 | dc99a3f2 | blueswir1 | } |
434 | dc99a3f2 | blueswir1 | |
435 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
436 | dc99a3f2 | blueswir1 | { |
437 | dc99a3f2 | blueswir1 | int l1;
|
438 | dc99a3f2 | blueswir1 | |
439 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
440 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
441 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
442 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
443 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
444 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
445 | dc99a3f2 | blueswir1 | } |
446 | dc99a3f2 | blueswir1 | |
447 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
448 | dc99a3f2 | blueswir1 | { |
449 | dc99a3f2 | blueswir1 | int l1;
|
450 | 2ea815ca | blueswir1 | TCGv r_const; |
451 | dc99a3f2 | blueswir1 | |
452 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
453 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
454 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
455 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
456 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
457 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
458 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
459 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
460 | dc99a3f2 | blueswir1 | } |
461 | dc99a3f2 | blueswir1 | |
462 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
463 | dc99a3f2 | blueswir1 | { |
464 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
465 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
466 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
467 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
468 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
469 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
470 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
471 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
472 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
473 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
474 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
475 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
476 | ce5b3c3d | blueswir1 | #endif
|
477 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
478 | dc99a3f2 | blueswir1 | } |
479 | dc99a3f2 | blueswir1 | |
480 | 4af984a7 | blueswir1 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
481 | dc99a3f2 | blueswir1 | { |
482 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
483 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
484 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
485 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
486 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
487 | 5c6a0628 | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
488 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
489 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
490 | 5c6a0628 | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
491 | ce5b3c3d | blueswir1 | #endif
|
492 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
493 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
494 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
495 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
496 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
497 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
498 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
499 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
500 | ce5b3c3d | blueswir1 | #endif
|
501 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
502 | dc99a3f2 | blueswir1 | } |
503 | dc99a3f2 | blueswir1 | |
504 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
505 | dc99a3f2 | blueswir1 | { |
506 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
507 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
508 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
509 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
510 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
511 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
512 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
513 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
514 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
515 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
516 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
517 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
518 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
519 | ce5b3c3d | blueswir1 | #endif
|
520 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
521 | dc99a3f2 | blueswir1 | } |
522 | dc99a3f2 | blueswir1 | |
523 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
524 | dc99a3f2 | blueswir1 | { |
525 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
526 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
527 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
528 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
529 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
530 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
531 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
532 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
533 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
534 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
535 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
536 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
537 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
538 | ce5b3c3d | blueswir1 | #endif
|
539 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
540 | dc99a3f2 | blueswir1 | } |
541 | dc99a3f2 | blueswir1 | |
542 | dc99a3f2 | blueswir1 | /* old op:
|
543 | dc99a3f2 | blueswir1 | if (src1 < T1)
|
544 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
545 | dc99a3f2 | blueswir1 | */
|
546 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
547 | dc99a3f2 | blueswir1 | { |
548 | 8911f501 | blueswir1 | TCGv r_temp1, r_temp2; |
549 | dc99a3f2 | blueswir1 | int l1;
|
550 | dc99a3f2 | blueswir1 | |
551 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
552 | 8911f501 | blueswir1 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
553 | 8911f501 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
554 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
|
555 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
|
556 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
557 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
558 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
559 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp1); |
560 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
561 | ce5b3c3d | blueswir1 | } |
562 | ce5b3c3d | blueswir1 | |
563 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
564 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
565 | ce5b3c3d | blueswir1 | { |
566 | ce5b3c3d | blueswir1 | int l1;
|
567 | dc99a3f2 | blueswir1 | |
568 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
569 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); |
570 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
571 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
572 | dc99a3f2 | blueswir1 | } |
573 | ce5b3c3d | blueswir1 | #endif
|
574 | dc99a3f2 | blueswir1 | |
575 | dc99a3f2 | blueswir1 | /* old op:
|
576 | dc99a3f2 | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
|
577 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
578 | dc99a3f2 | blueswir1 | */
|
579 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
580 | dc99a3f2 | blueswir1 | { |
581 | 0425bee5 | blueswir1 | TCGv r_temp; |
582 | dc99a3f2 | blueswir1 | |
583 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
584 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
585 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
586 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
587 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
588 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
589 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
590 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
591 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
592 | ce5b3c3d | blueswir1 | } |
593 | ce5b3c3d | blueswir1 | |
594 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
595 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
596 | ce5b3c3d | blueswir1 | { |
597 | ce5b3c3d | blueswir1 | TCGv r_temp; |
598 | ce5b3c3d | blueswir1 | |
599 | ce5b3c3d | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
600 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
601 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
602 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
603 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
604 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
605 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
606 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
607 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
608 | dc99a3f2 | blueswir1 | } |
609 | ce5b3c3d | blueswir1 | #endif
|
610 | dc99a3f2 | blueswir1 | |
611 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
612 | dc99a3f2 | blueswir1 | { |
613 | 2ea815ca | blueswir1 | TCGv r_temp, r_const; |
614 | dc99a3f2 | blueswir1 | int l1;
|
615 | dc99a3f2 | blueswir1 | |
616 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
617 | dc99a3f2 | blueswir1 | |
618 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
619 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
620 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
621 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
622 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
623 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
624 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
625 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
626 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
627 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
628 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
629 | dc99a3f2 | blueswir1 | } |
630 | dc99a3f2 | blueswir1 | |
631 | 4af984a7 | blueswir1 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
632 | dc99a3f2 | blueswir1 | { |
633 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
634 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
635 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
636 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
637 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
638 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
639 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
640 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
641 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
642 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
643 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
644 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
645 | ce5b3c3d | blueswir1 | #endif
|
646 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
647 | dc99a3f2 | blueswir1 | } |
648 | dc99a3f2 | blueswir1 | |
649 | 4af984a7 | blueswir1 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
650 | dc99a3f2 | blueswir1 | { |
651 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
652 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
653 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
654 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
655 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
656 | 5c6a0628 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
657 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
658 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
659 | 5c6a0628 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
660 | ce5b3c3d | blueswir1 | #endif
|
661 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
662 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
663 | ba28189b | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
664 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
665 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
666 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
667 | ba28189b | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
668 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
669 | ce5b3c3d | blueswir1 | #endif
|
670 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
671 | dc99a3f2 | blueswir1 | } |
672 | dc99a3f2 | blueswir1 | |
673 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
674 | dc99a3f2 | blueswir1 | { |
675 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
676 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
677 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
678 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
679 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
680 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
681 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
682 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
683 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
684 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
685 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
686 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
687 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
688 | ce5b3c3d | blueswir1 | #endif
|
689 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
690 | dc99a3f2 | blueswir1 | } |
691 | dc99a3f2 | blueswir1 | |
692 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
693 | dc99a3f2 | blueswir1 | { |
694 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
695 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
696 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
697 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
698 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
699 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
700 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
701 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
702 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
703 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
704 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
705 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
706 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
707 | ce5b3c3d | blueswir1 | #endif
|
708 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
709 | dc99a3f2 | blueswir1 | } |
710 | dc99a3f2 | blueswir1 | |
711 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
712 | d9bdab86 | blueswir1 | { |
713 | 7127fe84 | blueswir1 | TCGv r_temp, r_temp2; |
714 | 6f551262 | blueswir1 | int l1;
|
715 | d9bdab86 | blueswir1 | |
716 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
717 | d9bdab86 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
718 | 7127fe84 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I32); |
719 | d9bdab86 | blueswir1 | |
720 | d9bdab86 | blueswir1 | /* old op:
|
721 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
722 | d9bdab86 | blueswir1 | T1 = 0;
|
723 | d9bdab86 | blueswir1 | */
|
724 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
725 | 7127fe84 | blueswir1 | tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
726 | 7127fe84 | blueswir1 | tcg_gen_trunc_tl_i32(r_temp2, r_temp); |
727 | 7127fe84 | blueswir1 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
|
728 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
729 | cb63669a | pbrook | tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
|
730 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
731 | 6f551262 | blueswir1 | gen_set_label(l1); |
732 | d9bdab86 | blueswir1 | |
733 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
734 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
735 | 6f551262 | blueswir1 | tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); |
736 | 7127fe84 | blueswir1 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
|
737 | 7127fe84 | blueswir1 | tcg_gen_shli_i32(r_temp2, r_temp2, 31);
|
738 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
739 | 8911f501 | blueswir1 | tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
|
740 | 7127fe84 | blueswir1 | tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); |
741 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
742 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
743 | d9bdab86 | blueswir1 | |
744 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
745 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
746 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
747 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
748 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
749 | d9bdab86 | blueswir1 | |
750 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
751 | d9bdab86 | blueswir1 | // src1 = T0;
|
752 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
753 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
754 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
755 | d9bdab86 | blueswir1 | |
756 | d9bdab86 | blueswir1 | /* do addition and update flags */
|
757 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
758 | d9bdab86 | blueswir1 | |
759 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
760 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
761 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
762 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
763 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
764 | d9bdab86 | blueswir1 | } |
765 | d9bdab86 | blueswir1 | |
766 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
767 | 8879d139 | blueswir1 | { |
768 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
769 | 8879d139 | blueswir1 | |
770 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
771 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
772 | 8879d139 | blueswir1 | |
773 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
774 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
775 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
776 | 8879d139 | blueswir1 | |
777 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
778 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
779 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
780 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
781 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
782 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
783 | 8879d139 | blueswir1 | #else
|
784 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
785 | 8879d139 | blueswir1 | #endif
|
786 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
787 | 8879d139 | blueswir1 | } |
788 | 8879d139 | blueswir1 | |
789 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
790 | 8879d139 | blueswir1 | { |
791 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
792 | 8879d139 | blueswir1 | |
793 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
794 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
795 | 8879d139 | blueswir1 | |
796 | 4af984a7 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
797 | 4af984a7 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
798 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
799 | 8879d139 | blueswir1 | |
800 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
801 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
802 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
803 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
804 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
805 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
806 | 8879d139 | blueswir1 | #else
|
807 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
808 | 8879d139 | blueswir1 | #endif
|
809 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
810 | 8879d139 | blueswir1 | } |
811 | 8879d139 | blueswir1 | |
812 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
813 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
814 | 1a7b60e7 | blueswir1 | { |
815 | 2ea815ca | blueswir1 | TCGv r_const; |
816 | 1a7b60e7 | blueswir1 | int l1;
|
817 | 1a7b60e7 | blueswir1 | |
818 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
819 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
820 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
821 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
822 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
823 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
824 | 1a7b60e7 | blueswir1 | } |
825 | 1a7b60e7 | blueswir1 | |
826 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
827 | 1a7b60e7 | blueswir1 | { |
828 | 1a7b60e7 | blueswir1 | int l1, l2;
|
829 | 1a7b60e7 | blueswir1 | |
830 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
831 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
832 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
833 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
834 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
835 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
836 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
837 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
838 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
839 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
840 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
841 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
842 | 1a7b60e7 | blueswir1 | } |
843 | 1a7b60e7 | blueswir1 | #endif
|
844 | 1a7b60e7 | blueswir1 | |
845 | 4af984a7 | blueswir1 | static inline void gen_op_div_cc(TCGv dst) |
846 | dc99a3f2 | blueswir1 | { |
847 | dc99a3f2 | blueswir1 | int l1;
|
848 | dc99a3f2 | blueswir1 | |
849 | ba28189b | blueswir1 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
850 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
851 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
852 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
853 | 5c6a0628 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
|
854 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
855 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
856 | dc99a3f2 | blueswir1 | } |
857 | dc99a3f2 | blueswir1 | |
858 | 4af984a7 | blueswir1 | static inline void gen_op_logic_cc(TCGv dst) |
859 | dc99a3f2 | blueswir1 | { |
860 | ba28189b | blueswir1 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
861 | ba28189b | blueswir1 | |
862 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
863 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
864 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
865 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
866 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
867 | ce5b3c3d | blueswir1 | #endif
|
868 | dc99a3f2 | blueswir1 | } |
869 | dc99a3f2 | blueswir1 | |
870 | 19f329ad | blueswir1 | // 1
|
871 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
872 | 19f329ad | blueswir1 | { |
873 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
874 | 19f329ad | blueswir1 | } |
875 | 19f329ad | blueswir1 | |
876 | 19f329ad | blueswir1 | // Z
|
877 | 19f329ad | blueswir1 | static inline void gen_op_eval_be(TCGv dst, TCGv src) |
878 | 19f329ad | blueswir1 | { |
879 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
880 | 19f329ad | blueswir1 | } |
881 | 19f329ad | blueswir1 | |
882 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
883 | 19f329ad | blueswir1 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) |
884 | 19f329ad | blueswir1 | { |
885 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
886 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
887 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
888 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
889 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
890 | 19f329ad | blueswir1 | } |
891 | 19f329ad | blueswir1 | |
892 | 19f329ad | blueswir1 | // N ^ V
|
893 | 19f329ad | blueswir1 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) |
894 | 19f329ad | blueswir1 | { |
895 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
896 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
897 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
898 | 19f329ad | blueswir1 | } |
899 | 19f329ad | blueswir1 | |
900 | 19f329ad | blueswir1 | // C | Z
|
901 | 19f329ad | blueswir1 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) |
902 | 19f329ad | blueswir1 | { |
903 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
904 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
905 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
906 | 19f329ad | blueswir1 | } |
907 | 19f329ad | blueswir1 | |
908 | 19f329ad | blueswir1 | // C
|
909 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) |
910 | 19f329ad | blueswir1 | { |
911 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
912 | 19f329ad | blueswir1 | } |
913 | 19f329ad | blueswir1 | |
914 | 19f329ad | blueswir1 | // V
|
915 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) |
916 | 19f329ad | blueswir1 | { |
917 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
918 | 19f329ad | blueswir1 | } |
919 | 19f329ad | blueswir1 | |
920 | 19f329ad | blueswir1 | // 0
|
921 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
922 | 19f329ad | blueswir1 | { |
923 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
924 | 19f329ad | blueswir1 | } |
925 | 19f329ad | blueswir1 | |
926 | 19f329ad | blueswir1 | // N
|
927 | 19f329ad | blueswir1 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) |
928 | 19f329ad | blueswir1 | { |
929 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
930 | 19f329ad | blueswir1 | } |
931 | 19f329ad | blueswir1 | |
932 | 19f329ad | blueswir1 | // !Z
|
933 | 19f329ad | blueswir1 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) |
934 | 19f329ad | blueswir1 | { |
935 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
936 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
937 | 19f329ad | blueswir1 | } |
938 | 19f329ad | blueswir1 | |
939 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
940 | 19f329ad | blueswir1 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) |
941 | 19f329ad | blueswir1 | { |
942 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
943 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
944 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
945 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
946 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
947 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
948 | 19f329ad | blueswir1 | } |
949 | 19f329ad | blueswir1 | |
950 | 19f329ad | blueswir1 | // !(N ^ V)
|
951 | 19f329ad | blueswir1 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) |
952 | 19f329ad | blueswir1 | { |
953 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
954 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
955 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
956 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
957 | 19f329ad | blueswir1 | } |
958 | 19f329ad | blueswir1 | |
959 | 19f329ad | blueswir1 | // !(C | Z)
|
960 | 19f329ad | blueswir1 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) |
961 | 19f329ad | blueswir1 | { |
962 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
963 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
964 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
965 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
966 | 19f329ad | blueswir1 | } |
967 | 19f329ad | blueswir1 | |
968 | 19f329ad | blueswir1 | // !C
|
969 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) |
970 | 19f329ad | blueswir1 | { |
971 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
972 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
973 | 19f329ad | blueswir1 | } |
974 | 19f329ad | blueswir1 | |
975 | 19f329ad | blueswir1 | // !N
|
976 | 19f329ad | blueswir1 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) |
977 | 19f329ad | blueswir1 | { |
978 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
979 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
980 | 19f329ad | blueswir1 | } |
981 | 19f329ad | blueswir1 | |
982 | 19f329ad | blueswir1 | // !V
|
983 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) |
984 | 19f329ad | blueswir1 | { |
985 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
986 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
987 | 19f329ad | blueswir1 | } |
988 | 19f329ad | blueswir1 | |
989 | 19f329ad | blueswir1 | /*
|
990 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
991 | 19f329ad | blueswir1 | 0 =
|
992 | 19f329ad | blueswir1 | 1 <
|
993 | 19f329ad | blueswir1 | 2 >
|
994 | 19f329ad | blueswir1 | 3 unordered
|
995 | 19f329ad | blueswir1 | */
|
996 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
997 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
998 | 19f329ad | blueswir1 | { |
999 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
1000 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); |
1001 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1002 | 19f329ad | blueswir1 | } |
1003 | 19f329ad | blueswir1 | |
1004 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
1005 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1006 | 19f329ad | blueswir1 | { |
1007 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
1008 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); |
1009 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1010 | 19f329ad | blueswir1 | } |
1011 | 19f329ad | blueswir1 | |
1012 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
1013 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
1014 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1015 | 19f329ad | blueswir1 | { |
1016 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1017 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1018 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1019 | 19f329ad | blueswir1 | } |
1020 | 19f329ad | blueswir1 | |
1021 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
1022 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
1023 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1024 | 19f329ad | blueswir1 | { |
1025 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1026 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1027 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1028 | 19f329ad | blueswir1 | } |
1029 | 19f329ad | blueswir1 | |
1030 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
1031 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
1032 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1033 | 19f329ad | blueswir1 | { |
1034 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1035 | 19f329ad | blueswir1 | } |
1036 | 19f329ad | blueswir1 | |
1037 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
1038 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
1039 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1040 | 19f329ad | blueswir1 | { |
1041 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1042 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1043 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1044 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1045 | 19f329ad | blueswir1 | } |
1046 | 19f329ad | blueswir1 | |
1047 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
1048 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
1049 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1050 | 19f329ad | blueswir1 | { |
1051 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1052 | 19f329ad | blueswir1 | } |
1053 | 19f329ad | blueswir1 | |
1054 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
1055 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
1056 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1057 | 19f329ad | blueswir1 | { |
1058 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1059 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1060 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1061 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1062 | 19f329ad | blueswir1 | } |
1063 | 19f329ad | blueswir1 | |
1064 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
1065 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
1066 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1067 | 19f329ad | blueswir1 | { |
1068 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1069 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1070 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1071 | 19f329ad | blueswir1 | } |
1072 | 19f329ad | blueswir1 | |
1073 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
1074 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
1075 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1076 | 19f329ad | blueswir1 | { |
1077 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1078 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1079 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1080 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1081 | 19f329ad | blueswir1 | } |
1082 | 19f329ad | blueswir1 | |
1083 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
1084 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
1085 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1086 | 19f329ad | blueswir1 | { |
1087 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1088 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1089 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1090 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1091 | 19f329ad | blueswir1 | } |
1092 | 19f329ad | blueswir1 | |
1093 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
1094 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
1095 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1096 | 19f329ad | blueswir1 | { |
1097 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1098 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1099 | 19f329ad | blueswir1 | } |
1100 | 19f329ad | blueswir1 | |
1101 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
1102 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
1103 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1104 | 19f329ad | blueswir1 | { |
1105 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1106 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1107 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1108 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1109 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1110 | 19f329ad | blueswir1 | } |
1111 | 19f329ad | blueswir1 | |
1112 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
1113 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
1114 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1115 | 19f329ad | blueswir1 | { |
1116 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1117 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1118 | 19f329ad | blueswir1 | } |
1119 | 19f329ad | blueswir1 | |
1120 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
1121 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
1122 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1123 | 19f329ad | blueswir1 | { |
1124 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1125 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1126 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1127 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1128 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1129 | 19f329ad | blueswir1 | } |
1130 | 19f329ad | blueswir1 | |
1131 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1132 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1133 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1134 | 19f329ad | blueswir1 | { |
1135 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1136 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1137 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1138 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1139 | 19f329ad | blueswir1 | } |
1140 | 19f329ad | blueswir1 | |
1141 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1142 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1143 | 83469015 | bellard | { |
1144 | 83469015 | bellard | int l1;
|
1145 | 83469015 | bellard | |
1146 | 83469015 | bellard | l1 = gen_new_label(); |
1147 | 83469015 | bellard | |
1148 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1149 | 83469015 | bellard | |
1150 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1151 | 83469015 | bellard | |
1152 | 83469015 | bellard | gen_set_label(l1); |
1153 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1154 | 83469015 | bellard | } |
1155 | 83469015 | bellard | |
1156 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1157 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1158 | 83469015 | bellard | { |
1159 | 83469015 | bellard | int l1;
|
1160 | 83469015 | bellard | |
1161 | 83469015 | bellard | l1 = gen_new_label(); |
1162 | 83469015 | bellard | |
1163 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1164 | 83469015 | bellard | |
1165 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1166 | 83469015 | bellard | |
1167 | 83469015 | bellard | gen_set_label(l1); |
1168 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1169 | 83469015 | bellard | } |
1170 | 83469015 | bellard | |
1171 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1172 | 19f329ad | blueswir1 | TCGv r_cond) |
1173 | 83469015 | bellard | { |
1174 | 83469015 | bellard | int l1, l2;
|
1175 | 83469015 | bellard | |
1176 | 83469015 | bellard | l1 = gen_new_label(); |
1177 | 83469015 | bellard | l2 = gen_new_label(); |
1178 | 19f329ad | blueswir1 | |
1179 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1180 | 83469015 | bellard | |
1181 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
1182 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1183 | 83469015 | bellard | |
1184 | 83469015 | bellard | gen_set_label(l1); |
1185 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
1186 | 83469015 | bellard | gen_set_label(l2); |
1187 | 83469015 | bellard | } |
1188 | 83469015 | bellard | |
1189 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
1190 | 4af984a7 | blueswir1 | have been set for a jump */
|
1191 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
1192 | 83469015 | bellard | { |
1193 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1194 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1195 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1196 | 83469015 | bellard | } |
1197 | 83469015 | bellard | } |
1198 | 83469015 | bellard | |
1199 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
1200 | 72cbca10 | bellard | { |
1201 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1202 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1203 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1204 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1205 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
1206 | 72cbca10 | bellard | } |
1207 | 72cbca10 | bellard | } |
1208 | 72cbca10 | bellard | |
1209 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
1210 | 72cbca10 | bellard | { |
1211 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1212 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
1213 | 72cbca10 | bellard | } |
1214 | 72cbca10 | bellard | |
1215 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
1216 | 0bee699e | bellard | { |
1217 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1218 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1219 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1220 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1221 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1222 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1223 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1224 | 0bee699e | bellard | } else {
|
1225 | 0bee699e | bellard | dc->pc = dc->npc; |
1226 | 0bee699e | bellard | } |
1227 | 0bee699e | bellard | } |
1228 | 0bee699e | bellard | |
1229 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1230 | 38bc628b | blueswir1 | { |
1231 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1232 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1233 | 38bc628b | blueswir1 | } |
1234 | 38bc628b | blueswir1 | |
1235 | 19f329ad | blueswir1 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1236 | 19f329ad | blueswir1 | { |
1237 | 19f329ad | blueswir1 | TCGv r_src; |
1238 | 3475187d | bellard | |
1239 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1240 | 19f329ad | blueswir1 | if (cc)
|
1241 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1242 | 19f329ad | blueswir1 | else
|
1243 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1244 | 3475187d | bellard | #else
|
1245 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1246 | 3475187d | bellard | #endif
|
1247 | 19f329ad | blueswir1 | switch (cond) {
|
1248 | 19f329ad | blueswir1 | case 0x0: |
1249 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1250 | 19f329ad | blueswir1 | break;
|
1251 | 19f329ad | blueswir1 | case 0x1: |
1252 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1253 | 19f329ad | blueswir1 | break;
|
1254 | 19f329ad | blueswir1 | case 0x2: |
1255 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1256 | 19f329ad | blueswir1 | break;
|
1257 | 19f329ad | blueswir1 | case 0x3: |
1258 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1259 | 19f329ad | blueswir1 | break;
|
1260 | 19f329ad | blueswir1 | case 0x4: |
1261 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1262 | 19f329ad | blueswir1 | break;
|
1263 | 19f329ad | blueswir1 | case 0x5: |
1264 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1265 | 19f329ad | blueswir1 | break;
|
1266 | 19f329ad | blueswir1 | case 0x6: |
1267 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1268 | 19f329ad | blueswir1 | break;
|
1269 | 19f329ad | blueswir1 | case 0x7: |
1270 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1271 | 19f329ad | blueswir1 | break;
|
1272 | 19f329ad | blueswir1 | case 0x8: |
1273 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1274 | 19f329ad | blueswir1 | break;
|
1275 | 19f329ad | blueswir1 | case 0x9: |
1276 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1277 | 19f329ad | blueswir1 | break;
|
1278 | 19f329ad | blueswir1 | case 0xa: |
1279 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1280 | 19f329ad | blueswir1 | break;
|
1281 | 19f329ad | blueswir1 | case 0xb: |
1282 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1283 | 19f329ad | blueswir1 | break;
|
1284 | 19f329ad | blueswir1 | case 0xc: |
1285 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1286 | 19f329ad | blueswir1 | break;
|
1287 | 19f329ad | blueswir1 | case 0xd: |
1288 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1289 | 19f329ad | blueswir1 | break;
|
1290 | 19f329ad | blueswir1 | case 0xe: |
1291 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1292 | 19f329ad | blueswir1 | break;
|
1293 | 19f329ad | blueswir1 | case 0xf: |
1294 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1295 | 19f329ad | blueswir1 | break;
|
1296 | 19f329ad | blueswir1 | } |
1297 | 19f329ad | blueswir1 | } |
1298 | 7a3f1944 | bellard | |
1299 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1300 | e8af50a3 | bellard | { |
1301 | 19f329ad | blueswir1 | unsigned int offset; |
1302 | 19f329ad | blueswir1 | |
1303 | 19f329ad | blueswir1 | switch (cc) {
|
1304 | 19f329ad | blueswir1 | default:
|
1305 | 19f329ad | blueswir1 | case 0x0: |
1306 | 19f329ad | blueswir1 | offset = 0;
|
1307 | 19f329ad | blueswir1 | break;
|
1308 | 19f329ad | blueswir1 | case 0x1: |
1309 | 19f329ad | blueswir1 | offset = 32 - 10; |
1310 | 19f329ad | blueswir1 | break;
|
1311 | 19f329ad | blueswir1 | case 0x2: |
1312 | 19f329ad | blueswir1 | offset = 34 - 10; |
1313 | 19f329ad | blueswir1 | break;
|
1314 | 19f329ad | blueswir1 | case 0x3: |
1315 | 19f329ad | blueswir1 | offset = 36 - 10; |
1316 | 19f329ad | blueswir1 | break;
|
1317 | 19f329ad | blueswir1 | } |
1318 | 19f329ad | blueswir1 | |
1319 | 19f329ad | blueswir1 | switch (cond) {
|
1320 | 19f329ad | blueswir1 | case 0x0: |
1321 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1322 | 19f329ad | blueswir1 | break;
|
1323 | 19f329ad | blueswir1 | case 0x1: |
1324 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1325 | 19f329ad | blueswir1 | break;
|
1326 | 19f329ad | blueswir1 | case 0x2: |
1327 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1328 | 19f329ad | blueswir1 | break;
|
1329 | 19f329ad | blueswir1 | case 0x3: |
1330 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1331 | 19f329ad | blueswir1 | break;
|
1332 | 19f329ad | blueswir1 | case 0x4: |
1333 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1334 | 19f329ad | blueswir1 | break;
|
1335 | 19f329ad | blueswir1 | case 0x5: |
1336 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1337 | 19f329ad | blueswir1 | break;
|
1338 | 19f329ad | blueswir1 | case 0x6: |
1339 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1340 | 19f329ad | blueswir1 | break;
|
1341 | 19f329ad | blueswir1 | case 0x7: |
1342 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1343 | 19f329ad | blueswir1 | break;
|
1344 | 19f329ad | blueswir1 | case 0x8: |
1345 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1346 | 19f329ad | blueswir1 | break;
|
1347 | 19f329ad | blueswir1 | case 0x9: |
1348 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1349 | 19f329ad | blueswir1 | break;
|
1350 | 19f329ad | blueswir1 | case 0xa: |
1351 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1352 | 19f329ad | blueswir1 | break;
|
1353 | 19f329ad | blueswir1 | case 0xb: |
1354 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1355 | 19f329ad | blueswir1 | break;
|
1356 | 19f329ad | blueswir1 | case 0xc: |
1357 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1358 | 19f329ad | blueswir1 | break;
|
1359 | 19f329ad | blueswir1 | case 0xd: |
1360 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1361 | 19f329ad | blueswir1 | break;
|
1362 | 19f329ad | blueswir1 | case 0xe: |
1363 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1364 | 19f329ad | blueswir1 | break;
|
1365 | 19f329ad | blueswir1 | case 0xf: |
1366 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1367 | 19f329ad | blueswir1 | break;
|
1368 | 19f329ad | blueswir1 | } |
1369 | e8af50a3 | bellard | } |
1370 | 00f219bf | blueswir1 | |
1371 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1372 | 00f219bf | blueswir1 | // Inverted logic
|
1373 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1374 | 00f219bf | blueswir1 | -1,
|
1375 | 00f219bf | blueswir1 | TCG_COND_NE, |
1376 | 00f219bf | blueswir1 | TCG_COND_GT, |
1377 | 00f219bf | blueswir1 | TCG_COND_GE, |
1378 | 00f219bf | blueswir1 | -1,
|
1379 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1380 | 00f219bf | blueswir1 | TCG_COND_LE, |
1381 | 00f219bf | blueswir1 | TCG_COND_LT, |
1382 | 00f219bf | blueswir1 | }; |
1383 | 19f329ad | blueswir1 | |
1384 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1385 | 19f329ad | blueswir1 | { |
1386 | 19f329ad | blueswir1 | int l1;
|
1387 | 19f329ad | blueswir1 | |
1388 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1389 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1390 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1391 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1392 | 19f329ad | blueswir1 | gen_set_label(l1); |
1393 | 19f329ad | blueswir1 | } |
1394 | 3475187d | bellard | #endif
|
1395 | cf495bcf | bellard | |
1396 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1397 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1398 | 4af984a7 | blueswir1 | TCGv r_cond) |
1399 | 7a3f1944 | bellard | { |
1400 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1401 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1402 | 5fafdf24 | ths | |
1403 | cf495bcf | bellard | if (cond == 0x0) { |
1404 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1405 | 0f8a249a | blueswir1 | if (a) {
|
1406 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1407 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1408 | 0f8a249a | blueswir1 | } else {
|
1409 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1410 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1411 | 0f8a249a | blueswir1 | } |
1412 | cf495bcf | bellard | } else if (cond == 0x8) { |
1413 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1414 | 0f8a249a | blueswir1 | if (a) {
|
1415 | 0f8a249a | blueswir1 | dc->pc = target; |
1416 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1417 | 0f8a249a | blueswir1 | } else {
|
1418 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1419 | 0f8a249a | blueswir1 | dc->npc = target; |
1420 | 0f8a249a | blueswir1 | } |
1421 | cf495bcf | bellard | } else {
|
1422 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1423 | 4af984a7 | blueswir1 | gen_cond(r_cond, cc, cond); |
1424 | 0f8a249a | blueswir1 | if (a) {
|
1425 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1426 | cf495bcf | bellard | dc->is_br = 1;
|
1427 | 0f8a249a | blueswir1 | } else {
|
1428 | cf495bcf | bellard | dc->pc = dc->npc; |
1429 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1430 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1431 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1432 | 0f8a249a | blueswir1 | } |
1433 | cf495bcf | bellard | } |
1434 | 7a3f1944 | bellard | } |
1435 | 7a3f1944 | bellard | |
1436 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1437 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1438 | 4af984a7 | blueswir1 | TCGv r_cond) |
1439 | e8af50a3 | bellard | { |
1440 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1441 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1442 | af7bf89b | bellard | |
1443 | e8af50a3 | bellard | if (cond == 0x0) { |
1444 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1445 | 0f8a249a | blueswir1 | if (a) {
|
1446 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1447 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1448 | 0f8a249a | blueswir1 | } else {
|
1449 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1450 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1451 | 0f8a249a | blueswir1 | } |
1452 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1453 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1454 | 0f8a249a | blueswir1 | if (a) {
|
1455 | 0f8a249a | blueswir1 | dc->pc = target; |
1456 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1457 | 0f8a249a | blueswir1 | } else {
|
1458 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1459 | 0f8a249a | blueswir1 | dc->npc = target; |
1460 | 0f8a249a | blueswir1 | } |
1461 | e8af50a3 | bellard | } else {
|
1462 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1463 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1464 | 0f8a249a | blueswir1 | if (a) {
|
1465 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1466 | e8af50a3 | bellard | dc->is_br = 1;
|
1467 | 0f8a249a | blueswir1 | } else {
|
1468 | e8af50a3 | bellard | dc->pc = dc->npc; |
1469 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1470 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1471 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1472 | 0f8a249a | blueswir1 | } |
1473 | e8af50a3 | bellard | } |
1474 | e8af50a3 | bellard | } |
1475 | e8af50a3 | bellard | |
1476 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1477 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1478 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1479 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1480 | 7a3f1944 | bellard | { |
1481 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1482 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1483 | 3475187d | bellard | |
1484 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1485 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1486 | 3475187d | bellard | if (a) {
|
1487 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1488 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1489 | 3475187d | bellard | } else {
|
1490 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1491 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1492 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1493 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1494 | 3475187d | bellard | } |
1495 | 7a3f1944 | bellard | } |
1496 | 7a3f1944 | bellard | |
1497 | 3475187d | bellard | static GenOpFunc * const gen_fcmps[4] = { |
1498 | 7e8c2b6c | blueswir1 | helper_fcmps, |
1499 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc1, |
1500 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc2, |
1501 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc3, |
1502 | 3475187d | bellard | }; |
1503 | 3475187d | bellard | |
1504 | 3475187d | bellard | static GenOpFunc * const gen_fcmpd[4] = { |
1505 | 7e8c2b6c | blueswir1 | helper_fcmpd, |
1506 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc1, |
1507 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc2, |
1508 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc3, |
1509 | 3475187d | bellard | }; |
1510 | 417454b0 | blueswir1 | |
1511 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpq[4] = { |
1512 | 7e8c2b6c | blueswir1 | helper_fcmpq, |
1513 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc1, |
1514 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc2, |
1515 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc3, |
1516 | 1f587329 | blueswir1 | }; |
1517 | 1f587329 | blueswir1 | |
1518 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmpes[4] = { |
1519 | 7e8c2b6c | blueswir1 | helper_fcmpes, |
1520 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc1, |
1521 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc2, |
1522 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc3, |
1523 | 417454b0 | blueswir1 | }; |
1524 | 417454b0 | blueswir1 | |
1525 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmped[4] = { |
1526 | 7e8c2b6c | blueswir1 | helper_fcmped, |
1527 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc1, |
1528 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc2, |
1529 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc3, |
1530 | 417454b0 | blueswir1 | }; |
1531 | 417454b0 | blueswir1 | |
1532 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpeq[4] = { |
1533 | 7e8c2b6c | blueswir1 | helper_fcmpeq, |
1534 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc1, |
1535 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc2, |
1536 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc3, |
1537 | 1f587329 | blueswir1 | }; |
1538 | 7e8c2b6c | blueswir1 | |
1539 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1540 | 7e8c2b6c | blueswir1 | { |
1541 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmps[fccno]); |
1542 | 7e8c2b6c | blueswir1 | } |
1543 | 7e8c2b6c | blueswir1 | |
1544 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1545 | 7e8c2b6c | blueswir1 | { |
1546 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); |
1547 | 7e8c2b6c | blueswir1 | } |
1548 | 7e8c2b6c | blueswir1 | |
1549 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1550 | 7e8c2b6c | blueswir1 | { |
1551 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); |
1552 | 7e8c2b6c | blueswir1 | } |
1553 | 7e8c2b6c | blueswir1 | |
1554 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1555 | 7e8c2b6c | blueswir1 | { |
1556 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); |
1557 | 7e8c2b6c | blueswir1 | } |
1558 | 7e8c2b6c | blueswir1 | |
1559 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1560 | 7e8c2b6c | blueswir1 | { |
1561 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmped[fccno]); |
1562 | 7e8c2b6c | blueswir1 | } |
1563 | 7e8c2b6c | blueswir1 | |
1564 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1565 | 7e8c2b6c | blueswir1 | { |
1566 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); |
1567 | 7e8c2b6c | blueswir1 | } |
1568 | 7e8c2b6c | blueswir1 | |
1569 | 7e8c2b6c | blueswir1 | #else
|
1570 | 7e8c2b6c | blueswir1 | |
1571 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1572 | 7e8c2b6c | blueswir1 | { |
1573 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmps); |
1574 | 7e8c2b6c | blueswir1 | } |
1575 | 7e8c2b6c | blueswir1 | |
1576 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1577 | 7e8c2b6c | blueswir1 | { |
1578 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpd); |
1579 | 7e8c2b6c | blueswir1 | } |
1580 | 7e8c2b6c | blueswir1 | |
1581 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1582 | 7e8c2b6c | blueswir1 | { |
1583 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpq); |
1584 | 7e8c2b6c | blueswir1 | } |
1585 | 7e8c2b6c | blueswir1 | |
1586 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1587 | 7e8c2b6c | blueswir1 | { |
1588 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpes); |
1589 | 7e8c2b6c | blueswir1 | } |
1590 | 7e8c2b6c | blueswir1 | |
1591 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1592 | 7e8c2b6c | blueswir1 | { |
1593 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmped); |
1594 | 7e8c2b6c | blueswir1 | } |
1595 | 7e8c2b6c | blueswir1 | |
1596 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1597 | 7e8c2b6c | blueswir1 | { |
1598 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq); |
1599 | 7e8c2b6c | blueswir1 | } |
1600 | 7e8c2b6c | blueswir1 | #endif
|
1601 | 7e8c2b6c | blueswir1 | |
1602 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1603 | 134d77a1 | blueswir1 | { |
1604 | 2ea815ca | blueswir1 | TCGv r_const; |
1605 | 2ea815ca | blueswir1 | |
1606 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1607 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1608 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1609 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
1610 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1611 | 134d77a1 | blueswir1 | } |
1612 | 134d77a1 | blueswir1 | |
1613 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1614 | a80dde08 | bellard | { |
1615 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1616 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1617 | 2ea815ca | blueswir1 | TCGv r_const; |
1618 | 2ea815ca | blueswir1 | |
1619 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1620 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1621 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
1622 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1623 | a80dde08 | bellard | dc->is_br = 1;
|
1624 | a80dde08 | bellard | return 1; |
1625 | a80dde08 | bellard | } |
1626 | a80dde08 | bellard | #endif
|
1627 | a80dde08 | bellard | return 0; |
1628 | a80dde08 | bellard | } |
1629 | a80dde08 | bellard | |
1630 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1631 | 7e8c2b6c | blueswir1 | { |
1632 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
1633 | 7e8c2b6c | blueswir1 | } |
1634 | 7e8c2b6c | blueswir1 | |
1635 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1636 | 7e8c2b6c | blueswir1 | { |
1637 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_clear_float_exceptions); |
1638 | 7e8c2b6c | blueswir1 | } |
1639 | 7e8c2b6c | blueswir1 | |
1640 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1641 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1642 | 0425bee5 | blueswir1 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1643 | 1a2fb1c0 | blueswir1 | { |
1644 | 95f9397c | blueswir1 | int asi;
|
1645 | 0425bee5 | blueswir1 | TCGv r_asi; |
1646 | 1a2fb1c0 | blueswir1 | |
1647 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1648 | 0425bee5 | blueswir1 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1649 | 0425bee5 | blueswir1 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); |
1650 | 1a2fb1c0 | blueswir1 | } else {
|
1651 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1652 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1653 | 1a2fb1c0 | blueswir1 | } |
1654 | 0425bee5 | blueswir1 | return r_asi;
|
1655 | 0425bee5 | blueswir1 | } |
1656 | 0425bee5 | blueswir1 | |
1657 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1658 | 77f193da | blueswir1 | int sign)
|
1659 | 0425bee5 | blueswir1 | { |
1660 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1661 | 0425bee5 | blueswir1 | |
1662 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1663 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1664 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1665 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); |
1666 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1667 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1668 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1669 | 1a2fb1c0 | blueswir1 | } |
1670 | 1a2fb1c0 | blueswir1 | |
1671 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1672 | 1a2fb1c0 | blueswir1 | { |
1673 | 2ea815ca | blueswir1 | TCGv r_asi, r_size; |
1674 | 1a2fb1c0 | blueswir1 | |
1675 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1676 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1677 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); |
1678 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1679 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1680 | 1a2fb1c0 | blueswir1 | } |
1681 | 1a2fb1c0 | blueswir1 | |
1682 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1683 | 1a2fb1c0 | blueswir1 | { |
1684 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_rd; |
1685 | 1a2fb1c0 | blueswir1 | |
1686 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1687 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1688 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1689 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); |
1690 | 2ea815ca | blueswir1 | tcg_temp_free(r_rd); |
1691 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1692 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1693 | 1a2fb1c0 | blueswir1 | } |
1694 | 1a2fb1c0 | blueswir1 | |
1695 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1696 | 1a2fb1c0 | blueswir1 | { |
1697 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_rd; |
1698 | 1a2fb1c0 | blueswir1 | |
1699 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1700 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1701 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1702 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); |
1703 | 2ea815ca | blueswir1 | tcg_temp_free(r_rd); |
1704 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1705 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1706 | 1a2fb1c0 | blueswir1 | } |
1707 | 1a2fb1c0 | blueswir1 | |
1708 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1709 | 1a2fb1c0 | blueswir1 | { |
1710 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1711 | 1a2fb1c0 | blueswir1 | |
1712 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1713 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1714 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1715 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1716 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1717 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
1718 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1719 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1720 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1721 | 1a2fb1c0 | blueswir1 | } |
1722 | 1a2fb1c0 | blueswir1 | |
1723 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1724 | 1a2fb1c0 | blueswir1 | { |
1725 | db166940 | blueswir1 | TCGv r_asi, r_rd; |
1726 | 1a2fb1c0 | blueswir1 | |
1727 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1728 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1729 | db166940 | blueswir1 | tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd); |
1730 | db166940 | blueswir1 | tcg_temp_free(r_rd); |
1731 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1732 | 0425bee5 | blueswir1 | } |
1733 | 0425bee5 | blueswir1 | |
1734 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1735 | 0425bee5 | blueswir1 | { |
1736 | 2ea815ca | blueswir1 | TCGv r_temp, r_asi, r_size; |
1737 | 0425bee5 | blueswir1 | |
1738 | 8d96d209 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
1739 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1740 | 4af984a7 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, |
1741 | 0425bee5 | blueswir1 | r_temp); |
1742 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
1743 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1744 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1745 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1746 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1747 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1748 | 1a2fb1c0 | blueswir1 | } |
1749 | 1a2fb1c0 | blueswir1 | |
1750 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1751 | 77f193da | blueswir1 | int rd)
|
1752 | 1a2fb1c0 | blueswir1 | { |
1753 | 1a2fb1c0 | blueswir1 | TCGv r_val1, r_asi; |
1754 | 1a2fb1c0 | blueswir1 | |
1755 | ef28fd86 | blueswir1 | r_val1 = tcg_temp_new(TCG_TYPE_TL); |
1756 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1757 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1758 | 4af984a7 | blueswir1 | tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); |
1759 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1760 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1761 | 1a2fb1c0 | blueswir1 | } |
1762 | 1a2fb1c0 | blueswir1 | |
1763 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1764 | 77f193da | blueswir1 | int rd)
|
1765 | 1a2fb1c0 | blueswir1 | { |
1766 | 8911f501 | blueswir1 | TCGv r_asi; |
1767 | 1a2fb1c0 | blueswir1 | |
1768 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1769 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1770 | 4af984a7 | blueswir1 | tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); |
1771 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1772 | 1a2fb1c0 | blueswir1 | } |
1773 | 1a2fb1c0 | blueswir1 | |
1774 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1775 | 1a2fb1c0 | blueswir1 | |
1776 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1777 | 77f193da | blueswir1 | int sign)
|
1778 | 1a2fb1c0 | blueswir1 | { |
1779 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1780 | 1a2fb1c0 | blueswir1 | |
1781 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1782 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1783 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1784 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1785 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1786 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1787 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1788 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1789 | 1a2fb1c0 | blueswir1 | } |
1790 | 1a2fb1c0 | blueswir1 | |
1791 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1792 | 1a2fb1c0 | blueswir1 | { |
1793 | 2ea815ca | blueswir1 | TCGv r_asi, r_size; |
1794 | 1a2fb1c0 | blueswir1 | |
1795 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1796 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1797 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1798 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1799 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1800 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1801 | 1a2fb1c0 | blueswir1 | } |
1802 | 1a2fb1c0 | blueswir1 | |
1803 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1804 | 1a2fb1c0 | blueswir1 | { |
1805 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1806 | 1a2fb1c0 | blueswir1 | |
1807 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1808 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1809 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1810 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1811 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1812 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
1813 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1814 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1815 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1816 | 1a2fb1c0 | blueswir1 | } |
1817 | 1a2fb1c0 | blueswir1 | |
1818 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1819 | 1a2fb1c0 | blueswir1 | { |
1820 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1821 | 1a2fb1c0 | blueswir1 | |
1822 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1823 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1824 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1825 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1826 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1827 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1828 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1829 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1830 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1831 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1832 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1833 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1834 | 0425bee5 | blueswir1 | } |
1835 | 0425bee5 | blueswir1 | |
1836 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1837 | 0425bee5 | blueswir1 | { |
1838 | 2ea815ca | blueswir1 | TCGv r_temp, r_asi, r_size; |
1839 | 0425bee5 | blueswir1 | |
1840 | 8d96d209 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
1841 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1842 | 4af984a7 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); |
1843 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
1844 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1845 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1846 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1847 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1848 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1849 | 1a2fb1c0 | blueswir1 | } |
1850 | 1a2fb1c0 | blueswir1 | #endif
|
1851 | 1a2fb1c0 | blueswir1 | |
1852 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1853 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1854 | 1a2fb1c0 | blueswir1 | { |
1855 | 2ea815ca | blueswir1 | TCGv r_val, r_asi, r_size; |
1856 | 1a2fb1c0 | blueswir1 | |
1857 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1858 | 1a2fb1c0 | blueswir1 | |
1859 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1860 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1861 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1862 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); |
1863 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1864 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1865 | 2ea815ca | blueswir1 | tcg_temp_free(r_val); |
1866 | 1a2fb1c0 | blueswir1 | } |
1867 | 1a2fb1c0 | blueswir1 | #endif
|
1868 | 1a2fb1c0 | blueswir1 | |
1869 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1870 | 9322a4bf | blueswir1 | { |
1871 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1872 | 9322a4bf | blueswir1 | unsigned int rs1; |
1873 | 9322a4bf | blueswir1 | |
1874 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1875 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1876 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1877 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1878 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1879 | 9322a4bf | blueswir1 | else
|
1880 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1881 | 9322a4bf | blueswir1 | return r_rs1;
|
1882 | 9322a4bf | blueswir1 | } |
1883 | 9322a4bf | blueswir1 | |
1884 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1885 | a49d9390 | blueswir1 | { |
1886 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1887 | a49d9390 | blueswir1 | unsigned int rs2; |
1888 | a49d9390 | blueswir1 | |
1889 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1890 | a49d9390 | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
1891 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl((int)rs2); // XXX how to free? |
1892 | a49d9390 | blueswir1 | } else { /* register */ |
1893 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1894 | a49d9390 | blueswir1 | if (rs2 == 0) |
1895 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1896 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1897 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1898 | a49d9390 | blueswir1 | else
|
1899 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1900 | a49d9390 | blueswir1 | } |
1901 | a49d9390 | blueswir1 | return r_rs2;
|
1902 | a49d9390 | blueswir1 | } |
1903 | a49d9390 | blueswir1 | |
1904 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1905 | 64a88d5d | blueswir1 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ |
1906 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1907 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1908 | 64a88d5d | blueswir1 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ |
1909 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1910 | 64a88d5d | blueswir1 | |
1911 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1912 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1913 | cf495bcf | bellard | { |
1914 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1915 | 7a3f1944 | bellard | |
1916 | a8c768c0 | blueswir1 | if (unlikely(loglevel & CPU_LOG_TB_OP))
|
1917 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1918 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1919 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1920 | 7a3f1944 | bellard | |
1921 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1922 | 6ae20372 | blueswir1 | |
1923 | 5c6a0628 | blueswir1 | cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
|
1924 | 5c6a0628 | blueswir1 | cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
|
1925 | 6ae20372 | blueswir1 | |
1926 | cf495bcf | bellard | switch (opc) {
|
1927 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1928 | 0f8a249a | blueswir1 | { |
1929 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1930 | 0f8a249a | blueswir1 | int32_t target; |
1931 | 0f8a249a | blueswir1 | switch (xop) {
|
1932 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1933 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1934 | 0f8a249a | blueswir1 | { |
1935 | 0f8a249a | blueswir1 | int cc;
|
1936 | 0f8a249a | blueswir1 | |
1937 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1938 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1939 | 0f8a249a | blueswir1 | target <<= 2;
|
1940 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1941 | 0f8a249a | blueswir1 | if (cc == 0) |
1942 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1943 | 0f8a249a | blueswir1 | else if (cc == 2) |
1944 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1945 | 0f8a249a | blueswir1 | else
|
1946 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1947 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1948 | 0f8a249a | blueswir1 | } |
1949 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1950 | 0f8a249a | blueswir1 | { |
1951 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1952 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1953 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1954 | 0f8a249a | blueswir1 | target <<= 2;
|
1955 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1956 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1957 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1958 | 0f8a249a | blueswir1 | } |
1959 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1960 | 0f8a249a | blueswir1 | { |
1961 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1962 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1963 | a80dde08 | bellard | goto jmp_insn;
|
1964 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1965 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1966 | 0f8a249a | blueswir1 | target <<= 2;
|
1967 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1968 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1969 | 0f8a249a | blueswir1 | } |
1970 | a4d17f19 | blueswir1 | #else
|
1971 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1972 | 0f8a249a | blueswir1 | { |
1973 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1974 | 0f8a249a | blueswir1 | } |
1975 | 0f8a249a | blueswir1 | #endif
|
1976 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1977 | 0f8a249a | blueswir1 | { |
1978 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1979 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1980 | 0f8a249a | blueswir1 | target <<= 2;
|
1981 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1982 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1983 | 0f8a249a | blueswir1 | } |
1984 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1985 | 0f8a249a | blueswir1 | { |
1986 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1987 | a80dde08 | bellard | goto jmp_insn;
|
1988 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1989 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1990 | 0f8a249a | blueswir1 | target <<= 2;
|
1991 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1992 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1993 | 0f8a249a | blueswir1 | } |
1994 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1995 | 0f8a249a | blueswir1 | if (rd) { // nop |
1996 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1997 | 2ea815ca | blueswir1 | TCGv r_const; |
1998 | 2ea815ca | blueswir1 | |
1999 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
2000 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2001 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2002 | 0f8a249a | blueswir1 | } |
2003 | 0f8a249a | blueswir1 | break;
|
2004 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
2005 | 0f8a249a | blueswir1 | default:
|
2006 | 3475187d | bellard | goto illegal_insn;
|
2007 | 0f8a249a | blueswir1 | } |
2008 | 0f8a249a | blueswir1 | break;
|
2009 | 0f8a249a | blueswir1 | } |
2010 | 0f8a249a | blueswir1 | break;
|
2011 | cf495bcf | bellard | case 1: |
2012 | 0f8a249a | blueswir1 | /*CALL*/ {
|
2013 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
2014 | 2ea815ca | blueswir1 | TCGv r_const; |
2015 | cf495bcf | bellard | |
2016 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2017 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
2018 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2019 | 0f8a249a | blueswir1 | target += dc->pc; |
2020 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
2021 | 0f8a249a | blueswir1 | dc->npc = target; |
2022 | 0f8a249a | blueswir1 | } |
2023 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2024 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2025 | 0f8a249a | blueswir1 | { |
2026 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2027 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2028 | cf495bcf | bellard | int cond;
|
2029 | 3475187d | bellard | |
2030 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2031 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
2032 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
2033 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
2034 | cf495bcf | bellard | } else {
|
2035 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2036 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2037 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2038 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2039 | 6f551262 | blueswir1 | } else
|
2040 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
2041 | cf495bcf | bellard | } |
2042 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
2043 | cf495bcf | bellard | if (cond == 0x8) { |
2044 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2045 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_trap, cpu_dst); |
2046 | af7bf89b | bellard | } else if (cond != 0) { |
2047 | 748b9d8e | blueswir1 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
2048 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2049 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2050 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2051 | 748b9d8e | blueswir1 | |
2052 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2053 | 0f8a249a | blueswir1 | if (cc == 0) |
2054 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2055 | 0f8a249a | blueswir1 | else if (cc == 2) |
2056 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
2057 | 0f8a249a | blueswir1 | else
|
2058 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2059 | 3475187d | bellard | #else
|
2060 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2061 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2062 | 3475187d | bellard | #endif
|
2063 | 6ae20372 | blueswir1 | tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
2064 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
2065 | cf495bcf | bellard | } |
2066 | a80dde08 | bellard | gen_op_next_insn(); |
2067 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2068 | a80dde08 | bellard | dc->is_br = 1;
|
2069 | a80dde08 | bellard | goto jmp_insn;
|
2070 | cf495bcf | bellard | } else if (xop == 0x28) { |
2071 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2072 | cf495bcf | bellard | switch(rs1) {
|
2073 | cf495bcf | bellard | case 0: /* rdy */ |
2074 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2075 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2076 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2077 | 65fe7b09 | blueswir1 | II */
|
2078 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2079 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2080 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2081 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2082 | 65fe7b09 | blueswir1 | microSPARC II */
|
2083 | 65fe7b09 | blueswir1 | #endif
|
2084 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2085 | 77f193da | blueswir1 | offsetof(CPUSPARCState, y)); |
2086 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2087 | cf495bcf | bellard | break;
|
2088 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2089 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2090 | 6ae20372 | blueswir1 | tcg_gen_helper_1_0(helper_rdccr, cpu_dst); |
2091 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2092 | 3475187d | bellard | break;
|
2093 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2094 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2095 | 77f193da | blueswir1 | offsetof(CPUSPARCState, asi)); |
2096 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2097 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2098 | 3475187d | bellard | break;
|
2099 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2100 | ccd4a219 | blueswir1 | { |
2101 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2102 | ccd4a219 | blueswir1 | |
2103 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2104 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2105 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2106 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
2107 | ccd4a219 | blueswir1 | r_tickptr); |
2108 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2109 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2110 | ccd4a219 | blueswir1 | } |
2111 | 3475187d | bellard | break;
|
2112 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2113 | 2ea815ca | blueswir1 | { |
2114 | 2ea815ca | blueswir1 | TCGv r_const; |
2115 | 2ea815ca | blueswir1 | |
2116 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2117 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2118 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2119 | 2ea815ca | blueswir1 | } |
2120 | 0f8a249a | blueswir1 | break;
|
2121 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2122 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2123 | 77f193da | blueswir1 | offsetof(CPUSPARCState, fprs)); |
2124 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2125 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2126 | 3475187d | bellard | break;
|
2127 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2128 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2129 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2130 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2131 | 725cb90b | bellard | goto jmp_insn;
|
2132 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2133 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gsr)); |
2134 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2135 | 725cb90b | bellard | break;
|
2136 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2137 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2138 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tick_cmpr)); |
2139 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2140 | 83469015 | bellard | break;
|
2141 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2142 | ccd4a219 | blueswir1 | { |
2143 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2144 | ccd4a219 | blueswir1 | |
2145 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2146 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2147 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2148 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
2149 | ccd4a219 | blueswir1 | r_tickptr); |
2150 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2151 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2152 | ccd4a219 | blueswir1 | } |
2153 | 83469015 | bellard | break;
|
2154 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2155 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2156 | 77f193da | blueswir1 | offsetof(CPUSPARCState, stick_cmpr)); |
2157 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2158 | 83469015 | bellard | break;
|
2159 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2160 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2161 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2162 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2163 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2164 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
2165 | 3475187d | bellard | #endif
|
2166 | 3475187d | bellard | default:
|
2167 | cf495bcf | bellard | goto illegal_insn;
|
2168 | cf495bcf | bellard | } |
2169 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2170 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2171 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2172 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2173 | 0f8a249a | blueswir1 | goto priv_insn;
|
2174 | 6ae20372 | blueswir1 | tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); |
2175 | e9ebed4d | blueswir1 | #else
|
2176 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2177 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2178 | e9ebed4d | blueswir1 | goto priv_insn;
|
2179 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2180 | e9ebed4d | blueswir1 | switch (rs1) {
|
2181 | e9ebed4d | blueswir1 | case 0: // hpstate |
2182 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2183 | e9ebed4d | blueswir1 | break;
|
2184 | e9ebed4d | blueswir1 | case 1: // htstate |
2185 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2186 | e9ebed4d | blueswir1 | break;
|
2187 | e9ebed4d | blueswir1 | case 3: // hintp |
2188 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2189 | 77f193da | blueswir1 | offsetof(CPUSPARCState, hintp)); |
2190 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2191 | e9ebed4d | blueswir1 | break;
|
2192 | e9ebed4d | blueswir1 | case 5: // htba |
2193 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2194 | 77f193da | blueswir1 | offsetof(CPUSPARCState, htba)); |
2195 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2196 | e9ebed4d | blueswir1 | break;
|
2197 | e9ebed4d | blueswir1 | case 6: // hver |
2198 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2199 | 77f193da | blueswir1 | offsetof(CPUSPARCState, hver)); |
2200 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2201 | e9ebed4d | blueswir1 | break;
|
2202 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2203 | 8d7d8c4b | blueswir1 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2204 | 8d7d8c4b | blueswir1 | offsetof(CPUSPARCState, hstick_cmpr)); |
2205 | e9ebed4d | blueswir1 | break;
|
2206 | e9ebed4d | blueswir1 | default:
|
2207 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2208 | e9ebed4d | blueswir1 | } |
2209 | e9ebed4d | blueswir1 | #endif
|
2210 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2211 | e8af50a3 | bellard | break;
|
2212 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2213 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2214 | 0f8a249a | blueswir1 | goto priv_insn;
|
2215 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2216 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2217 | 0f8a249a | blueswir1 | switch (rs1) {
|
2218 | 0f8a249a | blueswir1 | case 0: // tpc |
2219 | 375ee38b | blueswir1 | { |
2220 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2221 | 375ee38b | blueswir1 | |
2222 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2223 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2224 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2225 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2226 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2227 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2228 | 375ee38b | blueswir1 | } |
2229 | 0f8a249a | blueswir1 | break;
|
2230 | 0f8a249a | blueswir1 | case 1: // tnpc |
2231 | 375ee38b | blueswir1 | { |
2232 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2233 | 375ee38b | blueswir1 | |
2234 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2235 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2236 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2237 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2238 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2239 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2240 | 375ee38b | blueswir1 | } |
2241 | 0f8a249a | blueswir1 | break;
|
2242 | 0f8a249a | blueswir1 | case 2: // tstate |
2243 | 375ee38b | blueswir1 | { |
2244 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2245 | 375ee38b | blueswir1 | |
2246 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2247 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2248 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2249 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2250 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2251 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2252 | 375ee38b | blueswir1 | } |
2253 | 0f8a249a | blueswir1 | break;
|
2254 | 0f8a249a | blueswir1 | case 3: // tt |
2255 | 375ee38b | blueswir1 | { |
2256 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2257 | 375ee38b | blueswir1 | |
2258 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2259 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2260 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2261 | ece43b8d | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, r_tsptr, |
2262 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2263 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2264 | 375ee38b | blueswir1 | } |
2265 | 0f8a249a | blueswir1 | break;
|
2266 | 0f8a249a | blueswir1 | case 4: // tick |
2267 | ccd4a219 | blueswir1 | { |
2268 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2269 | ccd4a219 | blueswir1 | |
2270 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2271 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2272 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2273 | ece43b8d | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, |
2274 | ccd4a219 | blueswir1 | r_tickptr); |
2275 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2276 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2277 | ccd4a219 | blueswir1 | } |
2278 | 0f8a249a | blueswir1 | break;
|
2279 | 0f8a249a | blueswir1 | case 5: // tba |
2280 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2281 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tbr)); |
2282 | 0f8a249a | blueswir1 | break;
|
2283 | 0f8a249a | blueswir1 | case 6: // pstate |
2284 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2285 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2286 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2287 | 0f8a249a | blueswir1 | break;
|
2288 | 0f8a249a | blueswir1 | case 7: // tl |
2289 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2290 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2291 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2292 | 0f8a249a | blueswir1 | break;
|
2293 | 0f8a249a | blueswir1 | case 8: // pil |
2294 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2295 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2296 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2297 | 0f8a249a | blueswir1 | break;
|
2298 | 0f8a249a | blueswir1 | case 9: // cwp |
2299 | ece43b8d | blueswir1 | tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0); |
2300 | 0f8a249a | blueswir1 | break;
|
2301 | 0f8a249a | blueswir1 | case 10: // cansave |
2302 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2303 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2304 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2305 | 0f8a249a | blueswir1 | break;
|
2306 | 0f8a249a | blueswir1 | case 11: // canrestore |
2307 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2308 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2309 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2310 | 0f8a249a | blueswir1 | break;
|
2311 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2312 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2313 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2314 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2315 | 0f8a249a | blueswir1 | break;
|
2316 | 0f8a249a | blueswir1 | case 13: // otherwin |
2317 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2318 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2319 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2320 | 0f8a249a | blueswir1 | break;
|
2321 | 0f8a249a | blueswir1 | case 14: // wstate |
2322 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2323 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2324 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2325 | 0f8a249a | blueswir1 | break;
|
2326 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2327 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2328 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2329 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2330 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2331 | e9ebed4d | blueswir1 | break;
|
2332 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2333 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2334 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2335 | e9ebed4d | blueswir1 | goto priv_insn;
|
2336 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2337 | 77f193da | blueswir1 | offsetof(CPUSPARCState, ssr)); |
2338 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2339 | e9ebed4d | blueswir1 | break;
|
2340 | 0f8a249a | blueswir1 | case 31: // ver |
2341 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
2342 | 77f193da | blueswir1 | offsetof(CPUSPARCState, version)); |
2343 | 0f8a249a | blueswir1 | break;
|
2344 | 0f8a249a | blueswir1 | case 15: // fq |
2345 | 0f8a249a | blueswir1 | default:
|
2346 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2347 | 0f8a249a | blueswir1 | } |
2348 | 3475187d | bellard | #else
|
2349 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2350 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wim)); |
2351 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2352 | 3475187d | bellard | #endif
|
2353 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2354 | e8af50a3 | bellard | break;
|
2355 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2356 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2357 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2358 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_flushw); |
2359 | 3475187d | bellard | #else
|
2360 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2361 | 0f8a249a | blueswir1 | goto priv_insn;
|
2362 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr)); |
2363 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2364 | 3475187d | bellard | #endif
|
2365 | e8af50a3 | bellard | break;
|
2366 | e8af50a3 | bellard | #endif
|
2367 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2368 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2369 | a80dde08 | bellard | goto jmp_insn;
|
2370 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2371 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2372 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2373 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2374 | 0f8a249a | blueswir1 | switch (xop) {
|
2375 | 0f8a249a | blueswir1 | case 0x1: /* fmovs */ |
2376 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2377 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2378 | 0f8a249a | blueswir1 | break;
|
2379 | 0f8a249a | blueswir1 | case 0x5: /* fnegs */ |
2380 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2381 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegs); |
2382 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2383 | 0f8a249a | blueswir1 | break;
|
2384 | 0f8a249a | blueswir1 | case 0x9: /* fabss */ |
2385 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2386 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabss); |
2387 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2388 | 0f8a249a | blueswir1 | break;
|
2389 | 0f8a249a | blueswir1 | case 0x29: /* fsqrts */ |
2390 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FSQRT); |
2391 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2392 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2393 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrts); |
2394 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2395 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2396 | 0f8a249a | blueswir1 | break;
|
2397 | 0f8a249a | blueswir1 | case 0x2a: /* fsqrtd */ |
2398 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FSQRT); |
2399 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2400 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2401 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtd); |
2402 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2403 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2404 | 0f8a249a | blueswir1 | break;
|
2405 | 0f8a249a | blueswir1 | case 0x2b: /* fsqrtq */ |
2406 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2407 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2408 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2409 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtq); |
2410 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2411 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2412 | 1f587329 | blueswir1 | break;
|
2413 | 0f8a249a | blueswir1 | case 0x41: |
2414 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2415 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2416 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2417 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fadds); |
2418 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2419 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2420 | 0f8a249a | blueswir1 | break;
|
2421 | 0f8a249a | blueswir1 | case 0x42: |
2422 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2423 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2424 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2425 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddd); |
2426 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2427 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2428 | 0f8a249a | blueswir1 | break;
|
2429 | 0f8a249a | blueswir1 | case 0x43: /* faddq */ |
2430 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2431 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2432 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2433 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2434 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddq); |
2435 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2436 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2437 | 1f587329 | blueswir1 | break;
|
2438 | 0f8a249a | blueswir1 | case 0x45: |
2439 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2440 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2441 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2442 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubs); |
2443 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2444 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2445 | 0f8a249a | blueswir1 | break;
|
2446 | 0f8a249a | blueswir1 | case 0x46: |
2447 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2448 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2449 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2450 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubd); |
2451 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2452 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2453 | 0f8a249a | blueswir1 | break;
|
2454 | 0f8a249a | blueswir1 | case 0x47: /* fsubq */ |
2455 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2456 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2457 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2458 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2459 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubq); |
2460 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2461 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2462 | 1f587329 | blueswir1 | break;
|
2463 | 64a88d5d | blueswir1 | case 0x49: /* fmuls */ |
2464 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2465 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2466 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2467 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2468 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuls); |
2469 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2470 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2471 | 0f8a249a | blueswir1 | break;
|
2472 | 64a88d5d | blueswir1 | case 0x4a: /* fmuld */ |
2473 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2474 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2475 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2476 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2477 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld); |
2478 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2479 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2480 | 0f8a249a | blueswir1 | break;
|
2481 | 0f8a249a | blueswir1 | case 0x4b: /* fmulq */ |
2482 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2483 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2484 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2485 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2486 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2487 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmulq); |
2488 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2489 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2490 | 1f587329 | blueswir1 | break;
|
2491 | 0f8a249a | blueswir1 | case 0x4d: |
2492 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2493 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2494 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2495 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivs); |
2496 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2497 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2498 | 0f8a249a | blueswir1 | break;
|
2499 | 0f8a249a | blueswir1 | case 0x4e: |
2500 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2501 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2502 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2503 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivd); |
2504 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2505 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2506 | 0f8a249a | blueswir1 | break;
|
2507 | 0f8a249a | blueswir1 | case 0x4f: /* fdivq */ |
2508 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2509 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2510 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2511 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2512 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivq); |
2513 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2514 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2515 | 1f587329 | blueswir1 | break;
|
2516 | 0f8a249a | blueswir1 | case 0x69: |
2517 | e30b4678 | blueswir1 | CHECK_FPU_FEATURE(dc, FSMULD); |
2518 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2519 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2520 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2521 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsmuld); |
2522 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2523 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2524 | 0f8a249a | blueswir1 | break;
|
2525 | 0f8a249a | blueswir1 | case 0x6e: /* fdmulq */ |
2526 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2527 | 1f587329 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2528 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2529 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2530 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdmulq); |
2531 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2532 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2533 | 1f587329 | blueswir1 | break;
|
2534 | 0f8a249a | blueswir1 | case 0xc4: |
2535 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2536 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2537 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitos); |
2538 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2539 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2540 | 0f8a249a | blueswir1 | break;
|
2541 | 0f8a249a | blueswir1 | case 0xc6: |
2542 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2543 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2544 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtos); |
2545 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2546 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2547 | 0f8a249a | blueswir1 | break;
|
2548 | 0f8a249a | blueswir1 | case 0xc7: /* fqtos */ |
2549 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2550 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2551 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2552 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtos); |
2553 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2554 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2555 | 1f587329 | blueswir1 | break;
|
2556 | 0f8a249a | blueswir1 | case 0xc8: |
2557 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2558 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitod); |
2559 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2560 | 0f8a249a | blueswir1 | break;
|
2561 | 0f8a249a | blueswir1 | case 0xc9: |
2562 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2563 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstod); |
2564 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2565 | 0f8a249a | blueswir1 | break;
|
2566 | 0f8a249a | blueswir1 | case 0xcb: /* fqtod */ |
2567 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2568 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2569 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2570 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtod); |
2571 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2572 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2573 | 1f587329 | blueswir1 | break;
|
2574 | 0f8a249a | blueswir1 | case 0xcc: /* fitoq */ |
2575 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2576 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2577 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitoq); |
2578 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2579 | 1f587329 | blueswir1 | break;
|
2580 | 0f8a249a | blueswir1 | case 0xcd: /* fstoq */ |
2581 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2582 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2583 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoq); |
2584 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2585 | 1f587329 | blueswir1 | break;
|
2586 | 0f8a249a | blueswir1 | case 0xce: /* fdtoq */ |
2587 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2588 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2589 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoq); |
2590 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2591 | 1f587329 | blueswir1 | break;
|
2592 | 0f8a249a | blueswir1 | case 0xd1: |
2593 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2594 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2595 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoi); |
2596 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2597 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2598 | 0f8a249a | blueswir1 | break;
|
2599 | 0f8a249a | blueswir1 | case 0xd2: |
2600 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2601 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2602 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoi); |
2603 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2604 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2605 | 0f8a249a | blueswir1 | break;
|
2606 | 0f8a249a | blueswir1 | case 0xd3: /* fqtoi */ |
2607 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2608 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2609 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2610 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtoi); |
2611 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2612 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2613 | 1f587329 | blueswir1 | break;
|
2614 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2615 | 0f8a249a | blueswir1 | case 0x2: /* V9 fmovd */ |
2616 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2617 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2618 | 0f8a249a | blueswir1 | break;
|
2619 | 1f587329 | blueswir1 | case 0x3: /* V9 fmovq */ |
2620 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2621 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2622 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2623 | 1f587329 | blueswir1 | break;
|
2624 | 0f8a249a | blueswir1 | case 0x6: /* V9 fnegd */ |
2625 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2626 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegd); |
2627 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2628 | 0f8a249a | blueswir1 | break;
|
2629 | 1f587329 | blueswir1 | case 0x7: /* V9 fnegq */ |
2630 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2631 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2632 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegq); |
2633 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2634 | 1f587329 | blueswir1 | break;
|
2635 | 0f8a249a | blueswir1 | case 0xa: /* V9 fabsd */ |
2636 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2637 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsd); |
2638 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2639 | 0f8a249a | blueswir1 | break;
|
2640 | 1f587329 | blueswir1 | case 0xb: /* V9 fabsq */ |
2641 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2642 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2643 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsq); |
2644 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2645 | 1f587329 | blueswir1 | break;
|
2646 | 0f8a249a | blueswir1 | case 0x81: /* V9 fstox */ |
2647 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2648 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2649 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstox); |
2650 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2651 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2652 | 0f8a249a | blueswir1 | break;
|
2653 | 0f8a249a | blueswir1 | case 0x82: /* V9 fdtox */ |
2654 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2655 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2656 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtox); |
2657 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2658 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2659 | 0f8a249a | blueswir1 | break;
|
2660 | 1f587329 | blueswir1 | case 0x83: /* V9 fqtox */ |
2661 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2662 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2663 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2664 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtox); |
2665 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2666 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2667 | 1f587329 | blueswir1 | break;
|
2668 | 0f8a249a | blueswir1 | case 0x84: /* V9 fxtos */ |
2669 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2670 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2671 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtos); |
2672 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2673 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2674 | 0f8a249a | blueswir1 | break;
|
2675 | 0f8a249a | blueswir1 | case 0x88: /* V9 fxtod */ |
2676 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2677 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2678 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtod); |
2679 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2680 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2681 | 0f8a249a | blueswir1 | break;
|
2682 | 0f8a249a | blueswir1 | case 0x8c: /* V9 fxtoq */ |
2683 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2684 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2685 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2686 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtoq); |
2687 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2688 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2689 | 1f587329 | blueswir1 | break;
|
2690 | 1f587329 | blueswir1 | #endif
|
2691 | 0f8a249a | blueswir1 | default:
|
2692 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2693 | 0f8a249a | blueswir1 | } |
2694 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2695 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2696 | 0f8a249a | blueswir1 | int cond;
|
2697 | 3475187d | bellard | #endif
|
2698 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2699 | a80dde08 | bellard | goto jmp_insn;
|
2700 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2701 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2702 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2703 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2704 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2705 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2706 | dcf24905 | blueswir1 | int l1;
|
2707 | dcf24905 | blueswir1 | |
2708 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2709 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2710 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2711 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2712 | cb63669a | pbrook | 0, l1);
|
2713 | 19f329ad | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2714 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2715 | dcf24905 | blueswir1 | gen_set_label(l1); |
2716 | 0f8a249a | blueswir1 | break;
|
2717 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2718 | dcf24905 | blueswir1 | int l1;
|
2719 | dcf24905 | blueswir1 | |
2720 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2721 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2722 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2723 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2724 | cb63669a | pbrook | 0, l1);
|
2725 | 19f329ad | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2726 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2727 | dcf24905 | blueswir1 | gen_set_label(l1); |
2728 | 0f8a249a | blueswir1 | break;
|
2729 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2730 | dcf24905 | blueswir1 | int l1;
|
2731 | dcf24905 | blueswir1 | |
2732 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2733 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2734 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2735 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2736 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2737 | cb63669a | pbrook | 0, l1);
|
2738 | 19f329ad | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2739 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2740 | dcf24905 | blueswir1 | gen_set_label(l1); |
2741 | 1f587329 | blueswir1 | break;
|
2742 | 0f8a249a | blueswir1 | } |
2743 | 0f8a249a | blueswir1 | #endif
|
2744 | 0f8a249a | blueswir1 | switch (xop) {
|
2745 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2746 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, fcc) \
|
2747 | 19f329ad | blueswir1 | { \ |
2748 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2749 | 19f329ad | blueswir1 | int l1; \
|
2750 | 19f329ad | blueswir1 | \ |
2751 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2752 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2753 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2754 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2755 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2756 | cb63669a | pbrook | 0, l1); \
|
2757 | 77f193da | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2758 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rs2))); \ |
2759 | 77f193da | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ |
2760 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rd))); \ |
2761 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2762 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2763 | 19f329ad | blueswir1 | } |
2764 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2765 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2766 | 0f8a249a | blueswir1 | break;
|
2767 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2768 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2769 | 0f8a249a | blueswir1 | break;
|
2770 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2771 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2772 | 19f329ad | blueswir1 | FMOVCC(Q, 0);
|
2773 | 1f587329 | blueswir1 | break;
|
2774 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2775 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2776 | 0f8a249a | blueswir1 | break;
|
2777 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2778 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2779 | 0f8a249a | blueswir1 | break;
|
2780 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2781 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2782 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2783 | 1f587329 | blueswir1 | break;
|
2784 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2785 | 19f329ad | blueswir1 | FMOVCC(F, 2);
|
2786 | 0f8a249a | blueswir1 | break;
|
2787 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2788 | 19f329ad | blueswir1 | FMOVCC(D, 2);
|
2789 | 0f8a249a | blueswir1 | break;
|
2790 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2791 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2792 | 19f329ad | blueswir1 | FMOVCC(Q, 2);
|
2793 | 1f587329 | blueswir1 | break;
|
2794 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2795 | 19f329ad | blueswir1 | FMOVCC(F, 3);
|
2796 | 0f8a249a | blueswir1 | break;
|
2797 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2798 | 19f329ad | blueswir1 | FMOVCC(D, 3);
|
2799 | 0f8a249a | blueswir1 | break;
|
2800 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2801 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2802 | 19f329ad | blueswir1 | FMOVCC(Q, 3);
|
2803 | 1f587329 | blueswir1 | break;
|
2804 | 19f329ad | blueswir1 | #undef FMOVCC
|
2805 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, icc) \
|
2806 | 19f329ad | blueswir1 | { \ |
2807 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2808 | 19f329ad | blueswir1 | int l1; \
|
2809 | 19f329ad | blueswir1 | \ |
2810 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2811 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2812 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2813 | 19f329ad | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2814 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2815 | cb63669a | pbrook | 0, l1); \
|
2816 | 77f193da | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2817 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rs2))); \ |
2818 | 77f193da | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ |
2819 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rd))); \ |
2820 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2821 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2822 | 19f329ad | blueswir1 | } |
2823 | 19f329ad | blueswir1 | |
2824 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2825 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2826 | 0f8a249a | blueswir1 | break;
|
2827 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2828 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2829 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2830 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2831 | 64a88d5d | blueswir1 | FMOVCC(Q, 0);
|
2832 | 1f587329 | blueswir1 | break;
|
2833 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2834 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2835 | 0f8a249a | blueswir1 | break;
|
2836 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2837 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2838 | 0f8a249a | blueswir1 | break;
|
2839 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2840 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2841 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2842 | 1f587329 | blueswir1 | break;
|
2843 | 19f329ad | blueswir1 | #undef FMOVCC
|
2844 | 1f587329 | blueswir1 | #endif
|
2845 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2846 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2847 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2848 | 7e8c2b6c | blueswir1 | gen_op_fcmps(rd & 3);
|
2849 | 0f8a249a | blueswir1 | break;
|
2850 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2851 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2852 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2853 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2854 | 0f8a249a | blueswir1 | break;
|
2855 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2856 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2857 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2858 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2859 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2860 | 1f587329 | blueswir1 | break;
|
2861 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2862 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2863 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2864 | 7e8c2b6c | blueswir1 | gen_op_fcmpes(rd & 3);
|
2865 | 0f8a249a | blueswir1 | break;
|
2866 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2867 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2868 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2869 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2870 | 0f8a249a | blueswir1 | break;
|
2871 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2872 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2873 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2874 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2875 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2876 | 1f587329 | blueswir1 | break;
|
2877 | 0f8a249a | blueswir1 | default:
|
2878 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2879 | 0f8a249a | blueswir1 | } |
2880 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2881 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2882 | e80cfcfc | bellard | |
2883 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2884 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2885 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2886 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2887 | 2ea815ca | blueswir1 | TCGv r_const; |
2888 | 2ea815ca | blueswir1 | |
2889 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2890 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
2891 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2892 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2893 | 0f8a249a | blueswir1 | } else { /* register */ |
2894 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2895 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2896 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2897 | 0f8a249a | blueswir1 | } |
2898 | 0f8a249a | blueswir1 | } else {
|
2899 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2900 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2901 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2902 | 6ae20372 | blueswir1 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
|
2903 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2904 | 0f8a249a | blueswir1 | } else { /* register */ |
2905 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2906 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2907 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2908 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2909 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2910 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2911 | 6f551262 | blueswir1 | } else
|
2912 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2913 | 0f8a249a | blueswir1 | } |
2914 | 0f8a249a | blueswir1 | } |
2915 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2916 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2917 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2918 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2919 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2920 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2921 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
2922 | 1a2fb1c0 | blueswir1 | } else {
|
2923 | 01b1fa6d | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
|
2924 | 1a2fb1c0 | blueswir1 | } |
2925 | 0f8a249a | blueswir1 | } else { /* register */ |
2926 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2927 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2928 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2929 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2930 | 1a2fb1c0 | blueswir1 | } else {
|
2931 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2932 | 1a2fb1c0 | blueswir1 | } |
2933 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2934 | 83469015 | bellard | } |
2935 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2936 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2937 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2938 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2939 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2940 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2941 | 6ae20372 | blueswir1 | tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
2942 | 1a2fb1c0 | blueswir1 | } else {
|
2943 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2944 | 6ae20372 | blueswir1 | tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
|
2945 | 1a2fb1c0 | blueswir1 | } |
2946 | 0f8a249a | blueswir1 | } else { /* register */ |
2947 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2948 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2949 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2950 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2951 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2952 | 1a2fb1c0 | blueswir1 | } else {
|
2953 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2954 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2955 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2956 | 1a2fb1c0 | blueswir1 | } |
2957 | 83469015 | bellard | } |
2958 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2959 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2960 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2961 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2962 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2963 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2964 | 6ae20372 | blueswir1 | tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
2965 | 1a2fb1c0 | blueswir1 | } else {
|
2966 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2967 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); |
2968 | 6ae20372 | blueswir1 | tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
|
2969 | 1a2fb1c0 | blueswir1 | } |
2970 | 0f8a249a | blueswir1 | } else { /* register */ |
2971 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2972 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2973 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2974 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2975 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2976 | 1a2fb1c0 | blueswir1 | } else {
|
2977 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2978 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2979 | 01b1fa6d | blueswir1 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); |
2980 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2981 | 1a2fb1c0 | blueswir1 | } |
2982 | 83469015 | bellard | } |
2983 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2984 | 83469015 | bellard | #endif
|
2985 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2986 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2987 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
2988 | cf495bcf | bellard | if (xop < 0x20) { |
2989 | cf495bcf | bellard | switch (xop & ~0x10) { |
2990 | cf495bcf | bellard | case 0x0: |
2991 | cf495bcf | bellard | if (xop & 0x10) |
2992 | 6ae20372 | blueswir1 | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
2993 | cf495bcf | bellard | else
|
2994 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2995 | cf495bcf | bellard | break;
|
2996 | cf495bcf | bellard | case 0x1: |
2997 | 6ae20372 | blueswir1 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
2998 | cf495bcf | bellard | if (xop & 0x10) |
2999 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3000 | cf495bcf | bellard | break;
|
3001 | cf495bcf | bellard | case 0x2: |
3002 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3003 | 0f8a249a | blueswir1 | if (xop & 0x10) |
3004 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3005 | 0f8a249a | blueswir1 | break;
|
3006 | cf495bcf | bellard | case 0x3: |
3007 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3008 | cf495bcf | bellard | if (xop & 0x10) |
3009 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3010 | cf495bcf | bellard | break;
|
3011 | cf495bcf | bellard | case 0x4: |
3012 | cf495bcf | bellard | if (xop & 0x10) |
3013 | 6ae20372 | blueswir1 | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3014 | cf495bcf | bellard | else
|
3015 | 6ae20372 | blueswir1 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
3016 | cf495bcf | bellard | break;
|
3017 | cf495bcf | bellard | case 0x5: |
3018 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3019 | 6ae20372 | blueswir1 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3020 | cf495bcf | bellard | if (xop & 0x10) |
3021 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3022 | cf495bcf | bellard | break;
|
3023 | cf495bcf | bellard | case 0x6: |
3024 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3025 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3026 | cf495bcf | bellard | if (xop & 0x10) |
3027 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3028 | cf495bcf | bellard | break;
|
3029 | cf495bcf | bellard | case 0x7: |
3030 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3031 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3032 | cf495bcf | bellard | if (xop & 0x10) |
3033 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3034 | cf495bcf | bellard | break;
|
3035 | cf495bcf | bellard | case 0x8: |
3036 | cf495bcf | bellard | if (xop & 0x10) |
3037 | 6ae20372 | blueswir1 | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
3038 | 38bc628b | blueswir1 | else {
|
3039 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3040 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3041 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3042 | 38bc628b | blueswir1 | } |
3043 | cf495bcf | bellard | break;
|
3044 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3045 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3046 | 6ae20372 | blueswir1 | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
3047 | ded3ab80 | pbrook | break;
|
3048 | ded3ab80 | pbrook | #endif
|
3049 | cf495bcf | bellard | case 0xa: |
3050 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3051 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3052 | cf495bcf | bellard | if (xop & 0x10) |
3053 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3054 | cf495bcf | bellard | break;
|
3055 | cf495bcf | bellard | case 0xb: |
3056 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3057 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3058 | cf495bcf | bellard | if (xop & 0x10) |
3059 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3060 | cf495bcf | bellard | break;
|
3061 | cf495bcf | bellard | case 0xc: |
3062 | cf495bcf | bellard | if (xop & 0x10) |
3063 | 6ae20372 | blueswir1 | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3064 | 38bc628b | blueswir1 | else {
|
3065 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3066 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3067 | 6ae20372 | blueswir1 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3068 | 38bc628b | blueswir1 | } |
3069 | cf495bcf | bellard | break;
|
3070 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3071 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3072 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3073 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3074 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3075 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3076 | ded3ab80 | pbrook | break;
|
3077 | ded3ab80 | pbrook | #endif
|
3078 | cf495bcf | bellard | case 0xe: |
3079 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3080 | 77f193da | blueswir1 | tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, |
3081 | 77f193da | blueswir1 | cpu_src2); |
3082 | cf495bcf | bellard | if (xop & 0x10) |
3083 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3084 | cf495bcf | bellard | break;
|
3085 | cf495bcf | bellard | case 0xf: |
3086 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3087 | 77f193da | blueswir1 | tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, |
3088 | 77f193da | blueswir1 | cpu_src2); |
3089 | cf495bcf | bellard | if (xop & 0x10) |
3090 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3091 | cf495bcf | bellard | break;
|
3092 | cf495bcf | bellard | default:
|
3093 | cf495bcf | bellard | goto illegal_insn;
|
3094 | cf495bcf | bellard | } |
3095 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3096 | cf495bcf | bellard | } else {
|
3097 | cf495bcf | bellard | switch (xop) {
|
3098 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3099 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3100 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3101 | 0f8a249a | blueswir1 | break;
|
3102 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3103 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3104 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3105 | 0f8a249a | blueswir1 | break;
|
3106 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3107 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3108 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3109 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3110 | 0f8a249a | blueswir1 | break;
|
3111 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3112 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3113 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3114 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3115 | 0f8a249a | blueswir1 | break;
|
3116 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3117 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3118 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3119 | cf495bcf | bellard | break;
|
3120 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3121 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3122 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3123 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3124 | e35298cd | blueswir1 | tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3125 | e35298cd | blueswir1 | } else { /* register */ |
3126 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3127 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3128 | e35298cd | blueswir1 | } |
3129 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3130 | cf495bcf | bellard | break;
|
3131 | 83469015 | bellard | case 0x26: /* srl */ |
3132 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3133 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3134 | e35298cd | blueswir1 | tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3135 | e35298cd | blueswir1 | } else { /* register */ |
3136 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3137 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3138 | e35298cd | blueswir1 | } |
3139 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3140 | cf495bcf | bellard | break;
|
3141 | 83469015 | bellard | case 0x27: /* sra */ |
3142 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3143 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3144 | e35298cd | blueswir1 | tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3145 | e35298cd | blueswir1 | } else { /* register */ |
3146 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3147 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3148 | e35298cd | blueswir1 | } |
3149 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3150 | cf495bcf | bellard | break;
|
3151 | 83469015 | bellard | #endif
|
3152 | cf495bcf | bellard | case 0x30: |
3153 | cf495bcf | bellard | { |
3154 | cf495bcf | bellard | switch(rd) {
|
3155 | 3475187d | bellard | case 0: /* wry */ |
3156 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3157 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3158 | 77f193da | blueswir1 | offsetof(CPUSPARCState, y)); |
3159 | cf495bcf | bellard | break;
|
3160 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3161 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3162 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3163 | 65fe7b09 | blueswir1 | on the microSPARC
|
3164 | 65fe7b09 | blueswir1 | II */
|
3165 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3166 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3167 | 65fe7b09 | blueswir1 | manual, nop on the
|
3168 | 65fe7b09 | blueswir1 | microSPARC II */
|
3169 | 65fe7b09 | blueswir1 | break;
|
3170 | 65fe7b09 | blueswir1 | #else
|
3171 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3172 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3173 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_wrccr, cpu_dst); |
3174 | 0f8a249a | blueswir1 | break;
|
3175 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3176 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3177 | 6ae20372 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
3178 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3179 | 77f193da | blueswir1 | offsetof(CPUSPARCState, asi)); |
3180 | 0f8a249a | blueswir1 | break;
|
3181 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3182 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3183 | 6ae20372 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
3184 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3185 | 77f193da | blueswir1 | offsetof(CPUSPARCState, fprs)); |
3186 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3187 | 3299908c | blueswir1 | gen_op_next_insn(); |
3188 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3189 | 3299908c | blueswir1 | dc->is_br = 1;
|
3190 | 0f8a249a | blueswir1 | break;
|
3191 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3192 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3193 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3194 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3195 | 3475187d | bellard | #endif
|
3196 | 0f8a249a | blueswir1 | break;
|
3197 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3198 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3199 | 725cb90b | bellard | goto jmp_insn;
|
3200 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3201 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3202 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gsr)); |
3203 | 0f8a249a | blueswir1 | break;
|
3204 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3205 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3206 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3207 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3208 | 83469015 | bellard | #endif
|
3209 | ccd4a219 | blueswir1 | { |
3210 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3211 | ccd4a219 | blueswir1 | |
3212 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, |
3213 | 6ae20372 | blueswir1 | cpu_src2); |
3214 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3215 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3216 | 77f193da | blueswir1 | tick_cmpr)); |
3217 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3218 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3219 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3220 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3221 | ece43b8d | blueswir1 | r_tickptr, cpu_tmp0); |
3222 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3223 | ccd4a219 | blueswir1 | } |
3224 | 0f8a249a | blueswir1 | break;
|
3225 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3226 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3227 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3228 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3229 | 83469015 | bellard | #endif
|
3230 | ccd4a219 | blueswir1 | { |
3231 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3232 | ccd4a219 | blueswir1 | |
3233 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3234 | 6ae20372 | blueswir1 | cpu_src2); |
3235 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3236 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3237 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3238 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3239 | 6ae20372 | blueswir1 | r_tickptr, cpu_dst); |
3240 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3241 | ccd4a219 | blueswir1 | } |
3242 | 0f8a249a | blueswir1 | break;
|
3243 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3244 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3245 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3246 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3247 | 3475187d | bellard | #endif
|
3248 | ccd4a219 | blueswir1 | { |
3249 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3250 | ccd4a219 | blueswir1 | |
3251 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, |
3252 | 6ae20372 | blueswir1 | cpu_src2); |
3253 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3254 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3255 | 77f193da | blueswir1 | stick_cmpr)); |
3256 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3257 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3258 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3259 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3260 | ece43b8d | blueswir1 | r_tickptr, cpu_tmp0); |
3261 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3262 | ccd4a219 | blueswir1 | } |
3263 | 0f8a249a | blueswir1 | break;
|
3264 | 83469015 | bellard | |
3265 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3266 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3267 | 77f193da | blueswir1 | Counter */
|
3268 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3269 | 0f8a249a | blueswir1 | case 0x14: /* Softint set */ |
3270 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear */ |
3271 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
3272 | 83469015 | bellard | #endif
|
3273 | 3475187d | bellard | default:
|
3274 | cf495bcf | bellard | goto illegal_insn;
|
3275 | cf495bcf | bellard | } |
3276 | cf495bcf | bellard | } |
3277 | cf495bcf | bellard | break;
|
3278 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3279 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3280 | e8af50a3 | bellard | { |
3281 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3282 | 0f8a249a | blueswir1 | goto priv_insn;
|
3283 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3284 | 0f8a249a | blueswir1 | switch (rd) {
|
3285 | 0f8a249a | blueswir1 | case 0: |
3286 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_saved); |
3287 | 0f8a249a | blueswir1 | break;
|
3288 | 0f8a249a | blueswir1 | case 1: |
3289 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restored); |
3290 | 0f8a249a | blueswir1 | break;
|
3291 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3292 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3293 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3294 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3295 | e9ebed4d | blueswir1 | // XXX
|
3296 | 0f8a249a | blueswir1 | default:
|
3297 | 3475187d | bellard | goto illegal_insn;
|
3298 | 3475187d | bellard | } |
3299 | 3475187d | bellard | #else
|
3300 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3301 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); |
3302 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3303 | 9e61bde5 | bellard | gen_op_next_insn(); |
3304 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3305 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3306 | 3475187d | bellard | #endif
|
3307 | e8af50a3 | bellard | } |
3308 | e8af50a3 | bellard | break;
|
3309 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3310 | e8af50a3 | bellard | { |
3311 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3312 | 0f8a249a | blueswir1 | goto priv_insn;
|
3313 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3314 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3315 | 0f8a249a | blueswir1 | switch (rd) {
|
3316 | 0f8a249a | blueswir1 | case 0: // tpc |
3317 | 375ee38b | blueswir1 | { |
3318 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3319 | 375ee38b | blueswir1 | |
3320 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3321 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3322 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3323 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3324 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3325 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3326 | 375ee38b | blueswir1 | } |
3327 | 0f8a249a | blueswir1 | break;
|
3328 | 0f8a249a | blueswir1 | case 1: // tnpc |
3329 | 375ee38b | blueswir1 | { |
3330 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3331 | 375ee38b | blueswir1 | |
3332 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3333 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3334 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3335 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3336 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3337 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3338 | 375ee38b | blueswir1 | } |
3339 | 0f8a249a | blueswir1 | break;
|
3340 | 0f8a249a | blueswir1 | case 2: // tstate |
3341 | 375ee38b | blueswir1 | { |
3342 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3343 | 375ee38b | blueswir1 | |
3344 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3345 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3346 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3347 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3348 | 77f193da | blueswir1 | offsetof(trap_state, |
3349 | 77f193da | blueswir1 | tstate)); |
3350 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3351 | 375ee38b | blueswir1 | } |
3352 | 0f8a249a | blueswir1 | break;
|
3353 | 0f8a249a | blueswir1 | case 3: // tt |
3354 | 375ee38b | blueswir1 | { |
3355 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3356 | 375ee38b | blueswir1 | |
3357 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3358 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3359 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3360 | ece43b8d | blueswir1 | tcg_gen_st_i32(cpu_tmp0, r_tsptr, |
3361 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3362 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3363 | 375ee38b | blueswir1 | } |
3364 | 0f8a249a | blueswir1 | break;
|
3365 | 0f8a249a | blueswir1 | case 4: // tick |
3366 | ccd4a219 | blueswir1 | { |
3367 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3368 | ccd4a219 | blueswir1 | |
3369 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3370 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3371 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3372 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3373 | ece43b8d | blueswir1 | r_tickptr, cpu_tmp0); |
3374 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3375 | ccd4a219 | blueswir1 | } |
3376 | 0f8a249a | blueswir1 | break;
|
3377 | 0f8a249a | blueswir1 | case 5: // tba |
3378 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3379 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tbr)); |
3380 | 0f8a249a | blueswir1 | break;
|
3381 | 0f8a249a | blueswir1 | case 6: // pstate |
3382 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3383 | ece43b8d | blueswir1 | tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0); |
3384 | ded3ab80 | pbrook | gen_op_next_insn(); |
3385 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3386 | ded3ab80 | pbrook | dc->is_br = 1;
|
3387 | 0f8a249a | blueswir1 | break;
|
3388 | 0f8a249a | blueswir1 | case 7: // tl |
3389 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3390 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3391 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3392 | 0f8a249a | blueswir1 | break;
|
3393 | 0f8a249a | blueswir1 | case 8: // pil |
3394 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3395 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3396 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3397 | 77f193da | blueswir1 | psrpil)); |
3398 | 0f8a249a | blueswir1 | break;
|
3399 | 0f8a249a | blueswir1 | case 9: // cwp |
3400 | ece43b8d | blueswir1 | tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0); |
3401 | 0f8a249a | blueswir1 | break;
|
3402 | 0f8a249a | blueswir1 | case 10: // cansave |
3403 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3404 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3405 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3406 | 77f193da | blueswir1 | cansave)); |
3407 | 0f8a249a | blueswir1 | break;
|
3408 | 0f8a249a | blueswir1 | case 11: // canrestore |
3409 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3410 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3411 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3412 | 77f193da | blueswir1 | canrestore)); |
3413 | 0f8a249a | blueswir1 | break;
|
3414 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3415 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3416 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3417 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3418 | 77f193da | blueswir1 | cleanwin)); |
3419 | 0f8a249a | blueswir1 | break;
|
3420 | 0f8a249a | blueswir1 | case 13: // otherwin |
3421 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3422 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3423 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3424 | 77f193da | blueswir1 | otherwin)); |
3425 | 0f8a249a | blueswir1 | break;
|
3426 | 0f8a249a | blueswir1 | case 14: // wstate |
3427 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3428 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3429 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3430 | 77f193da | blueswir1 | wstate)); |
3431 | 0f8a249a | blueswir1 | break;
|
3432 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3433 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3434 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3435 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3436 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3437 | e9ebed4d | blueswir1 | break;
|
3438 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3439 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3440 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3441 | e9ebed4d | blueswir1 | goto priv_insn;
|
3442 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3443 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3444 | 77f193da | blueswir1 | offsetof(CPUSPARCState, ssr)); |
3445 | e9ebed4d | blueswir1 | break;
|
3446 | 0f8a249a | blueswir1 | default:
|
3447 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3448 | 0f8a249a | blueswir1 | } |
3449 | 3475187d | bellard | #else
|
3450 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3451 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3452 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wim)); |
3453 | 3475187d | bellard | #endif
|
3454 | e8af50a3 | bellard | } |
3455 | e8af50a3 | bellard | break;
|
3456 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3457 | e8af50a3 | bellard | { |
3458 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3459 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3460 | 0f8a249a | blueswir1 | goto priv_insn;
|
3461 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3462 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3463 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tbr)); |
3464 | e9ebed4d | blueswir1 | #else
|
3465 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3466 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3467 | e9ebed4d | blueswir1 | goto priv_insn;
|
3468 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3469 | e9ebed4d | blueswir1 | switch (rd) {
|
3470 | e9ebed4d | blueswir1 | case 0: // hpstate |
3471 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3472 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3473 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3474 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3475 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3476 | e9ebed4d | blueswir1 | break;
|
3477 | e9ebed4d | blueswir1 | case 1: // htstate |
3478 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3479 | e9ebed4d | blueswir1 | break;
|
3480 | e9ebed4d | blueswir1 | case 3: // hintp |
3481 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3482 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3483 | 77f193da | blueswir1 | offsetof(CPUSPARCState, hintp)); |
3484 | e9ebed4d | blueswir1 | break;
|
3485 | e9ebed4d | blueswir1 | case 5: // htba |
3486 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3487 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3488 | 77f193da | blueswir1 | offsetof(CPUSPARCState, htba)); |
3489 | e9ebed4d | blueswir1 | break;
|
3490 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3491 | ccd4a219 | blueswir1 | { |
3492 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3493 | ccd4a219 | blueswir1 | |
3494 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
3495 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3496 | 77f193da | blueswir1 | hstick_cmpr)); |
3497 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3498 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3499 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3500 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3501 | ece43b8d | blueswir1 | r_tickptr, cpu_tmp0); |
3502 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3503 | ccd4a219 | blueswir1 | } |
3504 | e9ebed4d | blueswir1 | break;
|
3505 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3506 | e9ebed4d | blueswir1 | default:
|
3507 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3508 | e9ebed4d | blueswir1 | } |
3509 | e9ebed4d | blueswir1 | #endif
|
3510 | e8af50a3 | bellard | } |
3511 | e8af50a3 | bellard | break;
|
3512 | e8af50a3 | bellard | #endif
|
3513 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3514 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3515 | 0f8a249a | blueswir1 | { |
3516 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3517 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3518 | 748b9d8e | blueswir1 | TCGv r_cond; |
3519 | 00f219bf | blueswir1 | int l1;
|
3520 | 00f219bf | blueswir1 | |
3521 | 748b9d8e | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
3522 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3523 | 0f8a249a | blueswir1 | if (cc == 0) |
3524 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
3525 | 0f8a249a | blueswir1 | else if (cc == 2) |
3526 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
3527 | 0f8a249a | blueswir1 | else
|
3528 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3529 | 0f8a249a | blueswir1 | } else {
|
3530 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3531 | 0f8a249a | blueswir1 | } |
3532 | 00f219bf | blueswir1 | |
3533 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3534 | 00f219bf | blueswir1 | |
3535 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3536 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3537 | 2ea815ca | blueswir1 | TCGv r_const; |
3538 | 2ea815ca | blueswir1 | |
3539 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
3540 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
3541 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3542 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3543 | 00f219bf | blueswir1 | } else {
|
3544 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3545 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3546 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3547 | 00f219bf | blueswir1 | } |
3548 | 00f219bf | blueswir1 | gen_set_label(l1); |
3549 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3550 | 0f8a249a | blueswir1 | break;
|
3551 | 0f8a249a | blueswir1 | } |
3552 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3553 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3554 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3555 | 0f8a249a | blueswir1 | break;
|
3556 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3557 | 0f8a249a | blueswir1 | { |
3558 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3559 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_popc, cpu_dst, |
3560 | 6ae20372 | blueswir1 | cpu_src2); |
3561 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3562 | 0f8a249a | blueswir1 | } |
3563 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3564 | 0f8a249a | blueswir1 | { |
3565 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3566 | 00f219bf | blueswir1 | int l1;
|
3567 | 00f219bf | blueswir1 | |
3568 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3569 | 00f219bf | blueswir1 | |
3570 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3571 | 00f219bf | blueswir1 | |
3572 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3573 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3574 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3575 | 2ea815ca | blueswir1 | TCGv r_const; |
3576 | 2ea815ca | blueswir1 | |
3577 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
3578 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
3579 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3580 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3581 | 00f219bf | blueswir1 | } else {
|
3582 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3583 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3584 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3585 | 0f8a249a | blueswir1 | } |
3586 | 00f219bf | blueswir1 | gen_set_label(l1); |
3587 | 0f8a249a | blueswir1 | break;
|
3588 | 0f8a249a | blueswir1 | } |
3589 | 0f8a249a | blueswir1 | #endif
|
3590 | 0f8a249a | blueswir1 | default:
|
3591 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3592 | 0f8a249a | blueswir1 | } |
3593 | 0f8a249a | blueswir1 | } |
3594 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3595 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3596 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3597 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3598 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3599 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3600 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3601 | 3299908c | blueswir1 | |
3602 | 3299908c | blueswir1 | switch (opf) {
|
3603 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3604 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3605 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3606 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3607 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3608 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3609 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3610 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3611 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3612 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3613 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3614 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3615 | e9ebed4d | blueswir1 | // XXX
|
3616 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3617 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3618 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3619 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3620 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3621 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3622 | 6ae20372 | blueswir1 | cpu_src2); |
3623 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3624 | e9ebed4d | blueswir1 | break;
|
3625 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3626 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3627 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3628 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3629 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3630 | 6ae20372 | blueswir1 | cpu_src2); |
3631 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3632 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3633 | e9ebed4d | blueswir1 | break;
|
3634 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3635 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3636 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3637 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3638 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3639 | 6ae20372 | blueswir1 | cpu_src2); |
3640 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3641 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3642 | e9ebed4d | blueswir1 | break;
|
3643 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3644 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3645 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3646 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3647 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, |
3648 | 6ae20372 | blueswir1 | cpu_src2); |
3649 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3650 | 3299908c | blueswir1 | break;
|
3651 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3652 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3653 | 3299908c | blueswir1 | // XXX
|
3654 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3655 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3656 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3657 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3658 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3659 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple16); |
3660 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3661 | e9ebed4d | blueswir1 | break;
|
3662 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3663 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3664 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3665 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3666 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne16); |
3667 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3668 | 3299908c | blueswir1 | break;
|
3669 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3670 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3671 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3672 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3673 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple32); |
3674 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3675 | e9ebed4d | blueswir1 | break;
|
3676 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3677 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3678 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3679 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3680 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne32); |
3681 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3682 | e9ebed4d | blueswir1 | break;
|
3683 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3684 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3685 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3686 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3687 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt16); |
3688 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3689 | e9ebed4d | blueswir1 | break;
|
3690 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3691 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3692 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3693 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3694 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq16); |
3695 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3696 | e9ebed4d | blueswir1 | break;
|
3697 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3698 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3699 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3700 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3701 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt32); |
3702 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3703 | e9ebed4d | blueswir1 | break;
|
3704 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3705 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3706 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3707 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3708 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq32); |
3709 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3710 | e9ebed4d | blueswir1 | break;
|
3711 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3712 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3713 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3714 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3715 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16); |
3716 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3717 | e9ebed4d | blueswir1 | break;
|
3718 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3719 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3720 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3721 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3722 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16au); |
3723 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3724 | e9ebed4d | blueswir1 | break;
|
3725 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3726 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3727 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3728 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3729 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16al); |
3730 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3731 | e9ebed4d | blueswir1 | break;
|
3732 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3733 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3734 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3735 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3736 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8sux16); |
3737 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3738 | e9ebed4d | blueswir1 | break;
|
3739 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3740 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3741 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3742 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3743 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
3744 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3745 | e9ebed4d | blueswir1 | break;
|
3746 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3747 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3748 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3749 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3750 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
3751 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3752 | e9ebed4d | blueswir1 | break;
|
3753 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3754 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3755 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3756 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3757 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
3758 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3759 | e9ebed4d | blueswir1 | break;
|
3760 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3761 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3762 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3763 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3764 | e9ebed4d | blueswir1 | // XXX
|
3765 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3766 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3767 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3768 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3769 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3770 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faligndata); |
3771 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3772 | 3299908c | blueswir1 | break;
|
3773 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3774 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3775 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3776 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3777 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpmerge); |
3778 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3779 | e9ebed4d | blueswir1 | break;
|
3780 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3781 | e9ebed4d | blueswir1 | // XXX
|
3782 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3783 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3784 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3785 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3786 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3787 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fexpand); |
3788 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3789 | e9ebed4d | blueswir1 | break;
|
3790 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3791 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3792 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3793 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3794 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16); |
3795 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3796 | e9ebed4d | blueswir1 | break;
|
3797 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3798 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3799 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3800 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3801 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16s); |
3802 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3803 | e9ebed4d | blueswir1 | break;
|
3804 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3805 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3806 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3807 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3808 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3809 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3810 | e9ebed4d | blueswir1 | break;
|
3811 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3812 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3813 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3814 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3815 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32s); |
3816 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3817 | e9ebed4d | blueswir1 | break;
|
3818 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3819 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3820 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3821 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3822 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16); |
3823 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3824 | e9ebed4d | blueswir1 | break;
|
3825 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3826 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3827 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3828 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3829 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16s); |
3830 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3831 | e9ebed4d | blueswir1 | break;
|
3832 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3833 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3834 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3835 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3836 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3837 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3838 | e9ebed4d | blueswir1 | break;
|
3839 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3840 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3841 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3842 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3843 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub32s); |
3844 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3845 | e9ebed4d | blueswir1 | break;
|
3846 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3847 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3848 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
3849 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3850 | 3299908c | blueswir1 | break;
|
3851 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3852 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3853 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3854 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3855 | 3299908c | blueswir1 | break;
|
3856 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3857 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3858 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3859 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3860 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnor); |
3861 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3862 | e9ebed4d | blueswir1 | break;
|
3863 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3864 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3865 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3866 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3867 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnors); |
3868 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3869 | e9ebed4d | blueswir1 | break;
|
3870 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3871 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3872 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3873 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3874 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3875 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3876 | e9ebed4d | blueswir1 | break;
|
3877 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3878 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3879 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3880 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3881 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3882 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3883 | e9ebed4d | blueswir1 | break;
|
3884 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3885 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3886 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3887 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3888 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3889 | e9ebed4d | blueswir1 | break;
|
3890 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3891 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3892 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3893 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3894 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3895 | e9ebed4d | blueswir1 | break;
|
3896 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3897 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3898 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3899 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3900 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3901 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3902 | e9ebed4d | blueswir1 | break;
|
3903 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3904 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3905 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3906 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3907 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3908 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3909 | e9ebed4d | blueswir1 | break;
|
3910 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3911 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3912 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3913 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3914 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3915 | e9ebed4d | blueswir1 | break;
|
3916 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3917 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3918 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3919 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3920 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3921 | e9ebed4d | blueswir1 | break;
|
3922 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3923 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3924 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3925 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3926 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxor); |
3927 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3928 | e9ebed4d | blueswir1 | break;
|
3929 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3930 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3931 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3932 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3933 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxors); |
3934 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3935 | e9ebed4d | blueswir1 | break;
|
3936 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3937 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3938 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3939 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3940 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnand); |
3941 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3942 | e9ebed4d | blueswir1 | break;
|
3943 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3944 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3945 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3946 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3947 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnands); |
3948 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3949 | e9ebed4d | blueswir1 | break;
|
3950 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3951 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3952 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3953 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3954 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fand); |
3955 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3956 | e9ebed4d | blueswir1 | break;
|
3957 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3958 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3959 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3960 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3961 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fands); |
3962 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3963 | e9ebed4d | blueswir1 | break;
|
3964 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3965 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3966 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3967 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3968 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnor); |
3969 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3970 | e9ebed4d | blueswir1 | break;
|
3971 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3972 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3973 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3974 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3975 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnors); |
3976 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3977 | e9ebed4d | blueswir1 | break;
|
3978 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3979 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3980 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3981 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3982 | 3299908c | blueswir1 | break;
|
3983 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3984 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3985 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3986 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3987 | 3299908c | blueswir1 | break;
|
3988 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3989 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3990 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3991 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3992 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
3993 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3994 | e9ebed4d | blueswir1 | break;
|
3995 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3996 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3997 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3998 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3999 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
4000 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
4001 | e9ebed4d | blueswir1 | break;
|
4002 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
4003 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4004 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
4005 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4006 | 3299908c | blueswir1 | break;
|
4007 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
4008 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4009 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs2); |
4010 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
4011 | 3299908c | blueswir1 | break;
|
4012 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
4013 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4014 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4015 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4016 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
4017 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4018 | e9ebed4d | blueswir1 | break;
|
4019 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
4020 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4021 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
4022 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
4023 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
4024 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
4025 | e9ebed4d | blueswir1 | break;
|
4026 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
4027 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4028 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4029 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
4030 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_for); |
4031 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4032 | e9ebed4d | blueswir1 | break;
|
4033 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
4034 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4035 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
4036 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
4037 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fors); |
4038 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
4039 | e9ebed4d | blueswir1 | break;
|
4040 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
4041 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4042 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
4043 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4044 | 3299908c | blueswir1 | break;
|
4045 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
4046 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4047 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
4048 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
4049 | 3299908c | blueswir1 | break;
|
4050 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
4051 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
4052 | e9ebed4d | blueswir1 | // XXX
|
4053 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4054 | 3299908c | blueswir1 | default:
|
4055 | 3299908c | blueswir1 | goto illegal_insn;
|
4056 | 3299908c | blueswir1 | } |
4057 | 3299908c | blueswir1 | #else
|
4058 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4059 | 3299908c | blueswir1 | #endif
|
4060 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
4061 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
4062 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4063 | fcc72045 | blueswir1 | #else
|
4064 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4065 | fcc72045 | blueswir1 | #endif
|
4066 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4067 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4068 | 2ea815ca | blueswir1 | TCGv r_const; |
4069 | 2ea815ca | blueswir1 | |
4070 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4071 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4072 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4073 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4074 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
|
4075 | 0f8a249a | blueswir1 | } else { /* register */ |
4076 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4077 | 0f8a249a | blueswir1 | if (rs2) {
|
4078 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4079 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4080 | 6f551262 | blueswir1 | } else
|
4081 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4082 | 3475187d | bellard | } |
4083 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4084 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4085 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4086 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); |
4087 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4088 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4089 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4090 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4091 | 3475187d | bellard | #endif
|
4092 | 0f8a249a | blueswir1 | } else {
|
4093 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4094 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4095 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4096 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
|
4097 | 0f8a249a | blueswir1 | } else { /* register */ |
4098 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4099 | 0f8a249a | blueswir1 | if (rs2) {
|
4100 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4101 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4102 | 6f551262 | blueswir1 | } else
|
4103 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4104 | cf495bcf | bellard | } |
4105 | 0f8a249a | blueswir1 | switch (xop) {
|
4106 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4107 | 0f8a249a | blueswir1 | { |
4108 | 2ea815ca | blueswir1 | TCGv r_const; |
4109 | 2ea815ca | blueswir1 | |
4110 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
4111 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
4112 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4113 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4114 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4115 | 77f193da | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
4116 | 2ea815ca | blueswir1 | r_const); |
4117 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4118 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4119 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4120 | 0f8a249a | blueswir1 | } |
4121 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4122 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4123 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4124 | 0f8a249a | blueswir1 | { |
4125 | 2ea815ca | blueswir1 | TCGv r_const; |
4126 | 2ea815ca | blueswir1 | |
4127 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4128 | 0f8a249a | blueswir1 | goto priv_insn;
|
4129 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4130 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4131 | 77f193da | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
4132 | 2ea815ca | blueswir1 | r_const); |
4133 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4134 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4135 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4136 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_rett); |
4137 | 0f8a249a | blueswir1 | } |
4138 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4139 | 0f8a249a | blueswir1 | #endif
|
4140 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4141 | 64a88d5d | blueswir1 | if (!((dc)->features & CPU_FEATURE_FLUSH))
|
4142 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4143 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_flush, cpu_dst); |
4144 | 0f8a249a | blueswir1 | break;
|
4145 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4146 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4147 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_save); |
4148 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4149 | 0f8a249a | blueswir1 | break;
|
4150 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4151 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4152 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4153 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4154 | 0f8a249a | blueswir1 | break;
|
4155 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4156 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4157 | 0f8a249a | blueswir1 | { |
4158 | 0f8a249a | blueswir1 | switch (rd) {
|
4159 | 0f8a249a | blueswir1 | case 0: |
4160 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4161 | 0f8a249a | blueswir1 | goto priv_insn;
|
4162 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4163 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4164 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_done); |
4165 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4166 | 0f8a249a | blueswir1 | case 1: |
4167 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4168 | 0f8a249a | blueswir1 | goto priv_insn;
|
4169 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4170 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4171 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_retry); |
4172 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4173 | 0f8a249a | blueswir1 | default:
|
4174 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4175 | 0f8a249a | blueswir1 | } |
4176 | 0f8a249a | blueswir1 | } |
4177 | 0f8a249a | blueswir1 | break;
|
4178 | 0f8a249a | blueswir1 | #endif
|
4179 | 0f8a249a | blueswir1 | default:
|
4180 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4181 | 0f8a249a | blueswir1 | } |
4182 | cf495bcf | bellard | } |
4183 | 0f8a249a | blueswir1 | break;
|
4184 | 0f8a249a | blueswir1 | } |
4185 | 0f8a249a | blueswir1 | break;
|
4186 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4187 | 0f8a249a | blueswir1 | { |
4188 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4189 | 9322a4bf | blueswir1 | |
4190 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4191 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4192 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4193 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4194 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4195 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4196 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4197 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
|
4198 | 0f8a249a | blueswir1 | } else { /* register */ |
4199 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4200 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4201 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4202 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4203 | 6f551262 | blueswir1 | } else
|
4204 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4205 | 0f8a249a | blueswir1 | } |
4206 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4207 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4208 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4209 | 0f8a249a | blueswir1 | switch (xop) {
|
4210 | 1a2fb1c0 | blueswir1 | case 0x0: /* load unsigned word */ |
4211 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4212 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4213 | 0f8a249a | blueswir1 | break;
|
4214 | 0f8a249a | blueswir1 | case 0x1: /* load unsigned byte */ |
4215 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4216 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4217 | 0f8a249a | blueswir1 | break;
|
4218 | 0f8a249a | blueswir1 | case 0x2: /* load unsigned halfword */ |
4219 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4220 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4221 | 0f8a249a | blueswir1 | break;
|
4222 | 0f8a249a | blueswir1 | case 0x3: /* load double word */ |
4223 | 0f8a249a | blueswir1 | if (rd & 1) |
4224 | d4218d99 | blueswir1 | goto illegal_insn;
|
4225 | 1a2fb1c0 | blueswir1 | else {
|
4226 | 2ea815ca | blueswir1 | TCGv r_const; |
4227 | 2ea815ca | blueswir1 | |
4228 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4229 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4230 | d987963a | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4231 | 2ea815ca | blueswir1 | r_const); // XXX remove
|
4232 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4233 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4234 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4235 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4236 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4237 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4238 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4239 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4240 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4241 | 1a2fb1c0 | blueswir1 | } |
4242 | 0f8a249a | blueswir1 | break;
|
4243 | 0f8a249a | blueswir1 | case 0x9: /* load signed byte */ |
4244 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4245 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4246 | 0f8a249a | blueswir1 | break;
|
4247 | 0f8a249a | blueswir1 | case 0xa: /* load signed halfword */ |
4248 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4249 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4250 | 0f8a249a | blueswir1 | break;
|
4251 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4252 | 2ea815ca | blueswir1 | { |
4253 | 2ea815ca | blueswir1 | TCGv r_const; |
4254 | 2ea815ca | blueswir1 | |
4255 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4256 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4257 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4258 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4259 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4260 | 2ea815ca | blueswir1 | } |
4261 | 0f8a249a | blueswir1 | break;
|
4262 | 77f193da | blueswir1 | case 0x0f: /* swap register with memory. Also |
4263 | 77f193da | blueswir1 | atomically */
|
4264 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4265 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4266 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4267 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4268 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4269 | 6ae20372 | blueswir1 | tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); |
4270 | 0f8a249a | blueswir1 | break;
|
4271 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4272 | 0f8a249a | blueswir1 | case 0x10: /* load word alternate */ |
4273 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4274 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4275 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4276 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4277 | 0f8a249a | blueswir1 | goto priv_insn;
|
4278 | 6ea4a6c8 | blueswir1 | #endif
|
4279 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4280 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4281 | 0f8a249a | blueswir1 | break;
|
4282 | 0f8a249a | blueswir1 | case 0x11: /* load unsigned byte alternate */ |
4283 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4284 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4285 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4286 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4287 | 0f8a249a | blueswir1 | goto priv_insn;
|
4288 | 0f8a249a | blueswir1 | #endif
|
4289 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4290 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4291 | 0f8a249a | blueswir1 | break;
|
4292 | 0f8a249a | blueswir1 | case 0x12: /* load unsigned halfword alternate */ |
4293 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4294 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4295 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4296 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4297 | 0f8a249a | blueswir1 | goto priv_insn;
|
4298 | 6ea4a6c8 | blueswir1 | #endif
|
4299 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4300 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4301 | 0f8a249a | blueswir1 | break;
|
4302 | 0f8a249a | blueswir1 | case 0x13: /* load double word alternate */ |
4303 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4304 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4305 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4306 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4307 | 0f8a249a | blueswir1 | goto priv_insn;
|
4308 | 3475187d | bellard | #endif
|
4309 | 0f8a249a | blueswir1 | if (rd & 1) |
4310 | d4218d99 | blueswir1 | goto illegal_insn;
|
4311 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4312 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4313 | db166940 | blueswir1 | goto skip_move;
|
4314 | 0f8a249a | blueswir1 | case 0x19: /* load signed byte alternate */ |
4315 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4316 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4317 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4318 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4319 | 0f8a249a | blueswir1 | goto priv_insn;
|
4320 | 0f8a249a | blueswir1 | #endif
|
4321 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4322 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4323 | 0f8a249a | blueswir1 | break;
|
4324 | 0f8a249a | blueswir1 | case 0x1a: /* load signed halfword alternate */ |
4325 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4326 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4327 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4328 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4329 | 0f8a249a | blueswir1 | goto priv_insn;
|
4330 | 6ea4a6c8 | blueswir1 | #endif
|
4331 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4332 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4333 | 0f8a249a | blueswir1 | break;
|
4334 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4335 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4336 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4337 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4338 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4339 | 0f8a249a | blueswir1 | goto priv_insn;
|
4340 | 0f8a249a | blueswir1 | #endif
|
4341 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4342 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4343 | 0f8a249a | blueswir1 | break;
|
4344 | 77f193da | blueswir1 | case 0x1f: /* swap reg with alt. memory. Also |
4345 | 77f193da | blueswir1 | atomically */
|
4346 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4347 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4348 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4349 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4350 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4351 | 0f8a249a | blueswir1 | goto priv_insn;
|
4352 | 6ea4a6c8 | blueswir1 | #endif
|
4353 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4354 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4355 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4356 | 0f8a249a | blueswir1 | break;
|
4357 | 3475187d | bellard | |
4358 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4359 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4360 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4361 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4362 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4363 | 3475187d | bellard | #endif
|
4364 | 3475187d | bellard | #endif
|
4365 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4366 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4367 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4368 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4369 | 0f8a249a | blueswir1 | break;
|
4370 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4371 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4372 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4373 | 0f8a249a | blueswir1 | break;
|
4374 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4375 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4376 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4377 | 0f8a249a | blueswir1 | break;
|
4378 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4379 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4380 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4381 | 0f8a249a | blueswir1 | break;
|
4382 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4383 | 0f8a249a | blueswir1 | goto skip_move;
|
4384 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4385 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4386 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4387 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4388 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4389 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4390 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4391 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4392 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4393 | 0f8a249a | blueswir1 | goto skip_move;
|
4394 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4395 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4396 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4397 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4398 | 1f587329 | blueswir1 | goto skip_move;
|
4399 | 1f587329 | blueswir1 | #endif
|
4400 | 0f8a249a | blueswir1 | default:
|
4401 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4402 | 0f8a249a | blueswir1 | } |
4403 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4404 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4405 | 0f8a249a | blueswir1 | skip_move: ;
|
4406 | 3475187d | bellard | #endif
|
4407 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4408 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4409 | a80dde08 | bellard | goto jmp_insn;
|
4410 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4411 | 0f8a249a | blueswir1 | switch (xop) {
|
4412 | 0f8a249a | blueswir1 | case 0x20: /* load fpreg */ |
4413 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4414 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4415 | ce8536e2 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4416 | ce8536e2 | blueswir1 | offsetof(CPUState, fpr[rd])); |
4417 | 0f8a249a | blueswir1 | break;
|
4418 | 0f8a249a | blueswir1 | case 0x21: /* load fsr */ |
4419 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4420 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4421 | ce8536e2 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4422 | ce8536e2 | blueswir1 | offsetof(CPUState, ft0)); |
4423 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_ldfsr); |
4424 | 0f8a249a | blueswir1 | break;
|
4425 | 0f8a249a | blueswir1 | case 0x22: /* load quad fpreg */ |
4426 | 2ea815ca | blueswir1 | { |
4427 | 2ea815ca | blueswir1 | TCGv r_const; |
4428 | 2ea815ca | blueswir1 | |
4429 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4430 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4431 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); |
4432 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4433 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4434 | 2ea815ca | blueswir1 | } |
4435 | 1f587329 | blueswir1 | break;
|
4436 | 0f8a249a | blueswir1 | case 0x23: /* load double fpreg */ |
4437 | 2ea815ca | blueswir1 | { |
4438 | 2ea815ca | blueswir1 | TCGv r_const; |
4439 | 2ea815ca | blueswir1 | |
4440 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4441 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); |
4442 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4443 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4444 | 2ea815ca | blueswir1 | } |
4445 | 0f8a249a | blueswir1 | break;
|
4446 | 0f8a249a | blueswir1 | default:
|
4447 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4448 | 0f8a249a | blueswir1 | } |
4449 | 0f8a249a | blueswir1 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
4450 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4451 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4452 | 0f8a249a | blueswir1 | switch (xop) {
|
4453 | 1a2fb1c0 | blueswir1 | case 0x4: /* store word */ |
4454 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4455 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4456 | 0f8a249a | blueswir1 | break;
|
4457 | 1a2fb1c0 | blueswir1 | case 0x5: /* store byte */ |
4458 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4459 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4460 | 0f8a249a | blueswir1 | break;
|
4461 | 1a2fb1c0 | blueswir1 | case 0x6: /* store halfword */ |
4462 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4463 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4464 | 0f8a249a | blueswir1 | break;
|
4465 | 1a2fb1c0 | blueswir1 | case 0x7: /* store double word */ |
4466 | 0f8a249a | blueswir1 | if (rd & 1) |
4467 | d4218d99 | blueswir1 | goto illegal_insn;
|
4468 | 1a2fb1c0 | blueswir1 | else {
|
4469 | 2ea815ca | blueswir1 | TCGv r_low, r_const; |
4470 | 1a2fb1c0 | blueswir1 | |
4471 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4472 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4473 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4474 | c2bc0e38 | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4475 | 2ea815ca | blueswir1 | r_const); // XXX remove
|
4476 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4477 | 8d96d209 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_TL); |
4478 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd + 1, r_low);
|
4479 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
4480 | 1a2fb1c0 | blueswir1 | r_low); |
4481 | 2ea815ca | blueswir1 | tcg_temp_free(r_low); |
4482 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4483 | 7fa76c0b | blueswir1 | } |
4484 | 0f8a249a | blueswir1 | break;
|
4485 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4486 | 1a2fb1c0 | blueswir1 | case 0x14: /* store word alternate */ |
4487 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4488 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4489 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4490 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4491 | 0f8a249a | blueswir1 | goto priv_insn;
|
4492 | 3475187d | bellard | #endif
|
4493 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4494 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4495 | d39c0b99 | bellard | break;
|
4496 | 1a2fb1c0 | blueswir1 | case 0x15: /* store byte alternate */ |
4497 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4498 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4499 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4500 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4501 | 0f8a249a | blueswir1 | goto priv_insn;
|
4502 | 3475187d | bellard | #endif
|
4503 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4504 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4505 | d39c0b99 | bellard | break;
|
4506 | 1a2fb1c0 | blueswir1 | case 0x16: /* store halfword alternate */ |
4507 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4508 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4509 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4510 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4511 | 0f8a249a | blueswir1 | goto priv_insn;
|
4512 | 3475187d | bellard | #endif
|
4513 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4514 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4515 | d39c0b99 | bellard | break;
|
4516 | 1a2fb1c0 | blueswir1 | case 0x17: /* store double word alternate */ |
4517 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4518 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4519 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4520 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4521 | 0f8a249a | blueswir1 | goto priv_insn;
|
4522 | 3475187d | bellard | #endif
|
4523 | 0f8a249a | blueswir1 | if (rd & 1) |
4524 | d4218d99 | blueswir1 | goto illegal_insn;
|
4525 | 1a2fb1c0 | blueswir1 | else {
|
4526 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4527 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4528 | 1a2fb1c0 | blueswir1 | } |
4529 | d39c0b99 | bellard | break;
|
4530 | e80cfcfc | bellard | #endif
|
4531 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4532 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4533 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4534 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4535 | 0f8a249a | blueswir1 | break;
|
4536 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4537 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4538 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4539 | 0f8a249a | blueswir1 | break;
|
4540 | 3475187d | bellard | #endif
|
4541 | 0f8a249a | blueswir1 | default:
|
4542 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4543 | 0f8a249a | blueswir1 | } |
4544 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4545 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4546 | a80dde08 | bellard | goto jmp_insn;
|
4547 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4548 | 0f8a249a | blueswir1 | switch (xop) {
|
4549 | ce8536e2 | blueswir1 | case 0x24: /* store fpreg */ |
4550 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4551 | ce8536e2 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4552 | ce8536e2 | blueswir1 | offsetof(CPUState, fpr[rd])); |
4553 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4554 | 0f8a249a | blueswir1 | break;
|
4555 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4556 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4557 | bb5529bb | blueswir1 | tcg_gen_helper_0_0(helper_stfsr); |
4558 | ce8536e2 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4559 | ce8536e2 | blueswir1 | offsetof(CPUState, ft0)); |
4560 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4561 | 0f8a249a | blueswir1 | break;
|
4562 | 1f587329 | blueswir1 | case 0x26: |
4563 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4564 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4565 | 2ea815ca | blueswir1 | { |
4566 | 2ea815ca | blueswir1 | TCGv r_const; |
4567 | 2ea815ca | blueswir1 | |
4568 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4569 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4570 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4571 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); |
4572 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4573 | 2ea815ca | blueswir1 | } |
4574 | 1f587329 | blueswir1 | break;
|
4575 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4576 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4577 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4578 | 1f587329 | blueswir1 | goto illegal_insn;
|
4579 | 1f587329 | blueswir1 | #else
|
4580 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4581 | 0f8a249a | blueswir1 | goto priv_insn;
|
4582 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4583 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4584 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4585 | 0f8a249a | blueswir1 | #endif
|
4586 | 1f587329 | blueswir1 | #endif
|
4587 | 7fa76c0b | blueswir1 | case 0x27: /* store double fpreg */ |
4588 | 2ea815ca | blueswir1 | { |
4589 | 2ea815ca | blueswir1 | TCGv r_const; |
4590 | 2ea815ca | blueswir1 | |
4591 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4592 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4593 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); |
4594 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4595 | 2ea815ca | blueswir1 | } |
4596 | 0f8a249a | blueswir1 | break;
|
4597 | 0f8a249a | blueswir1 | default:
|
4598 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4599 | 0f8a249a | blueswir1 | } |
4600 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4601 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4602 | 0f8a249a | blueswir1 | switch (xop) {
|
4603 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4604 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4605 | 3391c818 | blueswir1 | gen_op_load_fpr_FT0(rd); |
4606 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4607 | 0f8a249a | blueswir1 | break;
|
4608 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4609 | 2ea815ca | blueswir1 | { |
4610 | 2ea815ca | blueswir1 | TCGv r_const; |
4611 | 2ea815ca | blueswir1 | |
4612 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4613 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4614 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4615 | 2ea815ca | blueswir1 | r_const); |
4616 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4617 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4618 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4619 | 2ea815ca | blueswir1 | } |
4620 | 1f587329 | blueswir1 | break;
|
4621 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4622 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4623 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4624 | 0f8a249a | blueswir1 | break;
|
4625 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4626 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4627 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4628 | 0f8a249a | blueswir1 | break;
|
4629 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4630 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4631 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4632 | 0f8a249a | blueswir1 | break;
|
4633 | a4d17f19 | blueswir1 | #else
|
4634 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4635 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4636 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4637 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4638 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4639 | 0f8a249a | blueswir1 | #endif
|
4640 | 0f8a249a | blueswir1 | default:
|
4641 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4642 | 0f8a249a | blueswir1 | } |
4643 | e8af50a3 | bellard | } |
4644 | 0f8a249a | blueswir1 | else
|
4645 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4646 | 0f8a249a | blueswir1 | } |
4647 | 0f8a249a | blueswir1 | break;
|
4648 | cf495bcf | bellard | } |
4649 | cf495bcf | bellard | /* default case for non jump instructions */
|
4650 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4651 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4652 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4653 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4654 | 72cbca10 | bellard | /* we can do a static jump */
|
4655 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4656 | 72cbca10 | bellard | dc->is_br = 1;
|
4657 | 72cbca10 | bellard | } else {
|
4658 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4659 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4660 | cf495bcf | bellard | } |
4661 | e80cfcfc | bellard | jmp_insn:
|
4662 | cf495bcf | bellard | return;
|
4663 | cf495bcf | bellard | illegal_insn:
|
4664 | 2ea815ca | blueswir1 | { |
4665 | 2ea815ca | blueswir1 | TCGv r_const; |
4666 | 2ea815ca | blueswir1 | |
4667 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4668 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4669 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4670 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4671 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4672 | 2ea815ca | blueswir1 | } |
4673 | e8af50a3 | bellard | return;
|
4674 | 64a88d5d | blueswir1 | unimp_flush:
|
4675 | 2ea815ca | blueswir1 | { |
4676 | 2ea815ca | blueswir1 | TCGv r_const; |
4677 | 2ea815ca | blueswir1 | |
4678 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4679 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4680 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4681 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4682 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4683 | 2ea815ca | blueswir1 | } |
4684 | 64a88d5d | blueswir1 | return;
|
4685 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4686 | e8af50a3 | bellard | priv_insn:
|
4687 | 2ea815ca | blueswir1 | { |
4688 | 2ea815ca | blueswir1 | TCGv r_const; |
4689 | 2ea815ca | blueswir1 | |
4690 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4691 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4692 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4693 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4694 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4695 | 2ea815ca | blueswir1 | } |
4696 | e80cfcfc | bellard | return;
|
4697 | 64a88d5d | blueswir1 | #endif
|
4698 | e80cfcfc | bellard | nfpu_insn:
|
4699 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4700 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4701 | e80cfcfc | bellard | dc->is_br = 1;
|
4702 | fcc72045 | blueswir1 | return;
|
4703 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4704 | 9143e598 | blueswir1 | nfq_insn:
|
4705 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4706 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4707 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4708 | 9143e598 | blueswir1 | return;
|
4709 | 9143e598 | blueswir1 | #endif
|
4710 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4711 | fcc72045 | blueswir1 | ncp_insn:
|
4712 | 2ea815ca | blueswir1 | { |
4713 | 2ea815ca | blueswir1 | TCGv r_const; |
4714 | 2ea815ca | blueswir1 | |
4715 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4716 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4717 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4718 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4719 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4720 | 2ea815ca | blueswir1 | } |
4721 | fcc72045 | blueswir1 | return;
|
4722 | fcc72045 | blueswir1 | #endif
|
4723 | 7a3f1944 | bellard | } |
4724 | 7a3f1944 | bellard | |
4725 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4726 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4727 | 7a3f1944 | bellard | { |
4728 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4729 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4730 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4731 | e8af50a3 | bellard | int j, lj = -1; |
4732 | 2e70f6ef | pbrook | int num_insns;
|
4733 | 2e70f6ef | pbrook | int max_insns;
|
4734 | cf495bcf | bellard | |
4735 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4736 | cf495bcf | bellard | dc->tb = tb; |
4737 | 72cbca10 | bellard | pc_start = tb->pc; |
4738 | cf495bcf | bellard | dc->pc = pc_start; |
4739 | e80cfcfc | bellard | last_pc = dc->pc; |
4740 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4741 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4742 | 64a88d5d | blueswir1 | dc->features = env->features; |
4743 | 64a88d5d | blueswir1 | if ((dc->features & CPU_FEATURE_FLOAT)) {
|
4744 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4745 | 64a88d5d | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4746 | 64a88d5d | blueswir1 | dc->features |= CPU_FEATURE_FLOAT128; |
4747 | 64a88d5d | blueswir1 | #endif
|
4748 | 64a88d5d | blueswir1 | } else
|
4749 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4750 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4751 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4752 | 2cade6a3 | blueswir1 | #endif
|
4753 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4754 | cf495bcf | bellard | |
4755 | 1a2fb1c0 | blueswir1 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
4756 | 8911f501 | blueswir1 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4757 | 8911f501 | blueswir1 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
4758 | d987963a | blueswir1 | |
4759 | d987963a | blueswir1 | cpu_dst = tcg_temp_local_new(TCG_TYPE_TL); |
4760 | d987963a | blueswir1 | |
4761 | d987963a | blueswir1 | // loads and stores
|
4762 | 3f0436fe | blueswir1 | cpu_val = tcg_temp_local_new(TCG_TYPE_TL); |
4763 | d987963a | blueswir1 | cpu_addr = tcg_temp_local_new(TCG_TYPE_TL); |
4764 | 1a2fb1c0 | blueswir1 | |
4765 | 2e70f6ef | pbrook | num_insns = 0;
|
4766 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4767 | 2e70f6ef | pbrook | if (max_insns == 0) |
4768 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4769 | 2e70f6ef | pbrook | gen_icount_start(); |
4770 | cf495bcf | bellard | do {
|
4771 | e8af50a3 | bellard | if (env->nb_breakpoints > 0) { |
4772 | e8af50a3 | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
4773 | e8af50a3 | bellard | if (env->breakpoints[j] == dc->pc) {
|
4774 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4775 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4776 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_debug); |
4777 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4778 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4779 | e80cfcfc | bellard | goto exit_gen_loop;
|
4780 | e8af50a3 | bellard | } |
4781 | e8af50a3 | bellard | } |
4782 | e8af50a3 | bellard | } |
4783 | e8af50a3 | bellard | if (spc) {
|
4784 | e8af50a3 | bellard | if (loglevel > 0) |
4785 | e8af50a3 | bellard | fprintf(logfile, "Search PC...\n");
|
4786 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4787 | e8af50a3 | bellard | if (lj < j) {
|
4788 | e8af50a3 | bellard | lj++; |
4789 | e8af50a3 | bellard | while (lj < j)
|
4790 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4791 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4792 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4793 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4794 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4795 | e8af50a3 | bellard | } |
4796 | e8af50a3 | bellard | } |
4797 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4798 | 2e70f6ef | pbrook | gen_io_start(); |
4799 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4800 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4801 | 2e70f6ef | pbrook | num_insns++; |
4802 | 0f8a249a | blueswir1 | |
4803 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4804 | 0f8a249a | blueswir1 | break;
|
4805 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4806 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4807 | 0f8a249a | blueswir1 | break;
|
4808 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4809 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4810 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4811 | d39c0b99 | bellard | break;
|
4812 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4813 | e80cfcfc | bellard | generate an exception */
|
4814 | e80cfcfc | bellard | if (env->singlestep_enabled) {
|
4815 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4816 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4817 | e80cfcfc | bellard | break;
|
4818 | e80cfcfc | bellard | } |
4819 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4820 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4821 | 2e70f6ef | pbrook | num_insns < max_insns); |
4822 | e80cfcfc | bellard | |
4823 | e80cfcfc | bellard | exit_gen_loop:
|
4824 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4825 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4826 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4827 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp64); |
4828 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp32); |
4829 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4830 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4831 | 2e70f6ef | pbrook | gen_io_end(); |
4832 | 72cbca10 | bellard | if (!dc->is_br) {
|
4833 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4834 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4835 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4836 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4837 | 72cbca10 | bellard | } else {
|
4838 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4839 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4840 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4841 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4842 | 72cbca10 | bellard | } |
4843 | 72cbca10 | bellard | } |
4844 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4845 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4846 | e8af50a3 | bellard | if (spc) {
|
4847 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4848 | e8af50a3 | bellard | lj++; |
4849 | e8af50a3 | bellard | while (lj <= j)
|
4850 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4851 | e8af50a3 | bellard | #if 0
|
4852 | e8af50a3 | bellard | if (loglevel > 0) {
|
4853 | e8af50a3 | bellard | page_dump(logfile);
|
4854 | e8af50a3 | bellard | }
|
4855 | e8af50a3 | bellard | #endif
|
4856 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4857 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4858 | e8af50a3 | bellard | } else {
|
4859 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4860 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4861 | e8af50a3 | bellard | } |
4862 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4863 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
4864 | 0f8a249a | blueswir1 | fprintf(logfile, "--------------\n");
|
4865 | 0f8a249a | blueswir1 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
4866 | 0f8a249a | blueswir1 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
4867 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
4868 | cf495bcf | bellard | } |
4869 | 7a3f1944 | bellard | #endif
|
4870 | 7a3f1944 | bellard | } |
4871 | 7a3f1944 | bellard | |
4872 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4873 | 7a3f1944 | bellard | { |
4874 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4875 | 7a3f1944 | bellard | } |
4876 | 7a3f1944 | bellard | |
4877 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4878 | 7a3f1944 | bellard | { |
4879 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4880 | 7a3f1944 | bellard | } |
4881 | 7a3f1944 | bellard | |
4882 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4883 | e80cfcfc | bellard | { |
4884 | f5069b26 | blueswir1 | unsigned int i; |
4885 | c48fcb47 | blueswir1 | static int inited; |
4886 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4887 | f5069b26 | blueswir1 | NULL, // g0 not used |
4888 | f5069b26 | blueswir1 | "g1",
|
4889 | f5069b26 | blueswir1 | "g2",
|
4890 | f5069b26 | blueswir1 | "g3",
|
4891 | f5069b26 | blueswir1 | "g4",
|
4892 | f5069b26 | blueswir1 | "g5",
|
4893 | f5069b26 | blueswir1 | "g6",
|
4894 | f5069b26 | blueswir1 | "g7",
|
4895 | f5069b26 | blueswir1 | }; |
4896 | aaed909a | bellard | |
4897 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4898 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4899 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4900 | 1a2fb1c0 | blueswir1 | |
4901 | 1a2fb1c0 | blueswir1 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
4902 | db4a4ea4 | blueswir1 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4903 | db4a4ea4 | blueswir1 | offsetof(CPUState, regwptr), |
4904 | db4a4ea4 | blueswir1 | "regwptr");
|
4905 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4906 | dc99a3f2 | blueswir1 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4907 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, xcc), |
4908 | dc99a3f2 | blueswir1 | "xcc");
|
4909 | 1a2fb1c0 | blueswir1 | #endif
|
4910 | 7c60cc4b | bellard | cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
4911 | 77f193da | blueswir1 | TCG_AREG0, offsetof(CPUState, cond), |
4912 | 77f193da | blueswir1 | "cond");
|
4913 | dc99a3f2 | blueswir1 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4914 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_src), |
4915 | dc99a3f2 | blueswir1 | "cc_src");
|
4916 | d9bdab86 | blueswir1 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4917 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4918 | d9bdab86 | blueswir1 | "cc_src2");
|
4919 | dc99a3f2 | blueswir1 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4920 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_dst), |
4921 | dc99a3f2 | blueswir1 | "cc_dst");
|
4922 | dc99a3f2 | blueswir1 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
4923 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, psr), |
4924 | dc99a3f2 | blueswir1 | "psr");
|
4925 | 87e92502 | blueswir1 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4926 | 87e92502 | blueswir1 | TCG_AREG0, offsetof(CPUState, fsr), |
4927 | 87e92502 | blueswir1 | "fsr");
|
4928 | 48d5c82b | blueswir1 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4929 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, pc), |
4930 | 48d5c82b | blueswir1 | "pc");
|
4931 | 48d5c82b | blueswir1 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, |
4932 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, npc), |
4933 | 48d5c82b | blueswir1 | "npc");
|
4934 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4935 | f5069b26 | blueswir1 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4936 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4937 | f5069b26 | blueswir1 | gregnames[i]); |
4938 | c9e03d8f | blueswir1 | /* register helpers */
|
4939 | c9e03d8f | blueswir1 | |
4940 | c9e03d8f | blueswir1 | #undef DEF_HELPER
|
4941 | c9e03d8f | blueswir1 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
4942 | c9e03d8f | blueswir1 | #include "helper.h" |
4943 | 1a2fb1c0 | blueswir1 | } |
4944 | 658138bc | bellard | } |
4945 | d2856f1a | aurel32 | |
4946 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
4947 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
4948 | d2856f1a | aurel32 | { |
4949 | d2856f1a | aurel32 | target_ulong npc; |
4950 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
4951 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
4952 | d2856f1a | aurel32 | if (npc == 1) { |
4953 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
4954 | d2856f1a | aurel32 | } else if (npc == 2) { |
4955 | d2856f1a | aurel32 | target_ulong t2 = (target_ulong)(unsigned long)puc; |
4956 | d2856f1a | aurel32 | /* jump PC: use T2 and the jump targets of the translation */
|
4957 | d2856f1a | aurel32 | if (t2)
|
4958 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
4959 | d2856f1a | aurel32 | else
|
4960 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
4961 | d2856f1a | aurel32 | } else {
|
4962 | d2856f1a | aurel32 | env->npc = npc; |
4963 | d2856f1a | aurel32 | } |
4964 | d2856f1a | aurel32 | } |