root / hw / eccmemctl.c @ 43f20196
History | View | Annotate | Download (10.9 kB)
1 | 7eb0c8e8 | blueswir1 | /*
|
---|---|---|---|
2 | 7eb0c8e8 | blueswir1 | * QEMU Sparc Sun4m ECC memory controller emulation
|
3 | 7eb0c8e8 | blueswir1 | *
|
4 | 7eb0c8e8 | blueswir1 | * Copyright (c) 2007 Robert Reif
|
5 | 7eb0c8e8 | blueswir1 | *
|
6 | 7eb0c8e8 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 7eb0c8e8 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
|
8 | 7eb0c8e8 | blueswir1 | * in the Software without restriction, including without limitation the rights
|
9 | 7eb0c8e8 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 7eb0c8e8 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
|
11 | 7eb0c8e8 | blueswir1 | * furnished to do so, subject to the following conditions:
|
12 | 7eb0c8e8 | blueswir1 | *
|
13 | 7eb0c8e8 | blueswir1 | * The above copyright notice and this permission notice shall be included in
|
14 | 7eb0c8e8 | blueswir1 | * all copies or substantial portions of the Software.
|
15 | 7eb0c8e8 | blueswir1 | *
|
16 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 7eb0c8e8 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 7eb0c8e8 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 7eb0c8e8 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 7eb0c8e8 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 7eb0c8e8 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE.
|
23 | 7eb0c8e8 | blueswir1 | */
|
24 | 49e66373 | Blue Swirl | |
25 | 49e66373 | Blue Swirl | #include "sysbus.h" |
26 | 97bf4851 | Blue Swirl | #include "trace.h" |
27 | 7eb0c8e8 | blueswir1 | |
28 | 7eb0c8e8 | blueswir1 | /* There are 3 versions of this chip used in SMP sun4m systems:
|
29 | 7eb0c8e8 | blueswir1 | * MCC (version 0, implementation 0) SS-600MP
|
30 | 7eb0c8e8 | blueswir1 | * EMC (version 0, implementation 1) SS-10
|
31 | 7eb0c8e8 | blueswir1 | * SMC (version 0, implementation 2) SS-10SX and SS-20
|
32 | 5ac574c4 | Blue Swirl | *
|
33 | 5ac574c4 | Blue Swirl | * Chipset docs:
|
34 | 5ac574c4 | Blue Swirl | * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
|
35 | 5ac574c4 | Blue Swirl | * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
|
36 | 7eb0c8e8 | blueswir1 | */
|
37 | 7eb0c8e8 | blueswir1 | |
38 | 0bb3602c | blueswir1 | #define ECC_MCC 0x00000000 |
39 | 0bb3602c | blueswir1 | #define ECC_EMC 0x10000000 |
40 | 0bb3602c | blueswir1 | #define ECC_SMC 0x20000000 |
41 | 0bb3602c | blueswir1 | |
42 | 8f2ad0a3 | blueswir1 | /* Register indexes */
|
43 | 8f2ad0a3 | blueswir1 | #define ECC_MER 0 /* Memory Enable Register */ |
44 | 8f2ad0a3 | blueswir1 | #define ECC_MDR 1 /* Memory Delay Register */ |
45 | 8f2ad0a3 | blueswir1 | #define ECC_MFSR 2 /* Memory Fault Status Register */ |
46 | 8f2ad0a3 | blueswir1 | #define ECC_VCR 3 /* Video Configuration Register */ |
47 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
48 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
49 | 8f2ad0a3 | blueswir1 | #define ECC_DR 6 /* Diagnostic Register */ |
50 | 8f2ad0a3 | blueswir1 | #define ECC_ECR0 7 /* Event Count Register 0 */ |
51 | 8f2ad0a3 | blueswir1 | #define ECC_ECR1 8 /* Event Count Register 1 */ |
52 | 7eb0c8e8 | blueswir1 | |
53 | 7eb0c8e8 | blueswir1 | /* ECC fault control register */
|
54 | dd53ded3 | blueswir1 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
55 | 77f193da | blueswir1 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
56 | 77f193da | blueswir1 | correctable errors */
|
57 | dd53ded3 | blueswir1 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
58 | dd53ded3 | blueswir1 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
59 | dd53ded3 | blueswir1 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
60 | dd53ded3 | blueswir1 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
61 | dd53ded3 | blueswir1 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
62 | dd53ded3 | blueswir1 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
63 | dd53ded3 | blueswir1 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
64 | dd53ded3 | blueswir1 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
65 | 0bb3602c | blueswir1 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
66 | dd53ded3 | blueswir1 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
67 | 0bb3602c | blueswir1 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
68 | 77f193da | blueswir1 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
69 | dd53ded3 | blueswir1 | #define ECC_MER_VER 0x0f000000 /* Version */ |
70 | dd53ded3 | blueswir1 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
71 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
72 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
73 | 0bb3602c | blueswir1 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
74 | dd53ded3 | blueswir1 | |
75 | dd53ded3 | blueswir1 | /* ECC memory delay register */
|
76 | dd53ded3 | blueswir1 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
77 | dd53ded3 | blueswir1 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
78 | dd53ded3 | blueswir1 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
79 | dd53ded3 | blueswir1 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
80 | dd53ded3 | blueswir1 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
81 | dd53ded3 | blueswir1 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
82 | dd53ded3 | blueswir1 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
83 | dd53ded3 | blueswir1 | #define ECC_MDR_MASK 0x7fffffff |
84 | 7eb0c8e8 | blueswir1 | |
85 | 7eb0c8e8 | blueswir1 | /* ECC fault status register */
|
86 | dd53ded3 | blueswir1 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
87 | dd53ded3 | blueswir1 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
88 | dd53ded3 | blueswir1 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
89 | dd53ded3 | blueswir1 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
90 | dd53ded3 | blueswir1 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
91 | dd53ded3 | blueswir1 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
92 | dd53ded3 | blueswir1 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
93 | dd53ded3 | blueswir1 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
94 | 7eb0c8e8 | blueswir1 | |
95 | 7eb0c8e8 | blueswir1 | /* ECC fault address register 0 */
|
96 | dd53ded3 | blueswir1 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
97 | dd53ded3 | blueswir1 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
98 | dd53ded3 | blueswir1 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
99 | dd53ded3 | blueswir1 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
100 | dd53ded3 | blueswir1 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
101 | dd53ded3 | blueswir1 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
102 | dd53ded3 | blueswir1 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
103 | dd53ded3 | blueswir1 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
104 | dd53ded3 | blueswir1 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
105 | 7eb0c8e8 | blueswir1 | |
106 | 7eb0c8e8 | blueswir1 | /* ECC diagnostic register */
|
107 | dd53ded3 | blueswir1 | #define ECC_DR_CBX 0x00000001 |
108 | dd53ded3 | blueswir1 | #define ECC_DR_CB0 0x00000002 |
109 | dd53ded3 | blueswir1 | #define ECC_DR_CB1 0x00000004 |
110 | dd53ded3 | blueswir1 | #define ECC_DR_CB2 0x00000008 |
111 | dd53ded3 | blueswir1 | #define ECC_DR_CB4 0x00000010 |
112 | dd53ded3 | blueswir1 | #define ECC_DR_CB8 0x00000020 |
113 | dd53ded3 | blueswir1 | #define ECC_DR_CB16 0x00000040 |
114 | dd53ded3 | blueswir1 | #define ECC_DR_CB32 0x00000080 |
115 | dd53ded3 | blueswir1 | #define ECC_DR_DMODE 0x00000c00 |
116 | dd53ded3 | blueswir1 | |
117 | dd53ded3 | blueswir1 | #define ECC_NREGS 9 |
118 | 7eb0c8e8 | blueswir1 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
119 | dd53ded3 | blueswir1 | |
120 | dd53ded3 | blueswir1 | #define ECC_DIAG_SIZE 4 |
121 | dd53ded3 | blueswir1 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
122 | 7eb0c8e8 | blueswir1 | |
123 | 7eb0c8e8 | blueswir1 | typedef struct ECCState { |
124 | 49e66373 | Blue Swirl | SysBusDevice busdev; |
125 | e42c20b4 | blueswir1 | qemu_irq irq; |
126 | 7eb0c8e8 | blueswir1 | uint32_t regs[ECC_NREGS]; |
127 | dd53ded3 | blueswir1 | uint8_t diag[ECC_DIAG_SIZE]; |
128 | 0bb3602c | blueswir1 | uint32_t version; |
129 | 7eb0c8e8 | blueswir1 | } ECCState; |
130 | 7eb0c8e8 | blueswir1 | |
131 | c227f099 | Anthony Liguori | static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
132 | 7eb0c8e8 | blueswir1 | { |
133 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
134 | 7eb0c8e8 | blueswir1 | |
135 | e64d7d59 | blueswir1 | switch (addr >> 2) { |
136 | dd53ded3 | blueswir1 | case ECC_MER:
|
137 | 0bb3602c | blueswir1 | if (s->version == ECC_MCC)
|
138 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
139 | 0bb3602c | blueswir1 | else if (s->version == ECC_EMC) |
140 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
141 | 0bb3602c | blueswir1 | else if (s->version == ECC_SMC) |
142 | 0bb3602c | blueswir1 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
143 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_mer(val); |
144 | 7eb0c8e8 | blueswir1 | break;
|
145 | dd53ded3 | blueswir1 | case ECC_MDR:
|
146 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
147 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_mdr(val); |
148 | 7eb0c8e8 | blueswir1 | break;
|
149 | dd53ded3 | blueswir1 | case ECC_MFSR:
|
150 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MFSR] = val; |
151 | 0bb3602c | blueswir1 | qemu_irq_lower(s->irq); |
152 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_mfsr(val); |
153 | 7eb0c8e8 | blueswir1 | break;
|
154 | dd53ded3 | blueswir1 | case ECC_VCR:
|
155 | 8f2ad0a3 | blueswir1 | s->regs[ECC_VCR] = val; |
156 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_vcr(val); |
157 | 7eb0c8e8 | blueswir1 | break;
|
158 | dd53ded3 | blueswir1 | case ECC_DR:
|
159 | 8f2ad0a3 | blueswir1 | s->regs[ECC_DR] = val; |
160 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_dr(val); |
161 | dd53ded3 | blueswir1 | break;
|
162 | dd53ded3 | blueswir1 | case ECC_ECR0:
|
163 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
164 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_ecr0(val); |
165 | 7eb0c8e8 | blueswir1 | break;
|
166 | dd53ded3 | blueswir1 | case ECC_ECR1:
|
167 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
168 | 97bf4851 | Blue Swirl | trace_ecc_mem_writel_ecr1(val); |
169 | 7eb0c8e8 | blueswir1 | break;
|
170 | 7eb0c8e8 | blueswir1 | } |
171 | 7eb0c8e8 | blueswir1 | } |
172 | 7eb0c8e8 | blueswir1 | |
173 | c227f099 | Anthony Liguori | static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
174 | 7eb0c8e8 | blueswir1 | { |
175 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
176 | 7eb0c8e8 | blueswir1 | uint32_t ret = 0;
|
177 | 7eb0c8e8 | blueswir1 | |
178 | e64d7d59 | blueswir1 | switch (addr >> 2) { |
179 | dd53ded3 | blueswir1 | case ECC_MER:
|
180 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MER]; |
181 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_mer(ret); |
182 | 7eb0c8e8 | blueswir1 | break;
|
183 | dd53ded3 | blueswir1 | case ECC_MDR:
|
184 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MDR]; |
185 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_mdr(ret); |
186 | 7eb0c8e8 | blueswir1 | break;
|
187 | dd53ded3 | blueswir1 | case ECC_MFSR:
|
188 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFSR]; |
189 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_mfsr(ret); |
190 | 7eb0c8e8 | blueswir1 | break;
|
191 | dd53ded3 | blueswir1 | case ECC_VCR:
|
192 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_VCR]; |
193 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_vcr(ret); |
194 | 7eb0c8e8 | blueswir1 | break;
|
195 | dd53ded3 | blueswir1 | case ECC_MFAR0:
|
196 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR0]; |
197 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_mfar0(ret); |
198 | 7eb0c8e8 | blueswir1 | break;
|
199 | dd53ded3 | blueswir1 | case ECC_MFAR1:
|
200 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR1]; |
201 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_mfar1(ret); |
202 | 7eb0c8e8 | blueswir1 | break;
|
203 | dd53ded3 | blueswir1 | case ECC_DR:
|
204 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_DR]; |
205 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_dr(ret); |
206 | 7eb0c8e8 | blueswir1 | break;
|
207 | dd53ded3 | blueswir1 | case ECC_ECR0:
|
208 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
209 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_ecr0(ret); |
210 | dd53ded3 | blueswir1 | break;
|
211 | dd53ded3 | blueswir1 | case ECC_ECR1:
|
212 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
213 | 97bf4851 | Blue Swirl | trace_ecc_mem_readl_ecr1(ret); |
214 | 7eb0c8e8 | blueswir1 | break;
|
215 | 7eb0c8e8 | blueswir1 | } |
216 | 7eb0c8e8 | blueswir1 | return ret;
|
217 | 7eb0c8e8 | blueswir1 | } |
218 | 7eb0c8e8 | blueswir1 | |
219 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const ecc_mem_read[3] = { |
220 | 7c560456 | blueswir1 | NULL,
|
221 | 7c560456 | blueswir1 | NULL,
|
222 | 7eb0c8e8 | blueswir1 | ecc_mem_readl, |
223 | 7eb0c8e8 | blueswir1 | }; |
224 | 7eb0c8e8 | blueswir1 | |
225 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const ecc_mem_write[3] = { |
226 | 7c560456 | blueswir1 | NULL,
|
227 | 7c560456 | blueswir1 | NULL,
|
228 | 7eb0c8e8 | blueswir1 | ecc_mem_writel, |
229 | 7eb0c8e8 | blueswir1 | }; |
230 | 7eb0c8e8 | blueswir1 | |
231 | c227f099 | Anthony Liguori | static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
232 | dd53ded3 | blueswir1 | uint32_t val) |
233 | dd53ded3 | blueswir1 | { |
234 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
235 | dd53ded3 | blueswir1 | |
236 | 97bf4851 | Blue Swirl | trace_ecc_diag_mem_writeb(addr, val); |
237 | dd53ded3 | blueswir1 | s->diag[addr & ECC_DIAG_MASK] = val; |
238 | dd53ded3 | blueswir1 | } |
239 | dd53ded3 | blueswir1 | |
240 | c227f099 | Anthony Liguori | static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
241 | dd53ded3 | blueswir1 | { |
242 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
243 | e64d7d59 | blueswir1 | uint32_t ret = s->diag[(int)addr];
|
244 | e64d7d59 | blueswir1 | |
245 | 97bf4851 | Blue Swirl | trace_ecc_diag_mem_readb(addr, ret); |
246 | dd53ded3 | blueswir1 | return ret;
|
247 | dd53ded3 | blueswir1 | } |
248 | dd53ded3 | blueswir1 | |
249 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = { |
250 | dd53ded3 | blueswir1 | ecc_diag_mem_readb, |
251 | dd53ded3 | blueswir1 | NULL,
|
252 | dd53ded3 | blueswir1 | NULL,
|
253 | dd53ded3 | blueswir1 | }; |
254 | dd53ded3 | blueswir1 | |
255 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = { |
256 | dd53ded3 | blueswir1 | ecc_diag_mem_writeb, |
257 | dd53ded3 | blueswir1 | NULL,
|
258 | dd53ded3 | blueswir1 | NULL,
|
259 | dd53ded3 | blueswir1 | }; |
260 | dd53ded3 | blueswir1 | |
261 | c21011a9 | Blue Swirl | static const VMStateDescription vmstate_ecc = { |
262 | c21011a9 | Blue Swirl | .name ="ECC",
|
263 | c21011a9 | Blue Swirl | .version_id = 3,
|
264 | c21011a9 | Blue Swirl | .minimum_version_id = 3,
|
265 | c21011a9 | Blue Swirl | .minimum_version_id_old = 3,
|
266 | c21011a9 | Blue Swirl | .fields = (VMStateField []) { |
267 | c21011a9 | Blue Swirl | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), |
268 | c21011a9 | Blue Swirl | VMSTATE_BUFFER(diag, ECCState), |
269 | c21011a9 | Blue Swirl | VMSTATE_UINT32(version, ECCState), |
270 | c21011a9 | Blue Swirl | VMSTATE_END_OF_LIST() |
271 | c21011a9 | Blue Swirl | } |
272 | c21011a9 | Blue Swirl | }; |
273 | 7eb0c8e8 | blueswir1 | |
274 | 0284dc54 | Blue Swirl | static void ecc_reset(DeviceState *d) |
275 | 7eb0c8e8 | blueswir1 | { |
276 | 0284dc54 | Blue Swirl | ECCState *s = container_of(d, ECCState, busdev.qdev); |
277 | 7eb0c8e8 | blueswir1 | |
278 | 0bb3602c | blueswir1 | if (s->version == ECC_MCC)
|
279 | 0bb3602c | blueswir1 | s->regs[ECC_MER] &= ECC_MER_REU; |
280 | 0bb3602c | blueswir1 | else
|
281 | 0bb3602c | blueswir1 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
282 | 0bb3602c | blueswir1 | ECC_MER_DCI); |
283 | dd53ded3 | blueswir1 | s->regs[ECC_MDR] = 0x20;
|
284 | dd53ded3 | blueswir1 | s->regs[ECC_MFSR] = 0;
|
285 | dd53ded3 | blueswir1 | s->regs[ECC_VCR] = 0;
|
286 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR0] = 0x07c00000;
|
287 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR1] = 0;
|
288 | dd53ded3 | blueswir1 | s->regs[ECC_DR] = 0;
|
289 | dd53ded3 | blueswir1 | s->regs[ECC_ECR0] = 0;
|
290 | dd53ded3 | blueswir1 | s->regs[ECC_ECR1] = 0;
|
291 | 7eb0c8e8 | blueswir1 | } |
292 | 7eb0c8e8 | blueswir1 | |
293 | 81a322d4 | Gerd Hoffmann | static int ecc_init1(SysBusDevice *dev) |
294 | 7eb0c8e8 | blueswir1 | { |
295 | 7eb0c8e8 | blueswir1 | int ecc_io_memory;
|
296 | 49e66373 | Blue Swirl | ECCState *s = FROM_SYSBUS(ECCState, dev); |
297 | 7eb0c8e8 | blueswir1 | |
298 | 49e66373 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
299 | 49e66373 | Blue Swirl | s->regs[0] = s->version;
|
300 | 2507c12a | Alexander Graf | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s, |
301 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
302 | 49e66373 | Blue Swirl | sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); |
303 | 49e66373 | Blue Swirl | |
304 | 49e66373 | Blue Swirl | if (s->version == ECC_MCC) { // SS-600MP only |
305 | 1eed09cb | Avi Kivity | ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, |
306 | 2507c12a | Alexander Graf | ecc_diag_mem_write, s, |
307 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
308 | 49e66373 | Blue Swirl | sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory); |
309 | dd53ded3 | blueswir1 | } |
310 | 0284dc54 | Blue Swirl | |
311 | 81a322d4 | Gerd Hoffmann | return 0; |
312 | 7eb0c8e8 | blueswir1 | } |
313 | 49e66373 | Blue Swirl | |
314 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo ecc_info = {
|
315 | ee6847d1 | Gerd Hoffmann | .init = ecc_init1, |
316 | ee6847d1 | Gerd Hoffmann | .qdev.name = "eccmemctl",
|
317 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(ECCState),
|
318 | 0284dc54 | Blue Swirl | .qdev.vmsd = &vmstate_ecc, |
319 | 0284dc54 | Blue Swirl | .qdev.reset = ecc_reset, |
320 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
321 | d210a1b4 | Gerd Hoffmann | DEFINE_PROP_HEX32("version", ECCState, version, -1), |
322 | d210a1b4 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
323 | ee6847d1 | Gerd Hoffmann | } |
324 | ee6847d1 | Gerd Hoffmann | }; |
325 | ee6847d1 | Gerd Hoffmann | |
326 | ee6847d1 | Gerd Hoffmann | |
327 | 49e66373 | Blue Swirl | static void ecc_register_devices(void) |
328 | 49e66373 | Blue Swirl | { |
329 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&ecc_info); |
330 | 49e66373 | Blue Swirl | } |
331 | 49e66373 | Blue Swirl | |
332 | 49e66373 | Blue Swirl | device_init(ecc_register_devices) |