root / hw / omap_dma.c @ 43f20196
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1 | b4e3104b | balrog | /*
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2 | b4e3104b | balrog | * TI OMAP DMA gigacell.
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3 | b4e3104b | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | b4e3104b | balrog | * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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6 | b4e3104b | balrog | *
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7 | b4e3104b | balrog | * This program is free software; you can redistribute it and/or
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8 | b4e3104b | balrog | * modify it under the terms of the GNU General Public License as
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9 | b4e3104b | balrog | * published by the Free Software Foundation; either version 2 of
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10 | b4e3104b | balrog | * the License, or (at your option) any later version.
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11 | b4e3104b | balrog | *
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12 | b4e3104b | balrog | * This program is distributed in the hope that it will be useful,
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13 | b4e3104b | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | b4e3104b | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | b4e3104b | balrog | * GNU General Public License for more details.
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16 | b4e3104b | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | b4e3104b | balrog | */
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20 | b4e3104b | balrog | #include "qemu-common.h" |
21 | b4e3104b | balrog | #include "qemu-timer.h" |
22 | b4e3104b | balrog | #include "omap.h" |
23 | b4e3104b | balrog | #include "irq.h" |
24 | afbb5194 | balrog | #include "soc_dma.h" |
25 | b4e3104b | balrog | |
26 | b4e3104b | balrog | struct omap_dma_channel_s {
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27 | b4e3104b | balrog | /* transfer data */
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28 | b4e3104b | balrog | int burst[2]; |
29 | b4e3104b | balrog | int pack[2]; |
30 | 827df9f3 | balrog | int endian[2]; |
31 | 827df9f3 | balrog | int endian_lock[2]; |
32 | 827df9f3 | balrog | int translate[2]; |
33 | b4e3104b | balrog | enum omap_dma_port port[2]; |
34 | c227f099 | Anthony Liguori | target_phys_addr_t addr[2];
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35 | c227f099 | Anthony Liguori | omap_dma_addressing_t mode[2];
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36 | 827df9f3 | balrog | uint32_t elements; |
37 | b4e3104b | balrog | uint16_t frames; |
38 | 827df9f3 | balrog | int32_t frame_index[2];
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39 | b4e3104b | balrog | int16_t element_index[2];
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40 | b4e3104b | balrog | int data_type;
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41 | b4e3104b | balrog | |
42 | b4e3104b | balrog | /* transfer type */
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43 | b4e3104b | balrog | int transparent_copy;
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44 | b4e3104b | balrog | int constant_fill;
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45 | b4e3104b | balrog | uint32_t color; |
46 | 827df9f3 | balrog | int prefetch;
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47 | b4e3104b | balrog | |
48 | b4e3104b | balrog | /* auto init and linked channel data */
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49 | b4e3104b | balrog | int end_prog;
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50 | b4e3104b | balrog | int repeat;
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51 | b4e3104b | balrog | int auto_init;
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52 | b4e3104b | balrog | int link_enabled;
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53 | b4e3104b | balrog | int link_next_ch;
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54 | b4e3104b | balrog | |
55 | b4e3104b | balrog | /* interruption data */
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56 | b4e3104b | balrog | int interrupts;
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57 | b4e3104b | balrog | int status;
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58 | 827df9f3 | balrog | int cstatus;
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59 | b4e3104b | balrog | |
60 | b4e3104b | balrog | /* state data */
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61 | b4e3104b | balrog | int active;
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62 | b4e3104b | balrog | int enable;
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63 | b4e3104b | balrog | int sync;
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64 | 827df9f3 | balrog | int src_sync;
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65 | b4e3104b | balrog | int pending_request;
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66 | b4e3104b | balrog | int waiting_end_prog;
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67 | b4e3104b | balrog | uint16_t cpc; |
68 | afbb5194 | balrog | int set_update;
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69 | b4e3104b | balrog | |
70 | b4e3104b | balrog | /* sync type */
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71 | b4e3104b | balrog | int fs;
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72 | b4e3104b | balrog | int bs;
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73 | b4e3104b | balrog | |
74 | b4e3104b | balrog | /* compatibility */
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75 | b4e3104b | balrog | int omap_3_1_compatible_disable;
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76 | b4e3104b | balrog | |
77 | b4e3104b | balrog | qemu_irq irq; |
78 | b4e3104b | balrog | struct omap_dma_channel_s *sibling;
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79 | b4e3104b | balrog | |
80 | b4e3104b | balrog | struct omap_dma_reg_set_s {
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81 | c227f099 | Anthony Liguori | target_phys_addr_t src, dest; |
82 | b4e3104b | balrog | int frame;
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83 | b4e3104b | balrog | int element;
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84 | 827df9f3 | balrog | int pck_element;
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85 | b4e3104b | balrog | int frame_delta[2]; |
86 | b4e3104b | balrog | int elem_delta[2]; |
87 | b4e3104b | balrog | int frames;
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88 | b4e3104b | balrog | int elements;
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89 | 827df9f3 | balrog | int pck_elements;
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90 | b4e3104b | balrog | } active_set; |
91 | b4e3104b | balrog | |
92 | afbb5194 | balrog | struct soc_dma_ch_s *dma;
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93 | afbb5194 | balrog | |
94 | b4e3104b | balrog | /* unused parameters */
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95 | 827df9f3 | balrog | int write_mode;
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96 | b4e3104b | balrog | int priority;
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97 | b4e3104b | balrog | int interleave_disabled;
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98 | b4e3104b | balrog | int type;
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99 | 827df9f3 | balrog | int suspend;
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100 | 827df9f3 | balrog | int buf_disable;
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101 | b4e3104b | balrog | }; |
102 | b4e3104b | balrog | |
103 | b4e3104b | balrog | struct omap_dma_s {
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104 | afbb5194 | balrog | struct soc_dma_s *dma;
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105 | afbb5194 | balrog | |
106 | b4e3104b | balrog | struct omap_mpu_state_s *mpu;
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107 | b4e3104b | balrog | omap_clk clk; |
108 | 827df9f3 | balrog | qemu_irq irq[4];
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109 | 827df9f3 | balrog | void (*intr_update)(struct omap_dma_s *s); |
110 | b4e3104b | balrog | enum omap_dma_model model;
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111 | b4e3104b | balrog | int omap_3_1_mapping_disabled;
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112 | b4e3104b | balrog | |
113 | 827df9f3 | balrog | uint32_t gcr; |
114 | 827df9f3 | balrog | uint32_t ocp; |
115 | 827df9f3 | balrog | uint32_t caps[5];
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116 | 827df9f3 | balrog | uint32_t irqen[4];
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117 | 827df9f3 | balrog | uint32_t irqstat[4];
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118 | b4e3104b | balrog | |
119 | b4e3104b | balrog | int chans;
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120 | 827df9f3 | balrog | struct omap_dma_channel_s ch[32]; |
121 | b4e3104b | balrog | struct omap_dma_lcd_channel_s lcd_ch;
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122 | b4e3104b | balrog | }; |
123 | b4e3104b | balrog | |
124 | b4e3104b | balrog | /* Interrupts */
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125 | b4e3104b | balrog | #define TIMEOUT_INTR (1 << 0) |
126 | b4e3104b | balrog | #define EVENT_DROP_INTR (1 << 1) |
127 | b4e3104b | balrog | #define HALF_FRAME_INTR (1 << 2) |
128 | b4e3104b | balrog | #define END_FRAME_INTR (1 << 3) |
129 | b4e3104b | balrog | #define LAST_FRAME_INTR (1 << 4) |
130 | b4e3104b | balrog | #define END_BLOCK_INTR (1 << 5) |
131 | b4e3104b | balrog | #define SYNC (1 << 6) |
132 | 827df9f3 | balrog | #define END_PKT_INTR (1 << 7) |
133 | 827df9f3 | balrog | #define TRANS_ERR_INTR (1 << 8) |
134 | 827df9f3 | balrog | #define MISALIGN_INTR (1 << 11) |
135 | b4e3104b | balrog | |
136 | 827df9f3 | balrog | static inline void omap_dma_interrupts_update(struct omap_dma_s *s) |
137 | b4e3104b | balrog | { |
138 | 827df9f3 | balrog | return s->intr_update(s);
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139 | b4e3104b | balrog | } |
140 | b4e3104b | balrog | |
141 | afbb5194 | balrog | static void omap_dma_channel_load(struct omap_dma_channel_s *ch) |
142 | b4e3104b | balrog | { |
143 | b4e3104b | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
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144 | afbb5194 | balrog | int i, normal;
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145 | b4e3104b | balrog | int omap_3_1 = !ch->omap_3_1_compatible_disable;
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146 | b4e3104b | balrog | |
147 | b4e3104b | balrog | /*
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148 | b4e3104b | balrog | * TODO: verify address ranges and alignment
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149 | b4e3104b | balrog | * TODO: port endianness
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150 | b4e3104b | balrog | */
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151 | b4e3104b | balrog | |
152 | b4e3104b | balrog | a->src = ch->addr[0];
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153 | b4e3104b | balrog | a->dest = ch->addr[1];
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154 | b4e3104b | balrog | a->frames = ch->frames; |
155 | b4e3104b | balrog | a->elements = ch->elements; |
156 | 827df9f3 | balrog | a->pck_elements = ch->frame_index[!ch->src_sync]; |
157 | b4e3104b | balrog | a->frame = 0;
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158 | b4e3104b | balrog | a->element = 0;
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159 | 827df9f3 | balrog | a->pck_element = 0;
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160 | b4e3104b | balrog | |
161 | b4e3104b | balrog | if (unlikely(!ch->elements || !ch->frames)) {
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162 | b4e3104b | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
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163 | b4e3104b | balrog | return;
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164 | b4e3104b | balrog | } |
165 | b4e3104b | balrog | |
166 | b4e3104b | balrog | for (i = 0; i < 2; i ++) |
167 | b4e3104b | balrog | switch (ch->mode[i]) {
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168 | b4e3104b | balrog | case constant:
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169 | b4e3104b | balrog | a->elem_delta[i] = 0;
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170 | b4e3104b | balrog | a->frame_delta[i] = 0;
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171 | b4e3104b | balrog | break;
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172 | b4e3104b | balrog | case post_incremented:
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173 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type; |
174 | b4e3104b | balrog | a->frame_delta[i] = 0;
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175 | b4e3104b | balrog | break;
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176 | b4e3104b | balrog | case single_index:
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177 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
178 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
179 | b4e3104b | balrog | a->frame_delta[i] = 0;
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180 | b4e3104b | balrog | break;
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181 | b4e3104b | balrog | case double_index:
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182 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
183 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
184 | b4e3104b | balrog | a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
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185 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i];
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186 | b4e3104b | balrog | break;
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187 | b4e3104b | balrog | default:
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188 | b4e3104b | balrog | break;
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189 | b4e3104b | balrog | } |
190 | afbb5194 | balrog | |
191 | afbb5194 | balrog | normal = !ch->transparent_copy && !ch->constant_fill && |
192 | afbb5194 | balrog | /* FIFO is big-endian so either (ch->endian[n] == 1) OR
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193 | afbb5194 | balrog | * (ch->endian_lock[n] == 1) mean no endianism conversion. */
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194 | afbb5194 | balrog | (ch->endian[0] | ch->endian_lock[0]) == |
195 | afbb5194 | balrog | (ch->endian[1] | ch->endian_lock[1]); |
196 | afbb5194 | balrog | for (i = 0; i < 2; i ++) { |
197 | afbb5194 | balrog | /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
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198 | afbb5194 | balrog | * limit min_elems in omap_dma_transfer_setup to the nearest frame
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199 | afbb5194 | balrog | * end. */
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200 | afbb5194 | balrog | if (!a->elem_delta[i] && normal &&
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201 | afbb5194 | balrog | (a->frames == 1 || !a->frame_delta[i]))
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202 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_const; |
203 | afbb5194 | balrog | else if (a->elem_delta[i] == ch->data_type && normal && |
204 | afbb5194 | balrog | (a->frames == 1 || !a->frame_delta[i]))
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205 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_linear; |
206 | afbb5194 | balrog | else
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207 | afbb5194 | balrog | ch->dma->type[i] = soc_dma_access_other; |
208 | afbb5194 | balrog | |
209 | afbb5194 | balrog | ch->dma->vaddr[i] = ch->addr[i]; |
210 | afbb5194 | balrog | } |
211 | afbb5194 | balrog | soc_dma_ch_update(ch->dma); |
212 | b4e3104b | balrog | } |
213 | b4e3104b | balrog | |
214 | b4e3104b | balrog | static void omap_dma_activate_channel(struct omap_dma_s *s, |
215 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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216 | b4e3104b | balrog | { |
217 | b4e3104b | balrog | if (!ch->active) {
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218 | afbb5194 | balrog | if (ch->set_update) {
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219 | afbb5194 | balrog | /* It's not clear when the active set is supposed to be
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220 | afbb5194 | balrog | * loaded from registers. We're already loading it when the
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221 | afbb5194 | balrog | * channel is enabled, and for some guests this is not enough
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222 | afbb5194 | balrog | * but that may be also because of a race condition (no
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223 | afbb5194 | balrog | * delays in qemu) in the guest code, which we're just
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224 | afbb5194 | balrog | * working around here. */
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225 | afbb5194 | balrog | omap_dma_channel_load(ch); |
226 | afbb5194 | balrog | ch->set_update = 0;
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227 | afbb5194 | balrog | } |
228 | afbb5194 | balrog | |
229 | b4e3104b | balrog | ch->active = 1;
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230 | afbb5194 | balrog | soc_dma_set_request(ch->dma, 1);
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231 | b4e3104b | balrog | if (ch->sync)
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232 | b4e3104b | balrog | ch->status |= SYNC; |
233 | b4e3104b | balrog | } |
234 | b4e3104b | balrog | } |
235 | b4e3104b | balrog | |
236 | b4e3104b | balrog | static void omap_dma_deactivate_channel(struct omap_dma_s *s, |
237 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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238 | b4e3104b | balrog | { |
239 | b4e3104b | balrog | /* Update cpc */
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240 | b4e3104b | balrog | ch->cpc = ch->active_set.dest & 0xffff;
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241 | b4e3104b | balrog | |
242 | 827df9f3 | balrog | if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
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243 | b4e3104b | balrog | /* Don't deactivate the channel */
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244 | b4e3104b | balrog | ch->pending_request = 0;
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245 | 827df9f3 | balrog | return;
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246 | b4e3104b | balrog | } |
247 | b4e3104b | balrog | |
248 | b4e3104b | balrog | /* Don't deactive the channel if it is synchronized and the DMA request is
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249 | b4e3104b | balrog | active */
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250 | afbb5194 | balrog | if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync))) |
251 | b4e3104b | balrog | return;
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252 | b4e3104b | balrog | |
253 | b4e3104b | balrog | if (ch->active) {
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254 | b4e3104b | balrog | ch->active = 0;
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255 | b4e3104b | balrog | ch->status &= ~SYNC; |
256 | afbb5194 | balrog | soc_dma_set_request(ch->dma, 0);
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257 | b4e3104b | balrog | } |
258 | b4e3104b | balrog | } |
259 | b4e3104b | balrog | |
260 | b4e3104b | balrog | static void omap_dma_enable_channel(struct omap_dma_s *s, |
261 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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262 | b4e3104b | balrog | { |
263 | b4e3104b | balrog | if (!ch->enable) {
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264 | b4e3104b | balrog | ch->enable = 1;
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265 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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266 | afbb5194 | balrog | omap_dma_channel_load(ch); |
267 | 827df9f3 | balrog | /* TODO: theoretically if ch->sync && ch->prefetch &&
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268 | afbb5194 | balrog | * !s->dma->drqbmp[ch->sync], we should also activate and fetch
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269 | afbb5194 | balrog | * from source and then stall until signalled. */
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270 | afbb5194 | balrog | if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync))) |
271 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
272 | b4e3104b | balrog | } |
273 | b4e3104b | balrog | } |
274 | b4e3104b | balrog | |
275 | b4e3104b | balrog | static void omap_dma_disable_channel(struct omap_dma_s *s, |
276 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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277 | b4e3104b | balrog | { |
278 | b4e3104b | balrog | if (ch->enable) {
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279 | b4e3104b | balrog | ch->enable = 0;
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280 | b4e3104b | balrog | /* Discard any pending request */
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281 | b4e3104b | balrog | ch->pending_request = 0;
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282 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
283 | b4e3104b | balrog | } |
284 | b4e3104b | balrog | } |
285 | b4e3104b | balrog | |
286 | b4e3104b | balrog | static void omap_dma_channel_end_prog(struct omap_dma_s *s, |
287 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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288 | b4e3104b | balrog | { |
289 | b4e3104b | balrog | if (ch->waiting_end_prog) {
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290 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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291 | b4e3104b | balrog | if (!ch->sync || ch->pending_request) {
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292 | b4e3104b | balrog | ch->pending_request = 0;
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293 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
294 | b4e3104b | balrog | } |
295 | b4e3104b | balrog | } |
296 | b4e3104b | balrog | } |
297 | b4e3104b | balrog | |
298 | 827df9f3 | balrog | static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) |
299 | 827df9f3 | balrog | { |
300 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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301 | 827df9f3 | balrog | |
302 | 827df9f3 | balrog | /* First three interrupts are shared between two channels each. */
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303 | 827df9f3 | balrog | if (ch[0].status | ch[6].status) |
304 | 827df9f3 | balrog | qemu_irq_raise(ch[0].irq);
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305 | 827df9f3 | balrog | if (ch[1].status | ch[7].status) |
306 | 827df9f3 | balrog | qemu_irq_raise(ch[1].irq);
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307 | 827df9f3 | balrog | if (ch[2].status | ch[8].status) |
308 | 827df9f3 | balrog | qemu_irq_raise(ch[2].irq);
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309 | 827df9f3 | balrog | if (ch[3].status) |
310 | 827df9f3 | balrog | qemu_irq_raise(ch[3].irq);
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311 | 827df9f3 | balrog | if (ch[4].status) |
312 | 827df9f3 | balrog | qemu_irq_raise(ch[4].irq);
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313 | 827df9f3 | balrog | if (ch[5].status) |
314 | 827df9f3 | balrog | qemu_irq_raise(ch[5].irq);
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315 | 827df9f3 | balrog | } |
316 | 827df9f3 | balrog | |
317 | 827df9f3 | balrog | static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) |
318 | 827df9f3 | balrog | { |
319 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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320 | 827df9f3 | balrog | int i;
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321 | 827df9f3 | balrog | |
322 | 827df9f3 | balrog | for (i = s->chans; i; ch ++, i --)
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323 | 827df9f3 | balrog | if (ch->status)
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324 | 827df9f3 | balrog | qemu_irq_raise(ch->irq); |
325 | 827df9f3 | balrog | } |
326 | 827df9f3 | balrog | |
327 | b4e3104b | balrog | static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
328 | b4e3104b | balrog | { |
329 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 0;
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330 | b4e3104b | balrog | s->chans = 9;
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331 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_1_update; |
332 | b4e3104b | balrog | } |
333 | b4e3104b | balrog | |
334 | b4e3104b | balrog | static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
335 | b4e3104b | balrog | { |
336 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 1;
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337 | b4e3104b | balrog | s->chans = 16;
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338 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_2_update; |
339 | b4e3104b | balrog | } |
340 | b4e3104b | balrog | |
341 | b4e3104b | balrog | static void omap_dma_process_request(struct omap_dma_s *s, int request) |
342 | b4e3104b | balrog | { |
343 | b4e3104b | balrog | int channel;
|
344 | b4e3104b | balrog | int drop_event = 0; |
345 | b4e3104b | balrog | struct omap_dma_channel_s *ch = s->ch;
|
346 | b4e3104b | balrog | |
347 | b4e3104b | balrog | for (channel = 0; channel < s->chans; channel ++, ch ++) { |
348 | b4e3104b | balrog | if (ch->enable && ch->sync == request) {
|
349 | b4e3104b | balrog | if (!ch->active)
|
350 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
351 | b4e3104b | balrog | else if (!ch->pending_request) |
352 | b4e3104b | balrog | ch->pending_request = 1;
|
353 | b4e3104b | balrog | else {
|
354 | b4e3104b | balrog | /* Request collision */
|
355 | b4e3104b | balrog | /* Second request received while processing other request */
|
356 | b4e3104b | balrog | ch->status |= EVENT_DROP_INTR; |
357 | b4e3104b | balrog | drop_event = 1;
|
358 | b4e3104b | balrog | } |
359 | b4e3104b | balrog | } |
360 | b4e3104b | balrog | } |
361 | b4e3104b | balrog | |
362 | b4e3104b | balrog | if (drop_event)
|
363 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
364 | b4e3104b | balrog | } |
365 | b4e3104b | balrog | |
366 | afbb5194 | balrog | static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) |
367 | b4e3104b | balrog | { |
368 | b4e3104b | balrog | uint8_t value[4];
|
369 | afbb5194 | balrog | struct omap_dma_channel_s *ch = dma->opaque;
|
370 | afbb5194 | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
|
371 | afbb5194 | balrog | int bytes = dma->bytes;
|
372 | afbb5194 | balrog | #ifdef MULTI_REQ
|
373 | afbb5194 | balrog | uint16_t status = ch->status; |
374 | afbb5194 | balrog | #endif
|
375 | b4e3104b | balrog | |
376 | afbb5194 | balrog | do {
|
377 | afbb5194 | balrog | /* Transfer a single element */
|
378 | afbb5194 | balrog | /* FIXME: check the endianness */
|
379 | afbb5194 | balrog | if (!ch->constant_fill)
|
380 | afbb5194 | balrog | cpu_physical_memory_read(a->src, value, ch->data_type); |
381 | afbb5194 | balrog | else
|
382 | afbb5194 | balrog | *(uint32_t *) value = ch->color; |
383 | afbb5194 | balrog | |
384 | afbb5194 | balrog | if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
|
385 | afbb5194 | balrog | cpu_physical_memory_write(a->dest, value, ch->data_type); |
386 | afbb5194 | balrog | |
387 | afbb5194 | balrog | a->src += a->elem_delta[0];
|
388 | afbb5194 | balrog | a->dest += a->elem_delta[1];
|
389 | afbb5194 | balrog | a->element ++; |
390 | afbb5194 | balrog | |
391 | afbb5194 | balrog | #ifndef MULTI_REQ
|
392 | afbb5194 | balrog | if (a->element == a->elements) {
|
393 | afbb5194 | balrog | /* End of Frame */
|
394 | afbb5194 | balrog | a->element = 0;
|
395 | afbb5194 | balrog | a->src += a->frame_delta[0];
|
396 | afbb5194 | balrog | a->dest += a->frame_delta[1];
|
397 | afbb5194 | balrog | a->frame ++; |
398 | afbb5194 | balrog | |
399 | afbb5194 | balrog | /* If the channel is async, update cpc */
|
400 | afbb5194 | balrog | if (!ch->sync)
|
401 | afbb5194 | balrog | ch->cpc = a->dest & 0xffff;
|
402 | afbb5194 | balrog | } |
403 | afbb5194 | balrog | } while ((bytes -= ch->data_type));
|
404 | afbb5194 | balrog | #else
|
405 | afbb5194 | balrog | /* If the channel is element synchronized, deactivate it */
|
406 | afbb5194 | balrog | if (ch->sync && !ch->fs && !ch->bs)
|
407 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
408 | afbb5194 | balrog | |
409 | afbb5194 | balrog | /* If it is the last frame, set the LAST_FRAME interrupt */
|
410 | afbb5194 | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
411 | afbb5194 | balrog | if (ch->interrupts & LAST_FRAME_INTR)
|
412 | afbb5194 | balrog | ch->status |= LAST_FRAME_INTR; |
413 | afbb5194 | balrog | |
414 | afbb5194 | balrog | /* If the half of the frame was reached, set the HALF_FRAME
|
415 | afbb5194 | balrog | interrupt */
|
416 | afbb5194 | balrog | if (a->element == (a->elements >> 1)) |
417 | afbb5194 | balrog | if (ch->interrupts & HALF_FRAME_INTR)
|
418 | afbb5194 | balrog | ch->status |= HALF_FRAME_INTR; |
419 | afbb5194 | balrog | |
420 | afbb5194 | balrog | if (ch->fs && ch->bs) {
|
421 | afbb5194 | balrog | a->pck_element ++; |
422 | afbb5194 | balrog | /* Check if a full packet has beed transferred. */
|
423 | afbb5194 | balrog | if (a->pck_element == a->pck_elements) {
|
424 | afbb5194 | balrog | a->pck_element = 0;
|
425 | afbb5194 | balrog | |
426 | afbb5194 | balrog | /* Set the END_PKT interrupt */
|
427 | afbb5194 | balrog | if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
|
428 | afbb5194 | balrog | ch->status |= END_PKT_INTR; |
429 | afbb5194 | balrog | |
430 | afbb5194 | balrog | /* If the channel is packet-synchronized, deactivate it */
|
431 | afbb5194 | balrog | if (ch->sync)
|
432 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch); |
433 | afbb5194 | balrog | } |
434 | b4e3104b | balrog | } |
435 | b4e3104b | balrog | |
436 | afbb5194 | balrog | if (a->element == a->elements) {
|
437 | afbb5194 | balrog | /* End of Frame */
|
438 | afbb5194 | balrog | a->element = 0;
|
439 | afbb5194 | balrog | a->src += a->frame_delta[0];
|
440 | afbb5194 | balrog | a->dest += a->frame_delta[1];
|
441 | afbb5194 | balrog | a->frame ++; |
442 | afbb5194 | balrog | |
443 | afbb5194 | balrog | /* If the channel is frame synchronized, deactivate it */
|
444 | afbb5194 | balrog | if (ch->sync && ch->fs && !ch->bs)
|
445 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
446 | b4e3104b | balrog | |
447 | afbb5194 | balrog | /* If the channel is async, update cpc */
|
448 | afbb5194 | balrog | if (!ch->sync)
|
449 | afbb5194 | balrog | ch->cpc = a->dest & 0xffff;
|
450 | afbb5194 | balrog | |
451 | afbb5194 | balrog | /* Set the END_FRAME interrupt */
|
452 | afbb5194 | balrog | if (ch->interrupts & END_FRAME_INTR)
|
453 | afbb5194 | balrog | ch->status |= END_FRAME_INTR; |
454 | afbb5194 | balrog | |
455 | afbb5194 | balrog | if (a->frame == a->frames) {
|
456 | afbb5194 | balrog | /* End of Block */
|
457 | afbb5194 | balrog | /* Disable the channel */
|
458 | afbb5194 | balrog | |
459 | afbb5194 | balrog | if (ch->omap_3_1_compatible_disable) {
|
460 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
461 | afbb5194 | balrog | if (ch->link_enabled)
|
462 | afbb5194 | balrog | omap_dma_enable_channel(s, |
463 | afbb5194 | balrog | &s->ch[ch->link_next_ch]); |
464 | afbb5194 | balrog | } else {
|
465 | afbb5194 | balrog | if (!ch->auto_init)
|
466 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
467 | afbb5194 | balrog | else if (ch->repeat || ch->end_prog) |
468 | afbb5194 | balrog | omap_dma_channel_load(ch); |
469 | afbb5194 | balrog | else {
|
470 | afbb5194 | balrog | ch->waiting_end_prog = 1;
|
471 | 827df9f3 | balrog | omap_dma_deactivate_channel(s, ch); |
472 | afbb5194 | balrog | } |
473 | 827df9f3 | balrog | } |
474 | afbb5194 | balrog | |
475 | afbb5194 | balrog | if (ch->interrupts & END_BLOCK_INTR)
|
476 | afbb5194 | balrog | ch->status |= END_BLOCK_INTR; |
477 | 827df9f3 | balrog | } |
478 | afbb5194 | balrog | } |
479 | afbb5194 | balrog | } while (status == ch->status && ch->active);
|
480 | 827df9f3 | balrog | |
481 | afbb5194 | balrog | omap_dma_interrupts_update(s); |
482 | afbb5194 | balrog | #endif
|
483 | afbb5194 | balrog | } |
484 | b4e3104b | balrog | |
485 | afbb5194 | balrog | enum {
|
486 | afbb5194 | balrog | omap_dma_intr_element_sync, |
487 | afbb5194 | balrog | omap_dma_intr_last_frame, |
488 | afbb5194 | balrog | omap_dma_intr_half_frame, |
489 | afbb5194 | balrog | omap_dma_intr_frame, |
490 | afbb5194 | balrog | omap_dma_intr_frame_sync, |
491 | afbb5194 | balrog | omap_dma_intr_packet, |
492 | afbb5194 | balrog | omap_dma_intr_packet_sync, |
493 | afbb5194 | balrog | omap_dma_intr_block, |
494 | afbb5194 | balrog | __omap_dma_intr_last, |
495 | afbb5194 | balrog | }; |
496 | b4e3104b | balrog | |
497 | afbb5194 | balrog | static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) |
498 | afbb5194 | balrog | { |
499 | afbb5194 | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
|
500 | afbb5194 | balrog | struct omap_dma_reg_set_s *a;
|
501 | afbb5194 | balrog | struct omap_dma_channel_s *ch = dma->opaque;
|
502 | afbb5194 | balrog | struct omap_dma_s *s = dma->dma->opaque;
|
503 | afbb5194 | balrog | int frames, min_elems, elements[__omap_dma_intr_last];
|
504 | b4e3104b | balrog | |
505 | afbb5194 | balrog | a = &ch->active_set; |
506 | b4e3104b | balrog | |
507 | afbb5194 | balrog | src_p = &s->mpu->port[ch->port[0]];
|
508 | afbb5194 | balrog | dest_p = &s->mpu->port[ch->port[1]];
|
509 | afbb5194 | balrog | if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
|
510 | afbb5194 | balrog | (!dest_p->addr_valid(s->mpu, a->dest))) { |
511 | afbb5194 | balrog | #if 0
|
512 | afbb5194 | balrog | /* Bus time-out */
|
513 | afbb5194 | balrog | if (ch->interrupts & TIMEOUT_INTR)
|
514 | afbb5194 | balrog | ch->status |= TIMEOUT_INTR;
|
515 | afbb5194 | balrog | omap_dma_deactivate_channel(s, ch);
|
516 | afbb5194 | balrog | continue;
|
517 | afbb5194 | balrog | #endif
|
518 | afbb5194 | balrog | printf("%s: Bus time-out in DMA%i operation\n",
|
519 | afbb5194 | balrog | __FUNCTION__, dma->num); |
520 | afbb5194 | balrog | } |
521 | b4e3104b | balrog | |
522 | afbb5194 | balrog | min_elems = INT_MAX; |
523 | afbb5194 | balrog | |
524 | afbb5194 | balrog | /* Check all the conditions that terminate the transfer starting
|
525 | afbb5194 | balrog | * with those that can occur the soonest. */
|
526 | afbb5194 | balrog | #define INTR_CHECK(cond, id, nelements) \
|
527 | afbb5194 | balrog | if (cond) { \
|
528 | afbb5194 | balrog | elements[id] = nelements; \ |
529 | afbb5194 | balrog | if (elements[id] < min_elems) \
|
530 | afbb5194 | balrog | min_elems = elements[id]; \ |
531 | afbb5194 | balrog | } else \
|
532 | afbb5194 | balrog | elements[id] = INT_MAX; |
533 | afbb5194 | balrog | |
534 | afbb5194 | balrog | /* Elements */
|
535 | afbb5194 | balrog | INTR_CHECK( |
536 | afbb5194 | balrog | ch->sync && !ch->fs && !ch->bs, |
537 | afbb5194 | balrog | omap_dma_intr_element_sync, |
538 | afbb5194 | balrog | 1)
|
539 | afbb5194 | balrog | |
540 | afbb5194 | balrog | /* Frames */
|
541 | afbb5194 | balrog | /* TODO: for transfers where entire frames can be read and written
|
542 | afbb5194 | balrog | * using memcpy() but a->frame_delta is non-zero, try to still do
|
543 | afbb5194 | balrog | * transfers using soc_dma but limit min_elems to a->elements - ...
|
544 | afbb5194 | balrog | * See also the TODO in omap_dma_channel_load. */
|
545 | afbb5194 | balrog | INTR_CHECK( |
546 | afbb5194 | balrog | (ch->interrupts & LAST_FRAME_INTR) && |
547 | afbb5194 | balrog | ((a->frame < a->frames - 1) || !a->element),
|
548 | afbb5194 | balrog | omap_dma_intr_last_frame, |
549 | afbb5194 | balrog | (a->frames - a->frame - 2) * a->elements +
|
550 | afbb5194 | balrog | (a->elements - a->element + 1))
|
551 | afbb5194 | balrog | INTR_CHECK( |
552 | afbb5194 | balrog | ch->interrupts & HALF_FRAME_INTR, |
553 | afbb5194 | balrog | omap_dma_intr_half_frame, |
554 | afbb5194 | balrog | (a->elements >> 1) +
|
555 | afbb5194 | balrog | (a->element >= (a->elements >> 1) ? a->elements : 0) - |
556 | afbb5194 | balrog | a->element) |
557 | afbb5194 | balrog | INTR_CHECK( |
558 | afbb5194 | balrog | ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), |
559 | afbb5194 | balrog | omap_dma_intr_frame, |
560 | afbb5194 | balrog | a->elements - a->element) |
561 | afbb5194 | balrog | INTR_CHECK( |
562 | afbb5194 | balrog | ch->sync && ch->fs && !ch->bs, |
563 | afbb5194 | balrog | omap_dma_intr_frame_sync, |
564 | afbb5194 | balrog | a->elements - a->element) |
565 | afbb5194 | balrog | |
566 | afbb5194 | balrog | /* Packets */
|
567 | afbb5194 | balrog | INTR_CHECK( |
568 | afbb5194 | balrog | ch->fs && ch->bs && |
569 | afbb5194 | balrog | (ch->interrupts & END_PKT_INTR) && !ch->src_sync, |
570 | afbb5194 | balrog | omap_dma_intr_packet, |
571 | afbb5194 | balrog | a->pck_elements - a->pck_element) |
572 | afbb5194 | balrog | INTR_CHECK( |
573 | afbb5194 | balrog | ch->fs && ch->bs && ch->sync, |
574 | afbb5194 | balrog | omap_dma_intr_packet_sync, |
575 | afbb5194 | balrog | a->pck_elements - a->pck_element) |
576 | afbb5194 | balrog | |
577 | afbb5194 | balrog | /* Blocks */
|
578 | afbb5194 | balrog | INTR_CHECK( |
579 | afbb5194 | balrog | 1,
|
580 | afbb5194 | balrog | omap_dma_intr_block, |
581 | afbb5194 | balrog | (a->frames - a->frame - 1) * a->elements +
|
582 | afbb5194 | balrog | (a->elements - a->element)) |
583 | afbb5194 | balrog | |
584 | afbb5194 | balrog | dma->bytes = min_elems * ch->data_type; |
585 | afbb5194 | balrog | |
586 | afbb5194 | balrog | /* Set appropriate interrupts and/or deactivate channels */
|
587 | afbb5194 | balrog | |
588 | afbb5194 | balrog | #ifdef MULTI_REQ
|
589 | afbb5194 | balrog | /* TODO: should all of this only be done if dma->update, and otherwise
|
590 | afbb5194 | balrog | * inside omap_dma_transfer_generic below - check what's faster. */
|
591 | 317b7e67 | Michael S. Tsirkin | if (dma->update) {
|
592 | afbb5194 | balrog | #endif
|
593 | b4e3104b | balrog | |
594 | 317b7e67 | Michael S. Tsirkin | /* If the channel is element synchronized, deactivate it */
|
595 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_element_sync])
|
596 | 317b7e67 | Michael S. Tsirkin | omap_dma_deactivate_channel(s, ch); |
597 | afbb5194 | balrog | |
598 | 317b7e67 | Michael S. Tsirkin | /* If it is the last frame, set the LAST_FRAME interrupt */
|
599 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_last_frame])
|
600 | 317b7e67 | Michael S. Tsirkin | ch->status |= LAST_FRAME_INTR; |
601 | afbb5194 | balrog | |
602 | 317b7e67 | Michael S. Tsirkin | /* If exactly half of the frame was reached, set the HALF_FRAME
|
603 | 317b7e67 | Michael S. Tsirkin | interrupt */
|
604 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_half_frame])
|
605 | 317b7e67 | Michael S. Tsirkin | ch->status |= HALF_FRAME_INTR; |
606 | afbb5194 | balrog | |
607 | 317b7e67 | Michael S. Tsirkin | /* If a full packet has been transferred, set the END_PKT interrupt */
|
608 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_packet])
|
609 | 317b7e67 | Michael S. Tsirkin | ch->status |= END_PKT_INTR; |
610 | afbb5194 | balrog | |
611 | 317b7e67 | Michael S. Tsirkin | /* If the channel is packet-synchronized, deactivate it */
|
612 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_packet_sync])
|
613 | 317b7e67 | Michael S. Tsirkin | omap_dma_deactivate_channel(s, ch); |
614 | afbb5194 | balrog | |
615 | 317b7e67 | Michael S. Tsirkin | /* If the channel is frame synchronized, deactivate it */
|
616 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_frame_sync])
|
617 | 317b7e67 | Michael S. Tsirkin | omap_dma_deactivate_channel(s, ch); |
618 | afbb5194 | balrog | |
619 | 317b7e67 | Michael S. Tsirkin | /* Set the END_FRAME interrupt */
|
620 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_frame])
|
621 | 317b7e67 | Michael S. Tsirkin | ch->status |= END_FRAME_INTR; |
622 | afbb5194 | balrog | |
623 | 317b7e67 | Michael S. Tsirkin | if (min_elems == elements[omap_dma_intr_block]) {
|
624 | 317b7e67 | Michael S. Tsirkin | /* End of Block */
|
625 | 317b7e67 | Michael S. Tsirkin | /* Disable the channel */
|
626 | afbb5194 | balrog | |
627 | 317b7e67 | Michael S. Tsirkin | if (ch->omap_3_1_compatible_disable) {
|
628 | afbb5194 | balrog | omap_dma_disable_channel(s, ch); |
629 | 317b7e67 | Michael S. Tsirkin | if (ch->link_enabled)
|
630 | 317b7e67 | Michael S. Tsirkin | omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); |
631 | 317b7e67 | Michael S. Tsirkin | } else {
|
632 | 317b7e67 | Michael S. Tsirkin | if (!ch->auto_init)
|
633 | 317b7e67 | Michael S. Tsirkin | omap_dma_disable_channel(s, ch); |
634 | 317b7e67 | Michael S. Tsirkin | else if (ch->repeat || ch->end_prog) |
635 | 317b7e67 | Michael S. Tsirkin | omap_dma_channel_load(ch); |
636 | 317b7e67 | Michael S. Tsirkin | else {
|
637 | 317b7e67 | Michael S. Tsirkin | ch->waiting_end_prog = 1;
|
638 | 317b7e67 | Michael S. Tsirkin | omap_dma_deactivate_channel(s, ch); |
639 | 317b7e67 | Michael S. Tsirkin | } |
640 | b4e3104b | balrog | } |
641 | afbb5194 | balrog | |
642 | 317b7e67 | Michael S. Tsirkin | if (ch->interrupts & END_BLOCK_INTR)
|
643 | 317b7e67 | Michael S. Tsirkin | ch->status |= END_BLOCK_INTR; |
644 | 317b7e67 | Michael S. Tsirkin | } |
645 | afbb5194 | balrog | |
646 | 317b7e67 | Michael S. Tsirkin | /* Update packet number */
|
647 | 317b7e67 | Michael S. Tsirkin | if (ch->fs && ch->bs) {
|
648 | 317b7e67 | Michael S. Tsirkin | a->pck_element += min_elems; |
649 | 317b7e67 | Michael S. Tsirkin | a->pck_element %= a->pck_elements; |
650 | 317b7e67 | Michael S. Tsirkin | } |
651 | afbb5194 | balrog | |
652 | 317b7e67 | Michael S. Tsirkin | /* TODO: check if we really need to update anything here or perhaps we
|
653 | 317b7e67 | Michael S. Tsirkin | * can skip part of this. */
|
654 | afbb5194 | balrog | #ifndef MULTI_REQ
|
655 | 317b7e67 | Michael S. Tsirkin | if (dma->update) {
|
656 | afbb5194 | balrog | #endif
|
657 | 317b7e67 | Michael S. Tsirkin | a->element += min_elems; |
658 | afbb5194 | balrog | |
659 | 317b7e67 | Michael S. Tsirkin | frames = a->element / a->elements; |
660 | 317b7e67 | Michael S. Tsirkin | a->element = a->element % a->elements; |
661 | 317b7e67 | Michael S. Tsirkin | a->frame += frames; |
662 | 317b7e67 | Michael S. Tsirkin | a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; |
663 | 317b7e67 | Michael S. Tsirkin | a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; |
664 | afbb5194 | balrog | |
665 | 317b7e67 | Michael S. Tsirkin | /* If the channel is async, update cpc */
|
666 | 317b7e67 | Michael S. Tsirkin | if (!ch->sync && frames)
|
667 | 317b7e67 | Michael S. Tsirkin | ch->cpc = a->dest & 0xffff;
|
668 | d4066479 | balrog | |
669 | 317b7e67 | Michael S. Tsirkin | /* TODO: if the destination port is IMIF or EMIFF, set the dirty
|
670 | 317b7e67 | Michael S. Tsirkin | * bits on it. */
|
671 | f90554ad | Michael S. Tsirkin | #ifndef MULTI_REQ
|
672 | 317b7e67 | Michael S. Tsirkin | } |
673 | 317b7e67 | Michael S. Tsirkin | #else
|
674 | b4e3104b | balrog | } |
675 | f90554ad | Michael S. Tsirkin | #endif
|
676 | b4e3104b | balrog | |
677 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
678 | b4e3104b | balrog | } |
679 | b4e3104b | balrog | |
680 | afbb5194 | balrog | void omap_dma_reset(struct soc_dma_s *dma) |
681 | b4e3104b | balrog | { |
682 | b4e3104b | balrog | int i;
|
683 | afbb5194 | balrog | struct omap_dma_s *s = dma->opaque;
|
684 | b4e3104b | balrog | |
685 | afbb5194 | balrog | soc_dma_reset(s->dma); |
686 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
687 | 827df9f3 | balrog | s->gcr = 0x0004;
|
688 | 827df9f3 | balrog | else
|
689 | 827df9f3 | balrog | s->gcr = 0x00010010;
|
690 | 827df9f3 | balrog | s->ocp = 0x00000000;
|
691 | 827df9f3 | balrog | memset(&s->irqstat, 0, sizeof(s->irqstat)); |
692 | 827df9f3 | balrog | memset(&s->irqen, 0, sizeof(s->irqen)); |
693 | b4e3104b | balrog | s->lcd_ch.src = emiff; |
694 | b4e3104b | balrog | s->lcd_ch.condition = 0;
|
695 | b4e3104b | balrog | s->lcd_ch.interrupts = 0;
|
696 | b4e3104b | balrog | s->lcd_ch.dual = 0;
|
697 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
698 | 827df9f3 | balrog | omap_dma_enable_3_1_mapping(s); |
699 | b4e3104b | balrog | for (i = 0; i < s->chans; i ++) { |
700 | 827df9f3 | balrog | s->ch[i].suspend = 0;
|
701 | 827df9f3 | balrog | s->ch[i].prefetch = 0;
|
702 | 827df9f3 | balrog | s->ch[i].buf_disable = 0;
|
703 | 827df9f3 | balrog | s->ch[i].src_sync = 0;
|
704 | b4e3104b | balrog | memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
705 | b4e3104b | balrog | memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
706 | b4e3104b | balrog | memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
707 | b4e3104b | balrog | memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
708 | b4e3104b | balrog | memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
709 | 827df9f3 | balrog | memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); |
710 | 827df9f3 | balrog | memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); |
711 | 827df9f3 | balrog | memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); |
712 | 827df9f3 | balrog | s->ch[i].write_mode = 0;
|
713 | 827df9f3 | balrog | s->ch[i].data_type = 0;
|
714 | 827df9f3 | balrog | s->ch[i].transparent_copy = 0;
|
715 | 827df9f3 | balrog | s->ch[i].constant_fill = 0;
|
716 | 827df9f3 | balrog | s->ch[i].color = 0x00000000;
|
717 | 827df9f3 | balrog | s->ch[i].end_prog = 0;
|
718 | 827df9f3 | balrog | s->ch[i].repeat = 0;
|
719 | 827df9f3 | balrog | s->ch[i].auto_init = 0;
|
720 | 827df9f3 | balrog | s->ch[i].link_enabled = 0;
|
721 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
722 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0003;
|
723 | 827df9f3 | balrog | else
|
724 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0000;
|
725 | 827df9f3 | balrog | s->ch[i].status = 0;
|
726 | 827df9f3 | balrog | s->ch[i].cstatus = 0;
|
727 | 827df9f3 | balrog | s->ch[i].active = 0;
|
728 | 827df9f3 | balrog | s->ch[i].enable = 0;
|
729 | 827df9f3 | balrog | s->ch[i].sync = 0;
|
730 | 827df9f3 | balrog | s->ch[i].pending_request = 0;
|
731 | 827df9f3 | balrog | s->ch[i].waiting_end_prog = 0;
|
732 | 827df9f3 | balrog | s->ch[i].cpc = 0x0000;
|
733 | 827df9f3 | balrog | s->ch[i].fs = 0;
|
734 | 827df9f3 | balrog | s->ch[i].bs = 0;
|
735 | 827df9f3 | balrog | s->ch[i].omap_3_1_compatible_disable = 0;
|
736 | b4e3104b | balrog | memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
737 | 827df9f3 | balrog | s->ch[i].priority = 0;
|
738 | 827df9f3 | balrog | s->ch[i].interleave_disabled = 0;
|
739 | 827df9f3 | balrog | s->ch[i].type = 0;
|
740 | b4e3104b | balrog | } |
741 | b4e3104b | balrog | } |
742 | b4e3104b | balrog | |
743 | b4e3104b | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
744 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t *value) |
745 | b4e3104b | balrog | { |
746 | b4e3104b | balrog | switch (reg) {
|
747 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
748 | b4e3104b | balrog | *value = (ch->burst[1] << 14) | |
749 | b4e3104b | balrog | (ch->pack[1] << 13) | |
750 | b4e3104b | balrog | (ch->port[1] << 9) | |
751 | b4e3104b | balrog | (ch->burst[0] << 7) | |
752 | b4e3104b | balrog | (ch->pack[0] << 6) | |
753 | b4e3104b | balrog | (ch->port[0] << 2) | |
754 | b4e3104b | balrog | (ch->data_type >> 1);
|
755 | b4e3104b | balrog | break;
|
756 | b4e3104b | balrog | |
757 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
758 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
759 | b4e3104b | balrog | *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
760 | b4e3104b | balrog | else
|
761 | b4e3104b | balrog | *value = ch->omap_3_1_compatible_disable << 10;
|
762 | b4e3104b | balrog | *value |= (ch->mode[1] << 14) | |
763 | b4e3104b | balrog | (ch->mode[0] << 12) | |
764 | b4e3104b | balrog | (ch->end_prog << 11) |
|
765 | b4e3104b | balrog | (ch->repeat << 9) |
|
766 | b4e3104b | balrog | (ch->auto_init << 8) |
|
767 | b4e3104b | balrog | (ch->enable << 7) |
|
768 | b4e3104b | balrog | (ch->priority << 6) |
|
769 | b4e3104b | balrog | (ch->fs << 5) | ch->sync;
|
770 | b4e3104b | balrog | break;
|
771 | b4e3104b | balrog | |
772 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
773 | b4e3104b | balrog | *value = ch->interrupts; |
774 | b4e3104b | balrog | break;
|
775 | b4e3104b | balrog | |
776 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
777 | b4e3104b | balrog | *value = ch->status; |
778 | b4e3104b | balrog | ch->status &= SYNC; |
779 | b4e3104b | balrog | if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
780 | b4e3104b | balrog | *value |= (ch->sibling->status & 0x3f) << 6; |
781 | b4e3104b | balrog | ch->sibling->status &= SYNC; |
782 | b4e3104b | balrog | } |
783 | b4e3104b | balrog | qemu_irq_lower(ch->irq); |
784 | b4e3104b | balrog | break;
|
785 | b4e3104b | balrog | |
786 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
787 | b4e3104b | balrog | *value = ch->addr[0] & 0x0000ffff; |
788 | b4e3104b | balrog | break;
|
789 | b4e3104b | balrog | |
790 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
791 | b4e3104b | balrog | *value = ch->addr[0] >> 16; |
792 | b4e3104b | balrog | break;
|
793 | b4e3104b | balrog | |
794 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
795 | b4e3104b | balrog | *value = ch->addr[1] & 0x0000ffff; |
796 | b4e3104b | balrog | break;
|
797 | b4e3104b | balrog | |
798 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
799 | b4e3104b | balrog | *value = ch->addr[1] >> 16; |
800 | b4e3104b | balrog | break;
|
801 | b4e3104b | balrog | |
802 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
803 | b4e3104b | balrog | *value = ch->elements; |
804 | b4e3104b | balrog | break;
|
805 | b4e3104b | balrog | |
806 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
807 | b4e3104b | balrog | *value = ch->frames; |
808 | b4e3104b | balrog | break;
|
809 | b4e3104b | balrog | |
810 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
811 | b4e3104b | balrog | *value = ch->frame_index[0];
|
812 | b4e3104b | balrog | break;
|
813 | b4e3104b | balrog | |
814 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
815 | b4e3104b | balrog | *value = ch->element_index[0];
|
816 | b4e3104b | balrog | break;
|
817 | b4e3104b | balrog | |
818 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
819 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable)
|
820 | b4e3104b | balrog | *value = ch->active_set.src & 0xffff; /* CSAC */ |
821 | b4e3104b | balrog | else
|
822 | b4e3104b | balrog | *value = ch->cpc; |
823 | b4e3104b | balrog | break;
|
824 | b4e3104b | balrog | |
825 | b4e3104b | balrog | case 0x1a: /* DMA_CDAC */ |
826 | b4e3104b | balrog | *value = ch->active_set.dest & 0xffff; /* CDAC */ |
827 | b4e3104b | balrog | break;
|
828 | b4e3104b | balrog | |
829 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
830 | b4e3104b | balrog | *value = ch->element_index[1];
|
831 | b4e3104b | balrog | break;
|
832 | b4e3104b | balrog | |
833 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
834 | b4e3104b | balrog | *value = ch->frame_index[1];
|
835 | b4e3104b | balrog | break;
|
836 | b4e3104b | balrog | |
837 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
838 | b4e3104b | balrog | *value = ch->color & 0xffff;
|
839 | b4e3104b | balrog | break;
|
840 | b4e3104b | balrog | |
841 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
842 | b4e3104b | balrog | *value = ch->color >> 16;
|
843 | b4e3104b | balrog | break;
|
844 | b4e3104b | balrog | |
845 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
846 | b4e3104b | balrog | *value = (ch->bs << 2) |
|
847 | b4e3104b | balrog | (ch->transparent_copy << 1) |
|
848 | b4e3104b | balrog | ch->constant_fill; |
849 | b4e3104b | balrog | break;
|
850 | b4e3104b | balrog | |
851 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
852 | b4e3104b | balrog | *value = (ch->link_enabled << 15) |
|
853 | b4e3104b | balrog | (ch->link_next_ch & 0xf);
|
854 | b4e3104b | balrog | break;
|
855 | b4e3104b | balrog | |
856 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
857 | b4e3104b | balrog | *value = (ch->interleave_disabled << 15) |
|
858 | b4e3104b | balrog | ch->type; |
859 | b4e3104b | balrog | break;
|
860 | b4e3104b | balrog | |
861 | b4e3104b | balrog | default:
|
862 | b4e3104b | balrog | return 1; |
863 | b4e3104b | balrog | } |
864 | b4e3104b | balrog | return 0; |
865 | b4e3104b | balrog | } |
866 | b4e3104b | balrog | |
867 | b4e3104b | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
868 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t value) |
869 | b4e3104b | balrog | { |
870 | b4e3104b | balrog | switch (reg) {
|
871 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
872 | b4e3104b | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
873 | b4e3104b | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
874 | b4e3104b | balrog | ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
875 | b4e3104b | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
876 | b4e3104b | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
877 | b4e3104b | balrog | ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
878 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
879 | 827df9f3 | balrog | if (ch->port[0] >= __omap_dma_port_last) |
880 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
881 | b4e3104b | balrog | ch->port[0]);
|
882 | 827df9f3 | balrog | if (ch->port[1] >= __omap_dma_port_last) |
883 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
884 | b4e3104b | balrog | ch->port[1]);
|
885 | b4e3104b | balrog | if ((value & 3) == 3) |
886 | b4e3104b | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
887 | b4e3104b | balrog | break;
|
888 | b4e3104b | balrog | |
889 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
890 | c227f099 | Anthony Liguori | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
891 | c227f099 | Anthony Liguori | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
892 | b4e3104b | balrog | ch->end_prog = (value & 0x0800) >> 11; |
893 | 827df9f3 | balrog | if (s->model >= omap_dma_3_2)
|
894 | b4e3104b | balrog | ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
895 | b4e3104b | balrog | ch->repeat = (value & 0x0200) >> 9; |
896 | b4e3104b | balrog | ch->auto_init = (value & 0x0100) >> 8; |
897 | b4e3104b | balrog | ch->priority = (value & 0x0040) >> 6; |
898 | b4e3104b | balrog | ch->fs = (value & 0x0020) >> 5; |
899 | b4e3104b | balrog | ch->sync = value & 0x001f;
|
900 | b4e3104b | balrog | |
901 | b4e3104b | balrog | if (value & 0x0080) |
902 | b4e3104b | balrog | omap_dma_enable_channel(s, ch); |
903 | b4e3104b | balrog | else
|
904 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
905 | b4e3104b | balrog | |
906 | b4e3104b | balrog | if (ch->end_prog)
|
907 | b4e3104b | balrog | omap_dma_channel_end_prog(s, ch); |
908 | b4e3104b | balrog | |
909 | b4e3104b | balrog | break;
|
910 | b4e3104b | balrog | |
911 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
912 | 827df9f3 | balrog | ch->interrupts = value & 0x3f;
|
913 | b4e3104b | balrog | break;
|
914 | b4e3104b | balrog | |
915 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
916 | c227f099 | Anthony Liguori | OMAP_RO_REG((target_phys_addr_t) reg); |
917 | b4e3104b | balrog | break;
|
918 | b4e3104b | balrog | |
919 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
920 | b4e3104b | balrog | ch->addr[0] &= 0xffff0000; |
921 | b4e3104b | balrog | ch->addr[0] |= value;
|
922 | b4e3104b | balrog | break;
|
923 | b4e3104b | balrog | |
924 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
925 | b4e3104b | balrog | ch->addr[0] &= 0x0000ffff; |
926 | b4e3104b | balrog | ch->addr[0] |= (uint32_t) value << 16; |
927 | b4e3104b | balrog | break;
|
928 | b4e3104b | balrog | |
929 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
930 | b4e3104b | balrog | ch->addr[1] &= 0xffff0000; |
931 | b4e3104b | balrog | ch->addr[1] |= value;
|
932 | b4e3104b | balrog | break;
|
933 | b4e3104b | balrog | |
934 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
935 | b4e3104b | balrog | ch->addr[1] &= 0x0000ffff; |
936 | b4e3104b | balrog | ch->addr[1] |= (uint32_t) value << 16; |
937 | b4e3104b | balrog | break;
|
938 | b4e3104b | balrog | |
939 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
940 | b4e3104b | balrog | ch->elements = value; |
941 | b4e3104b | balrog | break;
|
942 | b4e3104b | balrog | |
943 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
944 | b4e3104b | balrog | ch->frames = value; |
945 | b4e3104b | balrog | break;
|
946 | b4e3104b | balrog | |
947 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
948 | b4e3104b | balrog | ch->frame_index[0] = (int16_t) value;
|
949 | b4e3104b | balrog | break;
|
950 | b4e3104b | balrog | |
951 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
952 | b4e3104b | balrog | ch->element_index[0] = (int16_t) value;
|
953 | b4e3104b | balrog | break;
|
954 | b4e3104b | balrog | |
955 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
956 | c227f099 | Anthony Liguori | OMAP_RO_REG((target_phys_addr_t) reg); |
957 | b4e3104b | balrog | break;
|
958 | b4e3104b | balrog | |
959 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
960 | b4e3104b | balrog | ch->element_index[1] = (int16_t) value;
|
961 | b4e3104b | balrog | break;
|
962 | b4e3104b | balrog | |
963 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
964 | b4e3104b | balrog | ch->frame_index[1] = (int16_t) value;
|
965 | b4e3104b | balrog | break;
|
966 | b4e3104b | balrog | |
967 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
968 | b4e3104b | balrog | ch->color &= 0xffff0000;
|
969 | b4e3104b | balrog | ch->color |= value; |
970 | b4e3104b | balrog | break;
|
971 | b4e3104b | balrog | |
972 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
973 | b4e3104b | balrog | ch->color &= 0xffff;
|
974 | b4e3104b | balrog | ch->color |= value << 16;
|
975 | b4e3104b | balrog | break;
|
976 | b4e3104b | balrog | |
977 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
978 | 827df9f3 | balrog | ch->bs = (value >> 2) & 0x1; |
979 | b4e3104b | balrog | ch->transparent_copy = (value >> 1) & 0x1; |
980 | b4e3104b | balrog | ch->constant_fill = value & 0x1;
|
981 | b4e3104b | balrog | break;
|
982 | b4e3104b | balrog | |
983 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
984 | b4e3104b | balrog | ch->link_enabled = (value >> 15) & 0x1; |
985 | b4e3104b | balrog | if (value & (1 << 14)) { /* Stop_Lnk */ |
986 | b4e3104b | balrog | ch->link_enabled = 0;
|
987 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
988 | b4e3104b | balrog | } |
989 | b4e3104b | balrog | ch->link_next_ch = value & 0x1f;
|
990 | b4e3104b | balrog | break;
|
991 | b4e3104b | balrog | |
992 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
993 | b4e3104b | balrog | ch->interleave_disabled = (value >> 15) & 0x1; |
994 | b4e3104b | balrog | ch->type = value & 0xf;
|
995 | b4e3104b | balrog | break;
|
996 | b4e3104b | balrog | |
997 | b4e3104b | balrog | default:
|
998 | b4e3104b | balrog | return 1; |
999 | b4e3104b | balrog | } |
1000 | b4e3104b | balrog | return 0; |
1001 | b4e3104b | balrog | } |
1002 | b4e3104b | balrog | |
1003 | b4e3104b | balrog | static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
1004 | b4e3104b | balrog | uint16_t value) |
1005 | b4e3104b | balrog | { |
1006 | b4e3104b | balrog | switch (offset) {
|
1007 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
1008 | b4e3104b | balrog | s->brust_f2 = (value >> 14) & 0x3; |
1009 | b4e3104b | balrog | s->pack_f2 = (value >> 13) & 0x1; |
1010 | b4e3104b | balrog | s->data_type_f2 = (1 << ((value >> 11) & 0x3)); |
1011 | b4e3104b | balrog | s->brust_f1 = (value >> 7) & 0x3; |
1012 | b4e3104b | balrog | s->pack_f1 = (value >> 6) & 0x1; |
1013 | b4e3104b | balrog | s->data_type_f1 = (1 << ((value >> 0) & 0x3)); |
1014 | b4e3104b | balrog | break;
|
1015 | b4e3104b | balrog | |
1016 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
1017 | b4e3104b | balrog | s->mode_f2 = (value >> 14) & 0x3; |
1018 | b4e3104b | balrog | s->mode_f1 = (value >> 12) & 0x3; |
1019 | b4e3104b | balrog | s->end_prog = (value >> 11) & 0x1; |
1020 | b4e3104b | balrog | s->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
1021 | b4e3104b | balrog | s->repeat = (value >> 9) & 0x1; |
1022 | b4e3104b | balrog | s->auto_init = (value >> 8) & 0x1; |
1023 | b4e3104b | balrog | s->running = (value >> 7) & 0x1; |
1024 | b4e3104b | balrog | s->priority = (value >> 6) & 0x1; |
1025 | b4e3104b | balrog | s->bs = (value >> 4) & 0x1; |
1026 | b4e3104b | balrog | break;
|
1027 | b4e3104b | balrog | |
1028 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
1029 | b4e3104b | balrog | s->dst = (value >> 8) & 0x1; |
1030 | b4e3104b | balrog | s->src = ((value >> 6) & 0x3) << 1; |
1031 | b4e3104b | balrog | s->condition = 0;
|
1032 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
1033 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
1034 | b4e3104b | balrog | s->dual = value & 1;
|
1035 | b4e3104b | balrog | break;
|
1036 | b4e3104b | balrog | |
1037 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
1038 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
1039 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
1040 | b4e3104b | balrog | break;
|
1041 | b4e3104b | balrog | |
1042 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
1043 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
1044 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
1045 | b4e3104b | balrog | break;
|
1046 | b4e3104b | balrog | |
1047 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
1048 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
1049 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
1050 | b4e3104b | balrog | break;
|
1051 | b4e3104b | balrog | |
1052 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
1053 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
1054 | b4e3104b | balrog | s->src_f1_bottom |= (uint32_t) value << 16;
|
1055 | b4e3104b | balrog | break;
|
1056 | b4e3104b | balrog | |
1057 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
1058 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1059 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1060 | b4e3104b | balrog | break;
|
1061 | b4e3104b | balrog | |
1062 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
1063 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1064 | b4e3104b | balrog | s->src_f2_top |= (uint32_t) value << 16;
|
1065 | b4e3104b | balrog | break;
|
1066 | b4e3104b | balrog | |
1067 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
1068 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1069 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1070 | b4e3104b | balrog | break;
|
1071 | b4e3104b | balrog | |
1072 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
1073 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1074 | b4e3104b | balrog | s->src_f2_bottom |= (uint32_t) value << 16;
|
1075 | b4e3104b | balrog | break;
|
1076 | b4e3104b | balrog | |
1077 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
1078 | b4e3104b | balrog | s->element_index_f1 = value; |
1079 | b4e3104b | balrog | break;
|
1080 | b4e3104b | balrog | |
1081 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
1082 | b4e3104b | balrog | s->frame_index_f1 &= 0xffff0000;
|
1083 | b4e3104b | balrog | s->frame_index_f1 |= 0x0000ffff & value;
|
1084 | b4e3104b | balrog | break;
|
1085 | b4e3104b | balrog | |
1086 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
1087 | b4e3104b | balrog | s->frame_index_f1 &= 0x0000ffff;
|
1088 | b4e3104b | balrog | s->frame_index_f1 |= (uint32_t) value << 16;
|
1089 | b4e3104b | balrog | break;
|
1090 | b4e3104b | balrog | |
1091 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
1092 | b4e3104b | balrog | s->element_index_f2 = value; |
1093 | b4e3104b | balrog | break;
|
1094 | b4e3104b | balrog | |
1095 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
1096 | b4e3104b | balrog | s->frame_index_f2 &= 0xffff0000;
|
1097 | b4e3104b | balrog | s->frame_index_f2 |= 0x0000ffff & value;
|
1098 | b4e3104b | balrog | break;
|
1099 | b4e3104b | balrog | |
1100 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
1101 | b4e3104b | balrog | s->frame_index_f2 &= 0x0000ffff;
|
1102 | b4e3104b | balrog | s->frame_index_f2 |= (uint32_t) value << 16;
|
1103 | b4e3104b | balrog | break;
|
1104 | b4e3104b | balrog | |
1105 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
1106 | b4e3104b | balrog | s->elements_f1 = value; |
1107 | b4e3104b | balrog | break;
|
1108 | b4e3104b | balrog | |
1109 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
1110 | b4e3104b | balrog | s->frames_f1 = value; |
1111 | b4e3104b | balrog | break;
|
1112 | b4e3104b | balrog | |
1113 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
1114 | b4e3104b | balrog | s->elements_f2 = value; |
1115 | b4e3104b | balrog | break;
|
1116 | b4e3104b | balrog | |
1117 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
1118 | b4e3104b | balrog | s->frames_f2 = value; |
1119 | b4e3104b | balrog | break;
|
1120 | b4e3104b | balrog | |
1121 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
1122 | b4e3104b | balrog | s->lch_type = value & 0xf;
|
1123 | b4e3104b | balrog | break;
|
1124 | b4e3104b | balrog | |
1125 | b4e3104b | balrog | default:
|
1126 | b4e3104b | balrog | return 1; |
1127 | b4e3104b | balrog | } |
1128 | b4e3104b | balrog | return 0; |
1129 | b4e3104b | balrog | } |
1130 | b4e3104b | balrog | |
1131 | b4e3104b | balrog | static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1132 | b4e3104b | balrog | uint16_t *ret) |
1133 | b4e3104b | balrog | { |
1134 | b4e3104b | balrog | switch (offset) {
|
1135 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
1136 | b4e3104b | balrog | *ret = (s->brust_f2 << 14) |
|
1137 | b4e3104b | balrog | (s->pack_f2 << 13) |
|
1138 | b4e3104b | balrog | ((s->data_type_f2 >> 1) << 11) | |
1139 | b4e3104b | balrog | (s->brust_f1 << 7) |
|
1140 | b4e3104b | balrog | (s->pack_f1 << 6) |
|
1141 | b4e3104b | balrog | ((s->data_type_f1 >> 1) << 0); |
1142 | b4e3104b | balrog | break;
|
1143 | b4e3104b | balrog | |
1144 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
1145 | b4e3104b | balrog | *ret = (s->mode_f2 << 14) |
|
1146 | b4e3104b | balrog | (s->mode_f1 << 12) |
|
1147 | b4e3104b | balrog | (s->end_prog << 11) |
|
1148 | b4e3104b | balrog | (s->omap_3_1_compatible_disable << 10) |
|
1149 | b4e3104b | balrog | (s->repeat << 9) |
|
1150 | b4e3104b | balrog | (s->auto_init << 8) |
|
1151 | b4e3104b | balrog | (s->running << 7) |
|
1152 | b4e3104b | balrog | (s->priority << 6) |
|
1153 | b4e3104b | balrog | (s->bs << 4);
|
1154 | b4e3104b | balrog | break;
|
1155 | b4e3104b | balrog | |
1156 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
1157 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1158 | b4e3104b | balrog | *ret = (s->dst << 8) |
|
1159 | b4e3104b | balrog | ((s->src & 0x6) << 5) | |
1160 | b4e3104b | balrog | (s->condition << 3) |
|
1161 | b4e3104b | balrog | (s->interrupts << 1) |
|
1162 | b4e3104b | balrog | s->dual; |
1163 | b4e3104b | balrog | break;
|
1164 | b4e3104b | balrog | |
1165 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
1166 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1167 | b4e3104b | balrog | break;
|
1168 | b4e3104b | balrog | |
1169 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
1170 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1171 | b4e3104b | balrog | break;
|
1172 | b4e3104b | balrog | |
1173 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
1174 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1175 | b4e3104b | balrog | break;
|
1176 | b4e3104b | balrog | |
1177 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
1178 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1179 | b4e3104b | balrog | break;
|
1180 | b4e3104b | balrog | |
1181 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
1182 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1183 | b4e3104b | balrog | break;
|
1184 | b4e3104b | balrog | |
1185 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
1186 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1187 | b4e3104b | balrog | break;
|
1188 | b4e3104b | balrog | |
1189 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
1190 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1191 | b4e3104b | balrog | break;
|
1192 | b4e3104b | balrog | |
1193 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
1194 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1195 | b4e3104b | balrog | break;
|
1196 | b4e3104b | balrog | |
1197 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
1198 | b4e3104b | balrog | *ret = s->element_index_f1; |
1199 | b4e3104b | balrog | break;
|
1200 | b4e3104b | balrog | |
1201 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
1202 | b4e3104b | balrog | *ret = s->frame_index_f1 & 0xffff;
|
1203 | b4e3104b | balrog | break;
|
1204 | b4e3104b | balrog | |
1205 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
1206 | b4e3104b | balrog | *ret = s->frame_index_f1 >> 16;
|
1207 | b4e3104b | balrog | break;
|
1208 | b4e3104b | balrog | |
1209 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
1210 | b4e3104b | balrog | *ret = s->element_index_f2; |
1211 | b4e3104b | balrog | break;
|
1212 | b4e3104b | balrog | |
1213 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
1214 | b4e3104b | balrog | *ret = s->frame_index_f2 & 0xffff;
|
1215 | b4e3104b | balrog | break;
|
1216 | b4e3104b | balrog | |
1217 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
1218 | b4e3104b | balrog | *ret = s->frame_index_f2 >> 16;
|
1219 | b4e3104b | balrog | break;
|
1220 | b4e3104b | balrog | |
1221 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
1222 | b4e3104b | balrog | *ret = s->elements_f1; |
1223 | b4e3104b | balrog | break;
|
1224 | b4e3104b | balrog | |
1225 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
1226 | b4e3104b | balrog | *ret = s->frames_f1; |
1227 | b4e3104b | balrog | break;
|
1228 | b4e3104b | balrog | |
1229 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
1230 | b4e3104b | balrog | *ret = s->elements_f2; |
1231 | b4e3104b | balrog | break;
|
1232 | b4e3104b | balrog | |
1233 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
1234 | b4e3104b | balrog | *ret = s->frames_f2; |
1235 | b4e3104b | balrog | break;
|
1236 | b4e3104b | balrog | |
1237 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
1238 | b4e3104b | balrog | *ret = s->lch_type; |
1239 | b4e3104b | balrog | break;
|
1240 | b4e3104b | balrog | |
1241 | b4e3104b | balrog | default:
|
1242 | b4e3104b | balrog | return 1; |
1243 | b4e3104b | balrog | } |
1244 | b4e3104b | balrog | return 0; |
1245 | b4e3104b | balrog | } |
1246 | b4e3104b | balrog | |
1247 | b4e3104b | balrog | static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
1248 | b4e3104b | balrog | uint16_t value) |
1249 | b4e3104b | balrog | { |
1250 | b4e3104b | balrog | switch (offset) {
|
1251 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1252 | b4e3104b | balrog | s->src = (value & 0x40) ? imif : emiff;
|
1253 | b4e3104b | balrog | s->condition = 0;
|
1254 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
1255 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
1256 | b4e3104b | balrog | s->dual = value & 1;
|
1257 | b4e3104b | balrog | break;
|
1258 | b4e3104b | balrog | |
1259 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1260 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
1261 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
1262 | b4e3104b | balrog | break;
|
1263 | b4e3104b | balrog | |
1264 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1265 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
1266 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
1267 | b4e3104b | balrog | break;
|
1268 | b4e3104b | balrog | |
1269 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1270 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
1271 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
1272 | b4e3104b | balrog | break;
|
1273 | b4e3104b | balrog | |
1274 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1275 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
1276 | b4e3104b | balrog | s->src_f1_bottom |= value << 16;
|
1277 | b4e3104b | balrog | break;
|
1278 | b4e3104b | balrog | |
1279 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1280 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1281 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1282 | b4e3104b | balrog | break;
|
1283 | b4e3104b | balrog | |
1284 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1285 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1286 | b4e3104b | balrog | s->src_f2_top |= value << 16;
|
1287 | b4e3104b | balrog | break;
|
1288 | b4e3104b | balrog | |
1289 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1290 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1291 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1292 | b4e3104b | balrog | break;
|
1293 | b4e3104b | balrog | |
1294 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1295 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1296 | b4e3104b | balrog | s->src_f2_bottom |= value << 16;
|
1297 | b4e3104b | balrog | break;
|
1298 | b4e3104b | balrog | |
1299 | b4e3104b | balrog | default:
|
1300 | b4e3104b | balrog | return 1; |
1301 | b4e3104b | balrog | } |
1302 | b4e3104b | balrog | return 0; |
1303 | b4e3104b | balrog | } |
1304 | b4e3104b | balrog | |
1305 | b4e3104b | balrog | static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1306 | b4e3104b | balrog | uint16_t *ret) |
1307 | b4e3104b | balrog | { |
1308 | b4e3104b | balrog | int i;
|
1309 | b4e3104b | balrog | |
1310 | b4e3104b | balrog | switch (offset) {
|
1311 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1312 | b4e3104b | balrog | i = s->condition; |
1313 | b4e3104b | balrog | s->condition = 0;
|
1314 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1315 | b4e3104b | balrog | *ret = ((s->src == imif) << 6) | (i << 3) | |
1316 | b4e3104b | balrog | (s->interrupts << 1) | s->dual;
|
1317 | b4e3104b | balrog | break;
|
1318 | b4e3104b | balrog | |
1319 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1320 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1321 | b4e3104b | balrog | break;
|
1322 | b4e3104b | balrog | |
1323 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1324 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1325 | b4e3104b | balrog | break;
|
1326 | b4e3104b | balrog | |
1327 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1328 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1329 | b4e3104b | balrog | break;
|
1330 | b4e3104b | balrog | |
1331 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1332 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1333 | b4e3104b | balrog | break;
|
1334 | b4e3104b | balrog | |
1335 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1336 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1337 | b4e3104b | balrog | break;
|
1338 | b4e3104b | balrog | |
1339 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1340 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1341 | b4e3104b | balrog | break;
|
1342 | b4e3104b | balrog | |
1343 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1344 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1345 | b4e3104b | balrog | break;
|
1346 | b4e3104b | balrog | |
1347 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1348 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1349 | b4e3104b | balrog | break;
|
1350 | b4e3104b | balrog | |
1351 | b4e3104b | balrog | default:
|
1352 | b4e3104b | balrog | return 1; |
1353 | b4e3104b | balrog | } |
1354 | b4e3104b | balrog | return 0; |
1355 | b4e3104b | balrog | } |
1356 | b4e3104b | balrog | |
1357 | b4e3104b | balrog | static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) |
1358 | b4e3104b | balrog | { |
1359 | b4e3104b | balrog | switch (offset) {
|
1360 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1361 | b4e3104b | balrog | s->gcr = value; |
1362 | b4e3104b | balrog | break;
|
1363 | b4e3104b | balrog | |
1364 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1365 | b4e3104b | balrog | if (value & 0x8) |
1366 | b4e3104b | balrog | omap_dma_disable_3_1_mapping(s); |
1367 | b4e3104b | balrog | else
|
1368 | b4e3104b | balrog | omap_dma_enable_3_1_mapping(s); |
1369 | b4e3104b | balrog | break;
|
1370 | b4e3104b | balrog | |
1371 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1372 | b4e3104b | balrog | if (value & 0x1) |
1373 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1374 | b4e3104b | balrog | break;
|
1375 | b4e3104b | balrog | |
1376 | b4e3104b | balrog | default:
|
1377 | b4e3104b | balrog | return 1; |
1378 | b4e3104b | balrog | } |
1379 | b4e3104b | balrog | return 0; |
1380 | b4e3104b | balrog | } |
1381 | b4e3104b | balrog | |
1382 | b4e3104b | balrog | static int omap_dma_sys_read(struct omap_dma_s *s, int offset, |
1383 | b4e3104b | balrog | uint16_t *ret) |
1384 | b4e3104b | balrog | { |
1385 | b4e3104b | balrog | switch (offset) {
|
1386 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1387 | b4e3104b | balrog | *ret = s->gcr; |
1388 | b4e3104b | balrog | break;
|
1389 | b4e3104b | balrog | |
1390 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1391 | b4e3104b | balrog | *ret = s->omap_3_1_mapping_disabled << 3;
|
1392 | b4e3104b | balrog | break;
|
1393 | b4e3104b | balrog | |
1394 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1395 | b4e3104b | balrog | *ret = 0;
|
1396 | b4e3104b | balrog | break;
|
1397 | b4e3104b | balrog | |
1398 | b4e3104b | balrog | case 0x442: /* DMA_HW_ID */ |
1399 | b4e3104b | balrog | case 0x444: /* DMA_PCh2_ID */ |
1400 | b4e3104b | balrog | case 0x446: /* DMA_PCh0_ID */ |
1401 | b4e3104b | balrog | case 0x448: /* DMA_PCh1_ID */ |
1402 | b4e3104b | balrog | case 0x44a: /* DMA_PChG_ID */ |
1403 | b4e3104b | balrog | case 0x44c: /* DMA_PChD_ID */ |
1404 | b4e3104b | balrog | *ret = 1;
|
1405 | b4e3104b | balrog | break;
|
1406 | b4e3104b | balrog | |
1407 | b4e3104b | balrog | case 0x44e: /* DMA_CAPS_0_U */ |
1408 | 827df9f3 | balrog | *ret = (s->caps[0] >> 16) & 0xffff; |
1409 | b4e3104b | balrog | break;
|
1410 | b4e3104b | balrog | case 0x450: /* DMA_CAPS_0_L */ |
1411 | 827df9f3 | balrog | *ret = (s->caps[0] >> 0) & 0xffff; |
1412 | b4e3104b | balrog | break;
|
1413 | b4e3104b | balrog | |
1414 | 827df9f3 | balrog | case 0x452: /* DMA_CAPS_1_U */ |
1415 | 827df9f3 | balrog | *ret = (s->caps[1] >> 16) & 0xffff; |
1416 | 827df9f3 | balrog | break;
|
1417 | b4e3104b | balrog | case 0x454: /* DMA_CAPS_1_L */ |
1418 | 827df9f3 | balrog | *ret = (s->caps[1] >> 0) & 0xffff; |
1419 | b4e3104b | balrog | break;
|
1420 | b4e3104b | balrog | |
1421 | b4e3104b | balrog | case 0x456: /* DMA_CAPS_2 */ |
1422 | 827df9f3 | balrog | *ret = s->caps[2];
|
1423 | b4e3104b | balrog | break;
|
1424 | b4e3104b | balrog | |
1425 | b4e3104b | balrog | case 0x458: /* DMA_CAPS_3 */ |
1426 | 827df9f3 | balrog | *ret = s->caps[3];
|
1427 | b4e3104b | balrog | break;
|
1428 | b4e3104b | balrog | |
1429 | b4e3104b | balrog | case 0x45a: /* DMA_CAPS_4 */ |
1430 | 827df9f3 | balrog | *ret = s->caps[4];
|
1431 | b4e3104b | balrog | break;
|
1432 | b4e3104b | balrog | |
1433 | b4e3104b | balrog | case 0x460: /* DMA_PCh2_SR */ |
1434 | b4e3104b | balrog | case 0x480: /* DMA_PCh0_SR */ |
1435 | b4e3104b | balrog | case 0x482: /* DMA_PCh1_SR */ |
1436 | b4e3104b | balrog | case 0x4c0: /* DMA_PChD_SR_0 */ |
1437 | b4e3104b | balrog | printf("%s: Physical Channel Status Registers not implemented.\n",
|
1438 | b4e3104b | balrog | __FUNCTION__); |
1439 | b4e3104b | balrog | *ret = 0xff;
|
1440 | b4e3104b | balrog | break;
|
1441 | b4e3104b | balrog | |
1442 | b4e3104b | balrog | default:
|
1443 | b4e3104b | balrog | return 1; |
1444 | b4e3104b | balrog | } |
1445 | b4e3104b | balrog | return 0; |
1446 | b4e3104b | balrog | } |
1447 | b4e3104b | balrog | |
1448 | c227f099 | Anthony Liguori | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
1449 | b4e3104b | balrog | { |
1450 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1451 | 8da3ff18 | pbrook | int reg, ch;
|
1452 | b4e3104b | balrog | uint16_t ret; |
1453 | b4e3104b | balrog | |
1454 | 8da3ff18 | pbrook | switch (addr) {
|
1455 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1456 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1457 | 8da3ff18 | pbrook | if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
|
1458 | b4e3104b | balrog | break;
|
1459 | b4e3104b | balrog | return ret;
|
1460 | b4e3104b | balrog | } |
1461 | b4e3104b | balrog | /* Fall through. */
|
1462 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1463 | 8da3ff18 | pbrook | reg = addr & 0x3f;
|
1464 | 8da3ff18 | pbrook | ch = (addr >> 6) & 0x0f; |
1465 | b4e3104b | balrog | if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
|
1466 | b4e3104b | balrog | break;
|
1467 | b4e3104b | balrog | return ret;
|
1468 | b4e3104b | balrog | |
1469 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1470 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1471 | b4e3104b | balrog | break;
|
1472 | b4e3104b | balrog | /* Fall through. */
|
1473 | b4e3104b | balrog | case 0x400: |
1474 | 8da3ff18 | pbrook | if (omap_dma_sys_read(s, addr, &ret))
|
1475 | b4e3104b | balrog | break;
|
1476 | b4e3104b | balrog | return ret;
|
1477 | b4e3104b | balrog | |
1478 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1479 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1480 | 8da3ff18 | pbrook | if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
|
1481 | b4e3104b | balrog | break;
|
1482 | b4e3104b | balrog | return ret;
|
1483 | b4e3104b | balrog | } |
1484 | b4e3104b | balrog | break;
|
1485 | b4e3104b | balrog | } |
1486 | b4e3104b | balrog | |
1487 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1488 | b4e3104b | balrog | return 0; |
1489 | b4e3104b | balrog | } |
1490 | b4e3104b | balrog | |
1491 | c227f099 | Anthony Liguori | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
1492 | b4e3104b | balrog | uint32_t value) |
1493 | b4e3104b | balrog | { |
1494 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1495 | 8da3ff18 | pbrook | int reg, ch;
|
1496 | b4e3104b | balrog | |
1497 | 8da3ff18 | pbrook | switch (addr) {
|
1498 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1499 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1500 | 8da3ff18 | pbrook | if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
|
1501 | b4e3104b | balrog | break;
|
1502 | b4e3104b | balrog | return;
|
1503 | b4e3104b | balrog | } |
1504 | b4e3104b | balrog | /* Fall through. */
|
1505 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1506 | 8da3ff18 | pbrook | reg = addr & 0x3f;
|
1507 | 8da3ff18 | pbrook | ch = (addr >> 6) & 0x0f; |
1508 | b4e3104b | balrog | if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
|
1509 | b4e3104b | balrog | break;
|
1510 | b4e3104b | balrog | return;
|
1511 | b4e3104b | balrog | |
1512 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1513 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1514 | b4e3104b | balrog | break;
|
1515 | b4e3104b | balrog | case 0x400: |
1516 | b4e3104b | balrog | /* Fall through. */
|
1517 | 8da3ff18 | pbrook | if (omap_dma_sys_write(s, addr, value))
|
1518 | b4e3104b | balrog | break;
|
1519 | b4e3104b | balrog | return;
|
1520 | b4e3104b | balrog | |
1521 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1522 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1523 | 8da3ff18 | pbrook | if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
|
1524 | b4e3104b | balrog | break;
|
1525 | b4e3104b | balrog | return;
|
1526 | b4e3104b | balrog | } |
1527 | b4e3104b | balrog | break;
|
1528 | b4e3104b | balrog | } |
1529 | b4e3104b | balrog | |
1530 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1531 | b4e3104b | balrog | } |
1532 | b4e3104b | balrog | |
1533 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_dma_readfn[] = { |
1534 | b4e3104b | balrog | omap_badwidth_read16, |
1535 | b4e3104b | balrog | omap_dma_read, |
1536 | b4e3104b | balrog | omap_badwidth_read16, |
1537 | b4e3104b | balrog | }; |
1538 | b4e3104b | balrog | |
1539 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_dma_writefn[] = { |
1540 | b4e3104b | balrog | omap_badwidth_write16, |
1541 | b4e3104b | balrog | omap_dma_write, |
1542 | b4e3104b | balrog | omap_badwidth_write16, |
1543 | b4e3104b | balrog | }; |
1544 | b4e3104b | balrog | |
1545 | b4e3104b | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
1546 | b4e3104b | balrog | { |
1547 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1548 | 827df9f3 | balrog | /* The request pins are level triggered in QEMU. */
|
1549 | b4e3104b | balrog | if (req) {
|
1550 | afbb5194 | balrog | if (~s->dma->drqbmp & (1 << drq)) { |
1551 | afbb5194 | balrog | s->dma->drqbmp |= 1 << drq;
|
1552 | b4e3104b | balrog | omap_dma_process_request(s, drq); |
1553 | b4e3104b | balrog | } |
1554 | b4e3104b | balrog | } else
|
1555 | afbb5194 | balrog | s->dma->drqbmp &= ~(1 << drq);
|
1556 | b4e3104b | balrog | } |
1557 | b4e3104b | balrog | |
1558 | afbb5194 | balrog | /* XXX: this won't be needed once soc_dma knows about clocks. */
|
1559 | b4e3104b | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
1560 | b4e3104b | balrog | { |
1561 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1562 | afbb5194 | balrog | int i;
|
1563 | b4e3104b | balrog | |
1564 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(s->clk); |
1565 | afbb5194 | balrog | |
1566 | afbb5194 | balrog | for (i = 0; i < s->chans; i ++) |
1567 | afbb5194 | balrog | if (s->ch[i].active)
|
1568 | afbb5194 | balrog | soc_dma_set_request(s->ch[i].dma, on); |
1569 | b4e3104b | balrog | } |
1570 | b4e3104b | balrog | |
1571 | 827df9f3 | balrog | static void omap_dma_setcaps(struct omap_dma_s *s) |
1572 | 827df9f3 | balrog | { |
1573 | 827df9f3 | balrog | switch (s->model) {
|
1574 | 827df9f3 | balrog | default:
|
1575 | 827df9f3 | balrog | case omap_dma_3_1:
|
1576 | 827df9f3 | balrog | break;
|
1577 | 827df9f3 | balrog | case omap_dma_3_2:
|
1578 | 827df9f3 | balrog | case omap_dma_4:
|
1579 | 827df9f3 | balrog | /* XXX Only available for sDMA */
|
1580 | 827df9f3 | balrog | s->caps[0] =
|
1581 | 827df9f3 | balrog | (1 << 19) | /* Constant Fill Capability */ |
1582 | 827df9f3 | balrog | (1 << 18); /* Transparent BLT Capability */ |
1583 | 827df9f3 | balrog | s->caps[1] =
|
1584 | 827df9f3 | balrog | (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ |
1585 | 827df9f3 | balrog | s->caps[2] =
|
1586 | 827df9f3 | balrog | (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ |
1587 | 827df9f3 | balrog | (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ |
1588 | 827df9f3 | balrog | (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ |
1589 | 827df9f3 | balrog | (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ |
1590 | 827df9f3 | balrog | (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ |
1591 | 827df9f3 | balrog | (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ |
1592 | 827df9f3 | balrog | (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ |
1593 | 827df9f3 | balrog | (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ |
1594 | 827df9f3 | balrog | (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ |
1595 | 827df9f3 | balrog | s->caps[3] =
|
1596 | 827df9f3 | balrog | (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ |
1597 | 827df9f3 | balrog | (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ |
1598 | 827df9f3 | balrog | (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ |
1599 | 827df9f3 | balrog | (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ |
1600 | 827df9f3 | balrog | (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ |
1601 | 827df9f3 | balrog | (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ |
1602 | 827df9f3 | balrog | (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ |
1603 | 827df9f3 | balrog | (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ |
1604 | 827df9f3 | balrog | s->caps[4] =
|
1605 | 827df9f3 | balrog | (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ |
1606 | 827df9f3 | balrog | (1 << 6) | /* SYNC_STATUS_CPBLTY */ |
1607 | 827df9f3 | balrog | (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ |
1608 | 827df9f3 | balrog | (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ |
1609 | 827df9f3 | balrog | (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ |
1610 | 827df9f3 | balrog | (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ |
1611 | 827df9f3 | balrog | (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ |
1612 | 827df9f3 | balrog | (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ |
1613 | 827df9f3 | balrog | break;
|
1614 | 827df9f3 | balrog | } |
1615 | 827df9f3 | balrog | } |
1616 | 827df9f3 | balrog | |
1617 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
1618 | b4e3104b | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
1619 | b4e3104b | balrog | enum omap_dma_model model)
|
1620 | b4e3104b | balrog | { |
1621 | b4e3104b | balrog | int iomemtype, num_irqs, memsize, i;
|
1622 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1623 | b4e3104b | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1624 | b4e3104b | balrog | |
1625 | 827df9f3 | balrog | if (model <= omap_dma_3_1) {
|
1626 | b4e3104b | balrog | num_irqs = 6;
|
1627 | b4e3104b | balrog | memsize = 0x800;
|
1628 | b4e3104b | balrog | } else {
|
1629 | b4e3104b | balrog | num_irqs = 16;
|
1630 | b4e3104b | balrog | memsize = 0xc00;
|
1631 | b4e3104b | balrog | } |
1632 | b4e3104b | balrog | s->model = model; |
1633 | b4e3104b | balrog | s->mpu = mpu; |
1634 | b4e3104b | balrog | s->clk = clk; |
1635 | b4e3104b | balrog | s->lcd_ch.irq = lcd_irq; |
1636 | b4e3104b | balrog | s->lcd_ch.mpu = mpu; |
1637 | afbb5194 | balrog | |
1638 | afbb5194 | balrog | s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); |
1639 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(clk); |
1640 | afbb5194 | balrog | s->dma->transfer_fn = omap_dma_transfer_generic; |
1641 | afbb5194 | balrog | s->dma->setup_fn = omap_dma_transfer_setup; |
1642 | afbb5194 | balrog | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1643 | afbb5194 | balrog | s->dma->opaque = s; |
1644 | afbb5194 | balrog | |
1645 | b4e3104b | balrog | while (num_irqs --)
|
1646 | b4e3104b | balrog | s->ch[num_irqs].irq = irqs[num_irqs]; |
1647 | b4e3104b | balrog | for (i = 0; i < 3; i ++) { |
1648 | b4e3104b | balrog | s->ch[i].sibling = &s->ch[i + 6];
|
1649 | b4e3104b | balrog | s->ch[i + 6].sibling = &s->ch[i];
|
1650 | b4e3104b | balrog | } |
1651 | afbb5194 | balrog | for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { |
1652 | afbb5194 | balrog | s->ch[i].dma = &s->dma->ch[i]; |
1653 | afbb5194 | balrog | s->dma->ch[i].opaque = &s->ch[i]; |
1654 | afbb5194 | balrog | } |
1655 | afbb5194 | balrog | |
1656 | afbb5194 | balrog | omap_dma_setcaps(s); |
1657 | b4e3104b | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1658 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1659 | b4e3104b | balrog | omap_dma_clk_update(s, 0, 1); |
1660 | b4e3104b | balrog | |
1661 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_dma_readfn, |
1662 | 2507c12a | Alexander Graf | omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN); |
1663 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, memsize, iomemtype); |
1664 | b4e3104b | balrog | |
1665 | afbb5194 | balrog | mpu->drq = s->dma->drq; |
1666 | afbb5194 | balrog | |
1667 | afbb5194 | balrog | return s->dma;
|
1668 | b4e3104b | balrog | } |
1669 | b4e3104b | balrog | |
1670 | 827df9f3 | balrog | static void omap_dma_interrupts_4_update(struct omap_dma_s *s) |
1671 | 827df9f3 | balrog | { |
1672 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
|
1673 | 827df9f3 | balrog | uint32_t bmp, bit; |
1674 | 827df9f3 | balrog | |
1675 | 827df9f3 | balrog | for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) |
1676 | 827df9f3 | balrog | if (ch->status) {
|
1677 | 827df9f3 | balrog | bmp |= bit; |
1678 | 827df9f3 | balrog | ch->cstatus |= ch->status; |
1679 | 827df9f3 | balrog | ch->status = 0;
|
1680 | 827df9f3 | balrog | } |
1681 | 827df9f3 | balrog | if ((s->irqstat[0] |= s->irqen[0] & bmp)) |
1682 | 827df9f3 | balrog | qemu_irq_raise(s->irq[0]);
|
1683 | 827df9f3 | balrog | if ((s->irqstat[1] |= s->irqen[1] & bmp)) |
1684 | 827df9f3 | balrog | qemu_irq_raise(s->irq[1]);
|
1685 | 827df9f3 | balrog | if ((s->irqstat[2] |= s->irqen[2] & bmp)) |
1686 | 827df9f3 | balrog | qemu_irq_raise(s->irq[2]);
|
1687 | 827df9f3 | balrog | if ((s->irqstat[3] |= s->irqen[3] & bmp)) |
1688 | 827df9f3 | balrog | qemu_irq_raise(s->irq[3]);
|
1689 | 827df9f3 | balrog | } |
1690 | 827df9f3 | balrog | |
1691 | c227f099 | Anthony Liguori | static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) |
1692 | 827df9f3 | balrog | { |
1693 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1694 | 8da3ff18 | pbrook | int irqn = 0, chnum; |
1695 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1696 | 827df9f3 | balrog | |
1697 | 8da3ff18 | pbrook | switch (addr) {
|
1698 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1699 | 827df9f3 | balrog | return 0x40; |
1700 | 827df9f3 | balrog | |
1701 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1702 | 827df9f3 | balrog | irqn ++; |
1703 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1704 | 827df9f3 | balrog | irqn ++; |
1705 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1706 | 827df9f3 | balrog | irqn ++; |
1707 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1708 | 827df9f3 | balrog | return s->irqstat[irqn];
|
1709 | 827df9f3 | balrog | |
1710 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1711 | 827df9f3 | balrog | irqn ++; |
1712 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1713 | 827df9f3 | balrog | irqn ++; |
1714 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1715 | 827df9f3 | balrog | irqn ++; |
1716 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1717 | 827df9f3 | balrog | return s->irqen[irqn];
|
1718 | 827df9f3 | balrog | |
1719 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1720 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
1721 | 827df9f3 | balrog | |
1722 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1723 | 827df9f3 | balrog | return s->ocp;
|
1724 | 827df9f3 | balrog | |
1725 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1726 | 827df9f3 | balrog | return s->caps[0]; |
1727 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1728 | 827df9f3 | balrog | return s->caps[2]; |
1729 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1730 | 827df9f3 | balrog | return s->caps[3]; |
1731 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1732 | 827df9f3 | balrog | return s->caps[4]; |
1733 | 827df9f3 | balrog | |
1734 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1735 | 827df9f3 | balrog | return s->gcr;
|
1736 | 827df9f3 | balrog | |
1737 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1738 | 8da3ff18 | pbrook | addr -= 0x80;
|
1739 | 8da3ff18 | pbrook | chnum = addr / 0x60;
|
1740 | 827df9f3 | balrog | ch = s->ch + chnum; |
1741 | 8da3ff18 | pbrook | addr -= chnum * 0x60;
|
1742 | 827df9f3 | balrog | break;
|
1743 | 827df9f3 | balrog | |
1744 | 827df9f3 | balrog | default:
|
1745 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1746 | 827df9f3 | balrog | return 0; |
1747 | 827df9f3 | balrog | } |
1748 | 827df9f3 | balrog | |
1749 | 827df9f3 | balrog | /* Per-channel registers */
|
1750 | 8da3ff18 | pbrook | switch (addr) {
|
1751 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1752 | 827df9f3 | balrog | return (ch->buf_disable << 25) | |
1753 | 827df9f3 | balrog | (ch->src_sync << 24) |
|
1754 | 827df9f3 | balrog | (ch->prefetch << 23) |
|
1755 | 827df9f3 | balrog | ((ch->sync & 0x60) << 14) | |
1756 | 827df9f3 | balrog | (ch->bs << 18) |
|
1757 | 827df9f3 | balrog | (ch->transparent_copy << 17) |
|
1758 | 827df9f3 | balrog | (ch->constant_fill << 16) |
|
1759 | 827df9f3 | balrog | (ch->mode[1] << 14) | |
1760 | 827df9f3 | balrog | (ch->mode[0] << 12) | |
1761 | 827df9f3 | balrog | (0 << 10) | (0 << 9) | |
1762 | 827df9f3 | balrog | (ch->suspend << 8) |
|
1763 | 827df9f3 | balrog | (ch->enable << 7) |
|
1764 | 827df9f3 | balrog | (ch->priority << 6) |
|
1765 | 827df9f3 | balrog | (ch->fs << 5) | (ch->sync & 0x1f); |
1766 | 827df9f3 | balrog | |
1767 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1768 | 827df9f3 | balrog | return (ch->link_enabled << 15) | ch->link_next_ch; |
1769 | 827df9f3 | balrog | |
1770 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1771 | 827df9f3 | balrog | return ch->interrupts;
|
1772 | 827df9f3 | balrog | |
1773 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1774 | 827df9f3 | balrog | return ch->cstatus;
|
1775 | 827df9f3 | balrog | |
1776 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1777 | 827df9f3 | balrog | return (ch->endian[0] << 21) | |
1778 | 827df9f3 | balrog | (ch->endian_lock[0] << 20) | |
1779 | 827df9f3 | balrog | (ch->endian[1] << 19) | |
1780 | 827df9f3 | balrog | (ch->endian_lock[1] << 18) | |
1781 | 827df9f3 | balrog | (ch->write_mode << 16) |
|
1782 | 827df9f3 | balrog | (ch->burst[1] << 14) | |
1783 | 827df9f3 | balrog | (ch->pack[1] << 13) | |
1784 | 827df9f3 | balrog | (ch->translate[1] << 9) | |
1785 | 827df9f3 | balrog | (ch->burst[0] << 7) | |
1786 | 827df9f3 | balrog | (ch->pack[0] << 6) | |
1787 | 827df9f3 | balrog | (ch->translate[0] << 2) | |
1788 | 827df9f3 | balrog | (ch->data_type >> 1);
|
1789 | 827df9f3 | balrog | |
1790 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1791 | 827df9f3 | balrog | return ch->elements;
|
1792 | 827df9f3 | balrog | |
1793 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1794 | 827df9f3 | balrog | return ch->frames;
|
1795 | 827df9f3 | balrog | |
1796 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1797 | 827df9f3 | balrog | return ch->addr[0]; |
1798 | 827df9f3 | balrog | |
1799 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1800 | 827df9f3 | balrog | return ch->addr[1]; |
1801 | 827df9f3 | balrog | |
1802 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1803 | 827df9f3 | balrog | return ch->element_index[0]; |
1804 | 827df9f3 | balrog | |
1805 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1806 | 827df9f3 | balrog | return ch->frame_index[0]; |
1807 | 827df9f3 | balrog | |
1808 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1809 | 827df9f3 | balrog | return ch->element_index[1]; |
1810 | 827df9f3 | balrog | |
1811 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
1812 | 827df9f3 | balrog | return ch->frame_index[1]; |
1813 | 827df9f3 | balrog | |
1814 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
1815 | 827df9f3 | balrog | return ch->active_set.src & 0xffff; |
1816 | 827df9f3 | balrog | |
1817 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
1818 | 827df9f3 | balrog | return ch->active_set.dest & 0xffff; |
1819 | 827df9f3 | balrog | |
1820 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
1821 | 827df9f3 | balrog | return ch->active_set.element;
|
1822 | 827df9f3 | balrog | |
1823 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
1824 | 827df9f3 | balrog | return ch->active_set.frame;
|
1825 | 827df9f3 | balrog | |
1826 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
1827 | 827df9f3 | balrog | /* XXX only in sDMA */
|
1828 | 827df9f3 | balrog | return ch->color;
|
1829 | 827df9f3 | balrog | |
1830 | 827df9f3 | balrog | default:
|
1831 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1832 | 827df9f3 | balrog | return 0; |
1833 | 827df9f3 | balrog | } |
1834 | 827df9f3 | balrog | } |
1835 | 827df9f3 | balrog | |
1836 | c227f099 | Anthony Liguori | static void omap_dma4_write(void *opaque, target_phys_addr_t addr, |
1837 | 827df9f3 | balrog | uint32_t value) |
1838 | 827df9f3 | balrog | { |
1839 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1840 | 8da3ff18 | pbrook | int chnum, irqn = 0; |
1841 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1842 | 827df9f3 | balrog | |
1843 | 8da3ff18 | pbrook | switch (addr) {
|
1844 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1845 | 827df9f3 | balrog | irqn ++; |
1846 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1847 | 827df9f3 | balrog | irqn ++; |
1848 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1849 | 827df9f3 | balrog | irqn ++; |
1850 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1851 | 827df9f3 | balrog | s->irqstat[irqn] &= ~value; |
1852 | 827df9f3 | balrog | if (!s->irqstat[irqn])
|
1853 | 827df9f3 | balrog | qemu_irq_lower(s->irq[irqn]); |
1854 | 827df9f3 | balrog | return;
|
1855 | 827df9f3 | balrog | |
1856 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1857 | 827df9f3 | balrog | irqn ++; |
1858 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1859 | 827df9f3 | balrog | irqn ++; |
1860 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1861 | 827df9f3 | balrog | irqn ++; |
1862 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1863 | 827df9f3 | balrog | s->irqen[irqn] = value; |
1864 | 827df9f3 | balrog | return;
|
1865 | 827df9f3 | balrog | |
1866 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1867 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
1868 | afbb5194 | balrog | omap_dma_reset(s->dma); |
1869 | 827df9f3 | balrog | s->ocp = value & 0x3321;
|
1870 | 827df9f3 | balrog | if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ |
1871 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
|
1872 | 827df9f3 | balrog | return;
|
1873 | 827df9f3 | balrog | |
1874 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1875 | 827df9f3 | balrog | s->gcr = value & 0x00ff00ff;
|
1876 | 827df9f3 | balrog | if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ |
1877 | 827df9f3 | balrog | fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
|
1878 | 827df9f3 | balrog | return;
|
1879 | 827df9f3 | balrog | |
1880 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1881 | 8da3ff18 | pbrook | addr -= 0x80;
|
1882 | 8da3ff18 | pbrook | chnum = addr / 0x60;
|
1883 | 827df9f3 | balrog | ch = s->ch + chnum; |
1884 | 8da3ff18 | pbrook | addr -= chnum * 0x60;
|
1885 | 827df9f3 | balrog | break;
|
1886 | 827df9f3 | balrog | |
1887 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1888 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1889 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1890 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1891 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1892 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1893 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1894 | 827df9f3 | balrog | return;
|
1895 | 827df9f3 | balrog | |
1896 | 827df9f3 | balrog | default:
|
1897 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1898 | 827df9f3 | balrog | return;
|
1899 | 827df9f3 | balrog | } |
1900 | 827df9f3 | balrog | |
1901 | 827df9f3 | balrog | /* Per-channel registers */
|
1902 | 8da3ff18 | pbrook | switch (addr) {
|
1903 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1904 | 827df9f3 | balrog | ch->buf_disable = (value >> 25) & 1; |
1905 | 827df9f3 | balrog | ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ |
1906 | 827df9f3 | balrog | if (ch->buf_disable && !ch->src_sync)
|
1907 | 827df9f3 | balrog | fprintf(stderr, "%s: Buffering disable is not allowed in "
|
1908 | 827df9f3 | balrog | "destination synchronised mode\n", __FUNCTION__);
|
1909 | 827df9f3 | balrog | ch->prefetch = (value >> 23) & 1; |
1910 | 827df9f3 | balrog | ch->bs = (value >> 18) & 1; |
1911 | 827df9f3 | balrog | ch->transparent_copy = (value >> 17) & 1; |
1912 | 827df9f3 | balrog | ch->constant_fill = (value >> 16) & 1; |
1913 | c227f099 | Anthony Liguori | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
1914 | c227f099 | Anthony Liguori | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
1915 | 827df9f3 | balrog | ch->suspend = (value & 0x0100) >> 8; |
1916 | 827df9f3 | balrog | ch->priority = (value & 0x0040) >> 6; |
1917 | 827df9f3 | balrog | ch->fs = (value & 0x0020) >> 5; |
1918 | 827df9f3 | balrog | if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) |
1919 | 827df9f3 | balrog | fprintf(stderr, "%s: For a packet transfer at least one port "
|
1920 | 827df9f3 | balrog | "must be constant-addressed\n", __FUNCTION__);
|
1921 | 827df9f3 | balrog | ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); |
1922 | 827df9f3 | balrog | /* XXX must be 0x01 for CamDMA */
|
1923 | 827df9f3 | balrog | |
1924 | 827df9f3 | balrog | if (value & 0x0080) |
1925 | 827df9f3 | balrog | omap_dma_enable_channel(s, ch); |
1926 | 827df9f3 | balrog | else
|
1927 | 827df9f3 | balrog | omap_dma_disable_channel(s, ch); |
1928 | 827df9f3 | balrog | |
1929 | 827df9f3 | balrog | break;
|
1930 | 827df9f3 | balrog | |
1931 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1932 | 827df9f3 | balrog | ch->link_enabled = (value >> 15) & 0x1; |
1933 | 827df9f3 | balrog | ch->link_next_ch = value & 0x1f;
|
1934 | 827df9f3 | balrog | break;
|
1935 | 827df9f3 | balrog | |
1936 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1937 | 827df9f3 | balrog | ch->interrupts = value & 0x09be;
|
1938 | 827df9f3 | balrog | break;
|
1939 | 827df9f3 | balrog | |
1940 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1941 | 827df9f3 | balrog | ch->cstatus &= ~value; |
1942 | 827df9f3 | balrog | break;
|
1943 | 827df9f3 | balrog | |
1944 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1945 | 827df9f3 | balrog | ch->endian[0] =(value >> 21) & 1; |
1946 | 827df9f3 | balrog | ch->endian_lock[0] =(value >> 20) & 1; |
1947 | 827df9f3 | balrog | ch->endian[1] =(value >> 19) & 1; |
1948 | 827df9f3 | balrog | ch->endian_lock[1] =(value >> 18) & 1; |
1949 | 827df9f3 | balrog | if (ch->endian[0] != ch->endian[1]) |
1950 | afbb5194 | balrog | fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
|
1951 | 827df9f3 | balrog | __FUNCTION__); |
1952 | 827df9f3 | balrog | ch->write_mode = (value >> 16) & 3; |
1953 | 827df9f3 | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
1954 | 827df9f3 | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
1955 | 827df9f3 | balrog | ch->translate[1] = (value & 0x1e00) >> 9; |
1956 | 827df9f3 | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
1957 | 827df9f3 | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
1958 | 827df9f3 | balrog | ch->translate[0] = (value & 0x003c) >> 2; |
1959 | 827df9f3 | balrog | if (ch->translate[0] | ch->translate[1]) |
1960 | 827df9f3 | balrog | fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
|
1961 | 827df9f3 | balrog | __FUNCTION__); |
1962 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
1963 | 827df9f3 | balrog | if ((value & 3) == 3) |
1964 | 827df9f3 | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
1965 | 827df9f3 | balrog | break;
|
1966 | 827df9f3 | balrog | |
1967 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1968 | afbb5194 | balrog | ch->set_update = 1;
|
1969 | 827df9f3 | balrog | ch->elements = value & 0xffffff;
|
1970 | 827df9f3 | balrog | break;
|
1971 | 827df9f3 | balrog | |
1972 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1973 | 827df9f3 | balrog | ch->frames = value & 0xffff;
|
1974 | afbb5194 | balrog | ch->set_update = 1;
|
1975 | 827df9f3 | balrog | break;
|
1976 | 827df9f3 | balrog | |
1977 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1978 | c227f099 | Anthony Liguori | ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
|
1979 | afbb5194 | balrog | ch->set_update = 1;
|
1980 | 827df9f3 | balrog | break;
|
1981 | 827df9f3 | balrog | |
1982 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1983 | c227f099 | Anthony Liguori | ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
|
1984 | afbb5194 | balrog | ch->set_update = 1;
|
1985 | 827df9f3 | balrog | break;
|
1986 | 827df9f3 | balrog | |
1987 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1988 | 827df9f3 | balrog | ch->element_index[0] = (int16_t) value;
|
1989 | afbb5194 | balrog | ch->set_update = 1;
|
1990 | 827df9f3 | balrog | break;
|
1991 | 827df9f3 | balrog | |
1992 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1993 | 827df9f3 | balrog | ch->frame_index[0] = (int32_t) value;
|
1994 | afbb5194 | balrog | ch->set_update = 1;
|
1995 | 827df9f3 | balrog | break;
|
1996 | 827df9f3 | balrog | |
1997 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1998 | 827df9f3 | balrog | ch->element_index[1] = (int16_t) value;
|
1999 | afbb5194 | balrog | ch->set_update = 1;
|
2000 | 827df9f3 | balrog | break;
|
2001 | 827df9f3 | balrog | |
2002 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
2003 | 827df9f3 | balrog | ch->frame_index[1] = (int32_t) value;
|
2004 | afbb5194 | balrog | ch->set_update = 1;
|
2005 | 827df9f3 | balrog | break;
|
2006 | 827df9f3 | balrog | |
2007 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
2008 | 827df9f3 | balrog | /* XXX only in sDMA */
|
2009 | 827df9f3 | balrog | ch->color = value; |
2010 | 827df9f3 | balrog | break;
|
2011 | 827df9f3 | balrog | |
2012 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
2013 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
2014 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
2015 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
2016 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2017 | 827df9f3 | balrog | break;
|
2018 | 827df9f3 | balrog | |
2019 | 827df9f3 | balrog | default:
|
2020 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2021 | 827df9f3 | balrog | } |
2022 | 827df9f3 | balrog | } |
2023 | 827df9f3 | balrog | |
2024 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_dma4_readfn[] = { |
2025 | 827df9f3 | balrog | omap_badwidth_read16, |
2026 | 827df9f3 | balrog | omap_dma4_read, |
2027 | 827df9f3 | balrog | omap_dma4_read, |
2028 | 827df9f3 | balrog | }; |
2029 | 827df9f3 | balrog | |
2030 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_dma4_writefn[] = { |
2031 | 827df9f3 | balrog | omap_badwidth_write16, |
2032 | 827df9f3 | balrog | omap_dma4_write, |
2033 | 827df9f3 | balrog | omap_dma4_write, |
2034 | 827df9f3 | balrog | }; |
2035 | 827df9f3 | balrog | |
2036 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
|
2037 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
2038 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk)
|
2039 | 827df9f3 | balrog | { |
2040 | afbb5194 | balrog | int iomemtype, i;
|
2041 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
2042 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
2043 | 827df9f3 | balrog | |
2044 | 827df9f3 | balrog | s->model = omap_dma_4; |
2045 | 827df9f3 | balrog | s->chans = chans; |
2046 | 827df9f3 | balrog | s->mpu = mpu; |
2047 | 827df9f3 | balrog | s->clk = fclk; |
2048 | afbb5194 | balrog | |
2049 | afbb5194 | balrog | s->dma = soc_dma_init(s->chans); |
2050 | afbb5194 | balrog | s->dma->freq = omap_clk_getrate(fclk); |
2051 | afbb5194 | balrog | s->dma->transfer_fn = omap_dma_transfer_generic; |
2052 | afbb5194 | balrog | s->dma->setup_fn = omap_dma_transfer_setup; |
2053 | afbb5194 | balrog | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
|
2054 | afbb5194 | balrog | s->dma->opaque = s; |
2055 | afbb5194 | balrog | for (i = 0; i < s->chans; i ++) { |
2056 | afbb5194 | balrog | s->ch[i].dma = &s->dma->ch[i]; |
2057 | afbb5194 | balrog | s->dma->ch[i].opaque = &s->ch[i]; |
2058 | afbb5194 | balrog | } |
2059 | afbb5194 | balrog | |
2060 | 827df9f3 | balrog | memcpy(&s->irq, irqs, sizeof(s->irq));
|
2061 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_4_update; |
2062 | afbb5194 | balrog | |
2063 | 827df9f3 | balrog | omap_dma_setcaps(s); |
2064 | 827df9f3 | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
2065 | afbb5194 | balrog | omap_dma_reset(s->dma); |
2066 | afbb5194 | balrog | omap_dma_clk_update(s, 0, !!s->dma->freq);
|
2067 | 827df9f3 | balrog | |
2068 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_dma4_readfn, |
2069 | 2507c12a | Alexander Graf | omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN); |
2070 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x1000, iomemtype);
|
2071 | 827df9f3 | balrog | |
2072 | afbb5194 | balrog | mpu->drq = s->dma->drq; |
2073 | afbb5194 | balrog | |
2074 | afbb5194 | balrog | return s->dma;
|
2075 | 827df9f3 | balrog | } |
2076 | 827df9f3 | balrog | |
2077 | afbb5194 | balrog | struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) |
2078 | b4e3104b | balrog | { |
2079 | afbb5194 | balrog | struct omap_dma_s *s = dma->opaque;
|
2080 | afbb5194 | balrog | |
2081 | b4e3104b | balrog | return &s->lcd_ch;
|
2082 | b4e3104b | balrog | } |