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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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* maintained by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <pthread.h> |
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "qemu-queue.h" |
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#include "monitor.h" |
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#include "sysemu.h" |
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#include "qxl.h" |
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#undef SPICE_RING_PROD_ITEM
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#define SPICE_RING_PROD_ITEM(r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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abort(); \ |
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} \ |
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ret = &m_item->el; \ |
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} |
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#undef SPICE_RING_CONS_ITEM
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#define SPICE_RING_CONS_ITEM(r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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abort(); \ |
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} \ |
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ret = &m_item->el; \ |
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} |
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#undef ALIGN
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#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) |
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#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" |
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#define QXL_MODE(_x, _y, _b, _o) \
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{ .x_res = _x, \ |
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.y_res = _y, \ |
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.bits = _b, \ |
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.stride = (_x) * (_b) / 8, \
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.x_mili = PIXEL_SIZE * (_x), \ |
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.y_mili = PIXEL_SIZE * (_y), \ |
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.orientation = _o, \ |
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} |
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#define QXL_MODE_16_32(x_res, y_res, orientation) \
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QXL_MODE(x_res, y_res, 16, orientation), \
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QXL_MODE(x_res, y_res, 32, orientation)
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#define QXL_MODE_EX(x_res, y_res) \
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QXL_MODE_16_32(x_res, y_res, 0), \
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QXL_MODE_16_32(y_res, x_res, 1), \
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QXL_MODE_16_32(x_res, y_res, 2), \
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QXL_MODE_16_32(y_res, x_res, 3)
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static QXLMode qxl_modes[] = {
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QXL_MODE_EX(640, 480), |
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QXL_MODE_EX(800, 480), |
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QXL_MODE_EX(800, 600), |
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QXL_MODE_EX(832, 624), |
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QXL_MODE_EX(960, 640), |
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QXL_MODE_EX(1024, 600), |
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QXL_MODE_EX(1024, 768), |
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QXL_MODE_EX(1152, 864), |
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QXL_MODE_EX(1152, 870), |
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QXL_MODE_EX(1280, 720), |
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QXL_MODE_EX(1280, 760), |
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QXL_MODE_EX(1280, 768), |
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QXL_MODE_EX(1280, 800), |
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QXL_MODE_EX(1280, 960), |
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QXL_MODE_EX(1280, 1024), |
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QXL_MODE_EX(1360, 768), |
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QXL_MODE_EX(1366, 768), |
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QXL_MODE_EX(1400, 1050), |
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QXL_MODE_EX(1440, 900), |
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QXL_MODE_EX(1600, 900), |
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QXL_MODE_EX(1600, 1200), |
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QXL_MODE_EX(1680, 1050), |
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QXL_MODE_EX(1920, 1080), |
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#if VGA_RAM_SIZE >= (16 * 1024 * 1024) |
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/* these modes need more than 8 MB video memory */
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QXL_MODE_EX(1920, 1200), |
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QXL_MODE_EX(1920, 1440), |
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QXL_MODE_EX(2048, 1536), |
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QXL_MODE_EX(2560, 1440), |
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QXL_MODE_EX(2560, 1600), |
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#endif
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#if VGA_RAM_SIZE >= (32 * 1024 * 1024) |
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/* these modes need more than 16 MB video memory */
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QXL_MODE_EX(2560, 2048), |
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QXL_MODE_EX(2800, 2100), |
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QXL_MODE_EX(3200, 2400), |
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#endif
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}; |
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static PCIQXLDevice *qxl0;
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static void qxl_send_events(PCIQXLDevice *d, uint32_t events); |
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static void qxl_destroy_primary(PCIQXLDevice *d); |
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static void qxl_reset_memslots(PCIQXLDevice *d); |
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static void qxl_reset_surfaces(PCIQXLDevice *d); |
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl); |
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static inline uint32_t msb_mask(uint32_t val) |
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{ |
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uint32_t mask; |
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do {
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mask = ~(val - 1) & val;
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val &= ~mask; |
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} while (mask < val);
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return mask;
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} |
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static ram_addr_t qxl_rom_size(void) |
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{ |
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uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); |
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rom_size = MAX(rom_size, TARGET_PAGE_SIZE); |
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rom_size = msb_mask(rom_size * 2 - 1); |
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return rom_size;
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} |
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static void init_qxl_rom(PCIQXLDevice *d) |
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{ |
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QXLRom *rom = qemu_get_ram_ptr(d->rom_offset); |
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QXLModes *modes = (QXLModes *)(rom + 1);
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uint32_t ram_header_size; |
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uint32_t surface0_area_size; |
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uint32_t num_pages; |
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uint32_t fb, maxfb = 0;
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int i;
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memset(rom, 0, d->rom_size);
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rom->magic = cpu_to_le32(QXL_ROM_MAGIC); |
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rom->id = cpu_to_le32(d->id); |
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rom->log_level = cpu_to_le32(d->guestdebug); |
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rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
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rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; |
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rom->slot_id_bits = MEMSLOT_SLOT_BITS; |
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rom->slots_start = 1;
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rom->slots_end = NUM_MEMSLOTS - 1;
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rom->n_surfaces = cpu_to_le32(NUM_SURFACES); |
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modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); |
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for (i = 0; i < modes->n_modes; i++) { |
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fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
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if (maxfb < fb) {
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maxfb = fb; |
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} |
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modes->modes[i].id = cpu_to_le32(i); |
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modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); |
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modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); |
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modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); |
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modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); |
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modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); |
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modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); |
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modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); |
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} |
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if (maxfb < VGA_RAM_SIZE && d->id == 0) |
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maxfb = VGA_RAM_SIZE; |
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ram_header_size = ALIGN(sizeof(QXLRam), 4096); |
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surface0_area_size = ALIGN(maxfb, 4096);
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num_pages = d->vga.vram_size; |
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num_pages -= ram_header_size; |
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num_pages -= surface0_area_size; |
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num_pages = num_pages / TARGET_PAGE_SIZE; |
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rom->draw_area_offset = cpu_to_le32(0);
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rom->surface0_area_size = cpu_to_le32(surface0_area_size); |
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rom->pages_offset = cpu_to_le32(surface0_area_size); |
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rom->num_pages = cpu_to_le32(num_pages); |
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rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); |
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d->shadow_rom = *rom; |
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d->rom = rom; |
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d->modes = modes; |
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} |
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static void init_qxl_ram(PCIQXLDevice *d) |
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{ |
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uint8_t *buf; |
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uint64_t *item; |
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buf = d->vga.vram_ptr; |
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d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); |
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d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); |
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d->ram->int_pending = cpu_to_le32(0);
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d->ram->int_mask = cpu_to_le32(0);
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SPICE_RING_INIT(&d->ram->cmd_ring); |
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SPICE_RING_INIT(&d->ram->cursor_ring); |
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SPICE_RING_INIT(&d->ram->release_ring); |
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SPICE_RING_PROD_ITEM(&d->ram->release_ring, item); |
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*item = 0;
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qxl_ring_set_dirty(d); |
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} |
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/* can be called from spice server thread context */
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static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end) |
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{ |
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while (addr < end) {
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cpu_physical_memory_set_dirty(addr); |
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addr += TARGET_PAGE_SIZE; |
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} |
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} |
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static void qxl_rom_set_dirty(PCIQXLDevice *qxl) |
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{ |
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ram_addr_t addr = qxl->rom_offset; |
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qxl_set_dirty(addr, addr + qxl->rom_size); |
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} |
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/* called from spice server thread context only */
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static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) |
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{ |
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ram_addr_t addr = qxl->vga.vram_offset; |
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void *base = qxl->vga.vram_ptr;
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intptr_t offset; |
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offset = ptr - base; |
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offset &= ~(TARGET_PAGE_SIZE-1);
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assert(offset < qxl->vga.vram_size); |
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qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE); |
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} |
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/* can be called from spice server thread context */
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl) |
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{ |
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ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset; |
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ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size; |
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qxl_set_dirty(addr, end); |
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} |
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/*
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* keep track of some command state, for savevm/loadvm.
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* called from spice server thread context only
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*/
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static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
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{ |
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switch (le32_to_cpu(ext->cmd.type)) {
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case QXL_CMD_SURFACE:
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{ |
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QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
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uint32_t id = le32_to_cpu(cmd->surface_id); |
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PANIC_ON(id >= NUM_SURFACES); |
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if (cmd->type == QXL_SURFACE_CMD_CREATE) {
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qxl->guest_surfaces.cmds[id] = ext->cmd.data; |
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qxl->guest_surfaces.count++; |
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if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
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qxl->guest_surfaces.max = qxl->guest_surfaces.count; |
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} |
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if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
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qxl->guest_surfaces.cmds[id] = 0;
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qxl->guest_surfaces.count--; |
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} |
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break;
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} |
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case QXL_CMD_CURSOR:
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{ |
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QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
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if (cmd->type == QXL_CURSOR_SET) {
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qxl->guest_cursor = ext->cmd.data; |
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} |
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break;
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} |
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} |
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} |
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/* spice display interface callbacks */
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static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) |
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{ |
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PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
301 |
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dprint(qxl, 1, "%s:\n", __FUNCTION__); |
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qxl->ssd.worker = qxl_worker; |
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} |
305 |
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static void interface_set_compression_level(QXLInstance *sin, int level) |
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{ |
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PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
309 |
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dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level); |
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qxl->shadow_rom.compression_level = cpu_to_le32(level); |
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qxl->rom->compression_level = cpu_to_le32(level); |
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qxl_rom_set_dirty(qxl); |
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} |
315 |
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static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) |
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{ |
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PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
319 |
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qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
321 |
qxl->rom->mm_clock = cpu_to_le32(mm_time); |
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qxl_rom_set_dirty(qxl); |
323 |
} |
324 |
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static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) |
326 |
{ |
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PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
328 |
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dprint(qxl, 1, "%s:\n", __FUNCTION__); |
330 |
info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
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info->memslot_id_bits = MEMSLOT_SLOT_BITS; |
332 |
info->num_memslots = NUM_MEMSLOTS; |
333 |
info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; |
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info->internal_groupslot_id = 0;
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info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; |
336 |
info->n_surfaces = NUM_SURFACES; |
337 |
} |
338 |
|
339 |
/* called from spice server thread context only */
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340 |
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) |
341 |
{ |
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PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
343 |
SimpleSpiceUpdate *update; |
344 |
QXLCommandRing *ring; |
345 |
QXLCommand *cmd; |
346 |
int notify;
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347 |
|
348 |
switch (qxl->mode) {
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case QXL_MODE_VGA:
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dprint(qxl, 2, "%s: vga\n", __FUNCTION__); |
351 |
update = qemu_spice_create_update(&qxl->ssd); |
352 |
if (update == NULL) { |
353 |
return false; |
354 |
} |
355 |
*ext = update->ext; |
356 |
qxl_log_command(qxl, "vga", ext);
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return true; |
358 |
case QXL_MODE_COMPAT:
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359 |
case QXL_MODE_NATIVE:
|
360 |
case QXL_MODE_UNDEFINED:
|
361 |
dprint(qxl, 2, "%s: %s\n", __FUNCTION__, |
362 |
qxl->cmdflags ? "compat" : "native"); |
363 |
ring = &qxl->ram->cmd_ring; |
364 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
365 |
return false; |
366 |
} |
367 |
SPICE_RING_CONS_ITEM(ring, cmd); |
368 |
ext->cmd = *cmd; |
369 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
370 |
ext->flags = qxl->cmdflags; |
371 |
SPICE_RING_POP(ring, notify); |
372 |
qxl_ring_set_dirty(qxl); |
373 |
if (notify) {
|
374 |
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); |
375 |
} |
376 |
qxl->guest_primary.commands++; |
377 |
qxl_track_command(qxl, ext); |
378 |
qxl_log_command(qxl, "cmd", ext);
|
379 |
return true; |
380 |
default:
|
381 |
return false; |
382 |
} |
383 |
} |
384 |
|
385 |
/* called from spice server thread context only */
|
386 |
static int interface_req_cmd_notification(QXLInstance *sin) |
387 |
{ |
388 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
389 |
int wait = 1; |
390 |
|
391 |
switch (qxl->mode) {
|
392 |
case QXL_MODE_COMPAT:
|
393 |
case QXL_MODE_NATIVE:
|
394 |
case QXL_MODE_UNDEFINED:
|
395 |
SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); |
396 |
qxl_ring_set_dirty(qxl); |
397 |
break;
|
398 |
default:
|
399 |
/* nothing */
|
400 |
break;
|
401 |
} |
402 |
return wait;
|
403 |
} |
404 |
|
405 |
/* called from spice server thread context only */
|
406 |
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) |
407 |
{ |
408 |
QXLReleaseRing *ring = &d->ram->release_ring; |
409 |
uint64_t *item; |
410 |
int notify;
|
411 |
|
412 |
#define QXL_FREE_BUNCH_SIZE 32 |
413 |
|
414 |
if (ring->prod - ring->cons + 1 == ring->num_items) { |
415 |
/* ring full -- can't push */
|
416 |
return;
|
417 |
} |
418 |
if (!flush && d->oom_running) {
|
419 |
/* collect everything from oom handler before pushing */
|
420 |
return;
|
421 |
} |
422 |
if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
|
423 |
/* collect a bit more before pushing */
|
424 |
return;
|
425 |
} |
426 |
|
427 |
SPICE_RING_PUSH(ring, notify); |
428 |
dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n", |
429 |
d->num_free_res, notify ? "yes" : "no", |
430 |
ring->prod - ring->cons, ring->num_items, |
431 |
ring->prod, ring->cons); |
432 |
if (notify) {
|
433 |
qxl_send_events(d, QXL_INTERRUPT_DISPLAY); |
434 |
} |
435 |
SPICE_RING_PROD_ITEM(ring, item); |
436 |
*item = 0;
|
437 |
d->num_free_res = 0;
|
438 |
d->last_release = NULL;
|
439 |
qxl_ring_set_dirty(d); |
440 |
} |
441 |
|
442 |
/* called from spice server thread context only */
|
443 |
static void interface_release_resource(QXLInstance *sin, |
444 |
struct QXLReleaseInfoExt ext)
|
445 |
{ |
446 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
447 |
QXLReleaseRing *ring; |
448 |
uint64_t *item, id; |
449 |
|
450 |
if (ext.group_id == MEMSLOT_GROUP_HOST) {
|
451 |
/* host group -> vga mode update request */
|
452 |
qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
|
453 |
return;
|
454 |
} |
455 |
|
456 |
/*
|
457 |
* ext->info points into guest-visible memory
|
458 |
* pci bar 0, $command.release_info
|
459 |
*/
|
460 |
ring = &qxl->ram->release_ring; |
461 |
SPICE_RING_PROD_ITEM(ring, item); |
462 |
if (*item == 0) { |
463 |
/* stick head into the ring */
|
464 |
id = ext.info->id; |
465 |
ext.info->next = 0;
|
466 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
467 |
*item = id; |
468 |
qxl_ring_set_dirty(qxl); |
469 |
} else {
|
470 |
/* append item to the list */
|
471 |
qxl->last_release->next = ext.info->id; |
472 |
qxl_ram_set_dirty(qxl, &qxl->last_release->next); |
473 |
ext.info->next = 0;
|
474 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
475 |
} |
476 |
qxl->last_release = ext.info; |
477 |
qxl->num_free_res++; |
478 |
dprint(qxl, 3, "%4d\r", qxl->num_free_res); |
479 |
qxl_push_free_res(qxl, 0);
|
480 |
} |
481 |
|
482 |
/* called from spice server thread context only */
|
483 |
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) |
484 |
{ |
485 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
486 |
QXLCursorRing *ring; |
487 |
QXLCommand *cmd; |
488 |
int notify;
|
489 |
|
490 |
switch (qxl->mode) {
|
491 |
case QXL_MODE_COMPAT:
|
492 |
case QXL_MODE_NATIVE:
|
493 |
case QXL_MODE_UNDEFINED:
|
494 |
ring = &qxl->ram->cursor_ring; |
495 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
496 |
return false; |
497 |
} |
498 |
SPICE_RING_CONS_ITEM(ring, cmd); |
499 |
ext->cmd = *cmd; |
500 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
501 |
ext->flags = qxl->cmdflags; |
502 |
SPICE_RING_POP(ring, notify); |
503 |
qxl_ring_set_dirty(qxl); |
504 |
if (notify) {
|
505 |
qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); |
506 |
} |
507 |
qxl->guest_primary.commands++; |
508 |
qxl_track_command(qxl, ext); |
509 |
qxl_log_command(qxl, "csr", ext);
|
510 |
if (qxl->id == 0) { |
511 |
qxl_render_cursor(qxl, ext); |
512 |
} |
513 |
return true; |
514 |
default:
|
515 |
return false; |
516 |
} |
517 |
} |
518 |
|
519 |
/* called from spice server thread context only */
|
520 |
static int interface_req_cursor_notification(QXLInstance *sin) |
521 |
{ |
522 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
523 |
int wait = 1; |
524 |
|
525 |
switch (qxl->mode) {
|
526 |
case QXL_MODE_COMPAT:
|
527 |
case QXL_MODE_NATIVE:
|
528 |
case QXL_MODE_UNDEFINED:
|
529 |
SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); |
530 |
qxl_ring_set_dirty(qxl); |
531 |
break;
|
532 |
default:
|
533 |
/* nothing */
|
534 |
break;
|
535 |
} |
536 |
return wait;
|
537 |
} |
538 |
|
539 |
/* called from spice server thread context */
|
540 |
static void interface_notify_update(QXLInstance *sin, uint32_t update_id) |
541 |
{ |
542 |
fprintf(stderr, "%s: abort()\n", __FUNCTION__);
|
543 |
abort(); |
544 |
} |
545 |
|
546 |
/* called from spice server thread context only */
|
547 |
static int interface_flush_resources(QXLInstance *sin) |
548 |
{ |
549 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
550 |
int ret;
|
551 |
|
552 |
dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res); |
553 |
ret = qxl->num_free_res; |
554 |
if (ret) {
|
555 |
qxl_push_free_res(qxl, 1);
|
556 |
} |
557 |
return ret;
|
558 |
} |
559 |
|
560 |
static const QXLInterface qxl_interface = { |
561 |
.base.type = SPICE_INTERFACE_QXL, |
562 |
.base.description = "qxl gpu",
|
563 |
.base.major_version = SPICE_INTERFACE_QXL_MAJOR, |
564 |
.base.minor_version = SPICE_INTERFACE_QXL_MINOR, |
565 |
|
566 |
.attache_worker = interface_attach_worker, |
567 |
.set_compression_level = interface_set_compression_level, |
568 |
.set_mm_time = interface_set_mm_time, |
569 |
.get_init_info = interface_get_init_info, |
570 |
|
571 |
/* the callbacks below are called from spice server thread context */
|
572 |
.get_command = interface_get_command, |
573 |
.req_cmd_notification = interface_req_cmd_notification, |
574 |
.release_resource = interface_release_resource, |
575 |
.get_cursor_command = interface_get_cursor_command, |
576 |
.req_cursor_notification = interface_req_cursor_notification, |
577 |
.notify_update = interface_notify_update, |
578 |
.flush_resources = interface_flush_resources, |
579 |
}; |
580 |
|
581 |
static void qxl_enter_vga_mode(PCIQXLDevice *d) |
582 |
{ |
583 |
if (d->mode == QXL_MODE_VGA) {
|
584 |
return;
|
585 |
} |
586 |
dprint(d, 1, "%s\n", __FUNCTION__); |
587 |
qemu_spice_create_host_primary(&d->ssd); |
588 |
d->mode = QXL_MODE_VGA; |
589 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
590 |
} |
591 |
|
592 |
static void qxl_exit_vga_mode(PCIQXLDevice *d) |
593 |
{ |
594 |
if (d->mode != QXL_MODE_VGA) {
|
595 |
return;
|
596 |
} |
597 |
dprint(d, 1, "%s\n", __FUNCTION__); |
598 |
qxl_destroy_primary(d); |
599 |
} |
600 |
|
601 |
static void qxl_set_irq(PCIQXLDevice *d) |
602 |
{ |
603 |
uint32_t pending = le32_to_cpu(d->ram->int_pending); |
604 |
uint32_t mask = le32_to_cpu(d->ram->int_mask); |
605 |
int level = !!(pending & mask);
|
606 |
qemu_set_irq(d->pci.irq[0], level);
|
607 |
qxl_ring_set_dirty(d); |
608 |
} |
609 |
|
610 |
static void qxl_write_config(PCIDevice *d, uint32_t address, |
611 |
uint32_t val, int len)
|
612 |
{ |
613 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d); |
614 |
VGACommonState *vga = &qxl->vga; |
615 |
|
616 |
vga_dirty_log_stop(vga); |
617 |
pci_default_write_config(d, address, val, len); |
618 |
if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) { |
619 |
vga->map_addr = 0;
|
620 |
} |
621 |
vga_dirty_log_start(vga); |
622 |
} |
623 |
|
624 |
static void qxl_check_state(PCIQXLDevice *d) |
625 |
{ |
626 |
QXLRam *ram = d->ram; |
627 |
|
628 |
assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
629 |
assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring)); |
630 |
} |
631 |
|
632 |
static void qxl_reset_state(PCIQXLDevice *d) |
633 |
{ |
634 |
QXLRam *ram = d->ram; |
635 |
QXLRom *rom = d->rom; |
636 |
|
637 |
assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
638 |
assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring)); |
639 |
d->shadow_rom.update_id = cpu_to_le32(0);
|
640 |
*rom = d->shadow_rom; |
641 |
qxl_rom_set_dirty(d); |
642 |
init_qxl_ram(d); |
643 |
d->num_free_res = 0;
|
644 |
d->last_release = NULL;
|
645 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
646 |
} |
647 |
|
648 |
static void qxl_soft_reset(PCIQXLDevice *d) |
649 |
{ |
650 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
651 |
qxl_check_state(d); |
652 |
|
653 |
if (d->id == 0) { |
654 |
qxl_enter_vga_mode(d); |
655 |
} else {
|
656 |
d->mode = QXL_MODE_UNDEFINED; |
657 |
} |
658 |
} |
659 |
|
660 |
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) |
661 |
{ |
662 |
dprint(d, 1, "%s: start%s\n", __FUNCTION__, |
663 |
loadvm ? " (loadvm)" : ""); |
664 |
|
665 |
qemu_mutex_unlock_iothread(); |
666 |
d->ssd.worker->reset_cursor(d->ssd.worker); |
667 |
d->ssd.worker->reset_image_cache(d->ssd.worker); |
668 |
qemu_mutex_lock_iothread(); |
669 |
qxl_reset_surfaces(d); |
670 |
qxl_reset_memslots(d); |
671 |
|
672 |
/* pre loadvm reset must not touch QXLRam. This lives in
|
673 |
* device memory, is migrated together with RAM and thus
|
674 |
* already loaded at this point */
|
675 |
if (!loadvm) {
|
676 |
qxl_reset_state(d); |
677 |
} |
678 |
qemu_spice_create_host_memslot(&d->ssd); |
679 |
qxl_soft_reset(d); |
680 |
|
681 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
682 |
} |
683 |
|
684 |
static void qxl_reset_handler(DeviceState *dev) |
685 |
{ |
686 |
PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); |
687 |
qxl_hard_reset(d, 0);
|
688 |
} |
689 |
|
690 |
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
691 |
{ |
692 |
VGACommonState *vga = opaque; |
693 |
PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); |
694 |
|
695 |
if (qxl->mode != QXL_MODE_VGA) {
|
696 |
dprint(qxl, 1, "%s\n", __FUNCTION__); |
697 |
qxl_destroy_primary(qxl); |
698 |
qxl_soft_reset(qxl); |
699 |
} |
700 |
vga_ioport_write(opaque, addr, val); |
701 |
} |
702 |
|
703 |
static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta) |
704 |
{ |
705 |
static const int regions[] = { |
706 |
QXL_RAM_RANGE_INDEX, |
707 |
QXL_VRAM_RANGE_INDEX, |
708 |
}; |
709 |
uint64_t guest_start; |
710 |
uint64_t guest_end; |
711 |
int pci_region;
|
712 |
pcibus_t pci_start; |
713 |
pcibus_t pci_end; |
714 |
intptr_t virt_start; |
715 |
QXLDevMemSlot memslot; |
716 |
int i;
|
717 |
|
718 |
guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); |
719 |
guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); |
720 |
|
721 |
dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n", |
722 |
__FUNCTION__, slot_id, |
723 |
guest_start, guest_end); |
724 |
|
725 |
PANIC_ON(slot_id >= NUM_MEMSLOTS); |
726 |
PANIC_ON(guest_start > guest_end); |
727 |
|
728 |
for (i = 0; i < ARRAY_SIZE(regions); i++) { |
729 |
pci_region = regions[i]; |
730 |
pci_start = d->pci.io_regions[pci_region].addr; |
731 |
pci_end = pci_start + d->pci.io_regions[pci_region].size; |
732 |
/* mapped? */
|
733 |
if (pci_start == -1) { |
734 |
continue;
|
735 |
} |
736 |
/* start address in range ? */
|
737 |
if (guest_start < pci_start || guest_start > pci_end) {
|
738 |
continue;
|
739 |
} |
740 |
/* end address in range ? */
|
741 |
if (guest_end > pci_end) {
|
742 |
continue;
|
743 |
} |
744 |
/* passed */
|
745 |
break;
|
746 |
} |
747 |
PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
|
748 |
|
749 |
switch (pci_region) {
|
750 |
case QXL_RAM_RANGE_INDEX:
|
751 |
virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset); |
752 |
break;
|
753 |
case QXL_VRAM_RANGE_INDEX:
|
754 |
virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset); |
755 |
break;
|
756 |
default:
|
757 |
/* should not happen */
|
758 |
abort(); |
759 |
} |
760 |
|
761 |
memslot.slot_id = slot_id; |
762 |
memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
|
763 |
memslot.virt_start = virt_start + (guest_start - pci_start); |
764 |
memslot.virt_end = virt_start + (guest_end - pci_start); |
765 |
memslot.addr_delta = memslot.virt_start - delta; |
766 |
memslot.generation = d->rom->slot_generation = 0;
|
767 |
qxl_rom_set_dirty(d); |
768 |
|
769 |
dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n", |
770 |
__FUNCTION__, memslot.slot_id, |
771 |
memslot.virt_start, memslot.virt_end); |
772 |
|
773 |
d->ssd.worker->add_memslot(d->ssd.worker, &memslot); |
774 |
d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
|
775 |
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; |
776 |
d->guest_slots[slot_id].delta = delta; |
777 |
d->guest_slots[slot_id].active = 1;
|
778 |
} |
779 |
|
780 |
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) |
781 |
{ |
782 |
dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id); |
783 |
d->ssd.worker->del_memslot(d->ssd.worker, MEMSLOT_GROUP_HOST, slot_id); |
784 |
d->guest_slots[slot_id].active = 0;
|
785 |
} |
786 |
|
787 |
static void qxl_reset_memslots(PCIQXLDevice *d) |
788 |
{ |
789 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
790 |
d->ssd.worker->reset_memslots(d->ssd.worker); |
791 |
memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
792 |
} |
793 |
|
794 |
static void qxl_reset_surfaces(PCIQXLDevice *d) |
795 |
{ |
796 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
797 |
d->mode = QXL_MODE_UNDEFINED; |
798 |
qemu_mutex_unlock_iothread(); |
799 |
d->ssd.worker->destroy_surfaces(d->ssd.worker); |
800 |
qemu_mutex_lock_iothread(); |
801 |
memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds)); |
802 |
} |
803 |
|
804 |
/* called from spice server thread context only */
|
805 |
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
806 |
{ |
807 |
uint64_t phys = le64_to_cpu(pqxl); |
808 |
uint32_t slot = (phys >> (64 - 8)) & 0xff; |
809 |
uint64_t offset = phys & 0xffffffffffff;
|
810 |
|
811 |
switch (group_id) {
|
812 |
case MEMSLOT_GROUP_HOST:
|
813 |
return (void*)offset; |
814 |
case MEMSLOT_GROUP_GUEST:
|
815 |
PANIC_ON(slot > NUM_MEMSLOTS); |
816 |
PANIC_ON(!qxl->guest_slots[slot].active); |
817 |
PANIC_ON(offset < qxl->guest_slots[slot].delta); |
818 |
offset -= qxl->guest_slots[slot].delta; |
819 |
PANIC_ON(offset > qxl->guest_slots[slot].size) |
820 |
return qxl->guest_slots[slot].ptr + offset;
|
821 |
default:
|
822 |
PANIC_ON(1);
|
823 |
} |
824 |
} |
825 |
|
826 |
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm) |
827 |
{ |
828 |
QXLDevSurfaceCreate surface; |
829 |
QXLSurfaceCreate *sc = &qxl->guest_primary.surface; |
830 |
|
831 |
assert(qxl->mode != QXL_MODE_NATIVE); |
832 |
qxl_exit_vga_mode(qxl); |
833 |
|
834 |
dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__, |
835 |
le32_to_cpu(sc->width), le32_to_cpu(sc->height)); |
836 |
|
837 |
surface.format = le32_to_cpu(sc->format); |
838 |
surface.height = le32_to_cpu(sc->height); |
839 |
surface.mem = le64_to_cpu(sc->mem); |
840 |
surface.position = le32_to_cpu(sc->position); |
841 |
surface.stride = le32_to_cpu(sc->stride); |
842 |
surface.width = le32_to_cpu(sc->width); |
843 |
surface.type = le32_to_cpu(sc->type); |
844 |
surface.flags = le32_to_cpu(sc->flags); |
845 |
|
846 |
surface.mouse_mode = true;
|
847 |
surface.group_id = MEMSLOT_GROUP_GUEST; |
848 |
if (loadvm) {
|
849 |
surface.flags |= QXL_SURF_FLAG_KEEP_DATA; |
850 |
} |
851 |
|
852 |
qxl->mode = QXL_MODE_NATIVE; |
853 |
qxl->cmdflags = 0;
|
854 |
qxl->ssd.worker->create_primary_surface(qxl->ssd.worker, 0, &surface);
|
855 |
|
856 |
/* for local rendering */
|
857 |
qxl_render_resize(qxl); |
858 |
} |
859 |
|
860 |
static void qxl_destroy_primary(PCIQXLDevice *d) |
861 |
{ |
862 |
if (d->mode == QXL_MODE_UNDEFINED) {
|
863 |
return;
|
864 |
} |
865 |
|
866 |
dprint(d, 1, "%s\n", __FUNCTION__); |
867 |
|
868 |
d->mode = QXL_MODE_UNDEFINED; |
869 |
qemu_mutex_unlock_iothread(); |
870 |
d->ssd.worker->destroy_primary_surface(d->ssd.worker, 0);
|
871 |
qemu_mutex_lock_iothread(); |
872 |
} |
873 |
|
874 |
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) |
875 |
{ |
876 |
pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
877 |
pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; |
878 |
QXLMode *mode = d->modes->modes + modenr; |
879 |
uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
880 |
QXLMemSlot slot = { |
881 |
.mem_start = start, |
882 |
.mem_end = end |
883 |
}; |
884 |
QXLSurfaceCreate surface = { |
885 |
.width = mode->x_res, |
886 |
.height = mode->y_res, |
887 |
.stride = -mode->x_res * 4,
|
888 |
.format = SPICE_SURFACE_FMT_32_xRGB, |
889 |
.flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
|
890 |
.mouse_mode = true,
|
891 |
.mem = devmem + d->shadow_rom.draw_area_offset, |
892 |
}; |
893 |
|
894 |
dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__, |
895 |
modenr, mode->x_res, mode->y_res, mode->bits, devmem); |
896 |
if (!loadvm) {
|
897 |
qxl_hard_reset(d, 0);
|
898 |
} |
899 |
|
900 |
d->guest_slots[0].slot = slot;
|
901 |
qxl_add_memslot(d, 0, devmem);
|
902 |
|
903 |
d->guest_primary.surface = surface; |
904 |
qxl_create_guest_primary(d, 0);
|
905 |
|
906 |
d->mode = QXL_MODE_COMPAT; |
907 |
d->cmdflags = QXL_COMMAND_FLAG_COMPAT; |
908 |
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ |
909 |
if (mode->bits == 16) { |
910 |
d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; |
911 |
} |
912 |
#endif
|
913 |
d->shadow_rom.mode = cpu_to_le32(modenr); |
914 |
d->rom->mode = cpu_to_le32(modenr); |
915 |
qxl_rom_set_dirty(d); |
916 |
} |
917 |
|
918 |
static void ioport_write(void *opaque, uint32_t addr, uint32_t val) |
919 |
{ |
920 |
PCIQXLDevice *d = opaque; |
921 |
uint32_t io_port = addr - d->io_base; |
922 |
|
923 |
switch (io_port) {
|
924 |
case QXL_IO_RESET:
|
925 |
case QXL_IO_SET_MODE:
|
926 |
case QXL_IO_MEMSLOT_ADD:
|
927 |
case QXL_IO_MEMSLOT_DEL:
|
928 |
case QXL_IO_CREATE_PRIMARY:
|
929 |
break;
|
930 |
default:
|
931 |
if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
|
932 |
break;
|
933 |
dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port); |
934 |
return;
|
935 |
} |
936 |
|
937 |
switch (io_port) {
|
938 |
case QXL_IO_UPDATE_AREA:
|
939 |
{ |
940 |
QXLRect update = d->ram->update_area; |
941 |
qemu_mutex_unlock_iothread(); |
942 |
d->ssd.worker->update_area(d->ssd.worker, d->ram->update_surface, |
943 |
&update, NULL, 0, 0); |
944 |
qemu_mutex_lock_iothread(); |
945 |
break;
|
946 |
} |
947 |
case QXL_IO_NOTIFY_CMD:
|
948 |
d->ssd.worker->wakeup(d->ssd.worker); |
949 |
break;
|
950 |
case QXL_IO_NOTIFY_CURSOR:
|
951 |
d->ssd.worker->wakeup(d->ssd.worker); |
952 |
break;
|
953 |
case QXL_IO_UPDATE_IRQ:
|
954 |
qxl_set_irq(d); |
955 |
break;
|
956 |
case QXL_IO_NOTIFY_OOM:
|
957 |
if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
|
958 |
break;
|
959 |
} |
960 |
pthread_yield(); |
961 |
if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
|
962 |
break;
|
963 |
} |
964 |
d->oom_running = 1;
|
965 |
d->ssd.worker->oom(d->ssd.worker); |
966 |
d->oom_running = 0;
|
967 |
break;
|
968 |
case QXL_IO_SET_MODE:
|
969 |
dprint(d, 1, "QXL_SET_MODE %d\n", val); |
970 |
qxl_set_mode(d, val, 0);
|
971 |
break;
|
972 |
case QXL_IO_LOG:
|
973 |
if (d->guestdebug) {
|
974 |
fprintf(stderr, "qxl/guest: %s", d->ram->log_buf);
|
975 |
} |
976 |
break;
|
977 |
case QXL_IO_RESET:
|
978 |
dprint(d, 1, "QXL_IO_RESET\n"); |
979 |
qxl_hard_reset(d, 0);
|
980 |
break;
|
981 |
case QXL_IO_MEMSLOT_ADD:
|
982 |
PANIC_ON(val >= NUM_MEMSLOTS); |
983 |
PANIC_ON(d->guest_slots[val].active); |
984 |
d->guest_slots[val].slot = d->ram->mem_slot; |
985 |
qxl_add_memslot(d, val, 0);
|
986 |
break;
|
987 |
case QXL_IO_MEMSLOT_DEL:
|
988 |
qxl_del_memslot(d, val); |
989 |
break;
|
990 |
case QXL_IO_CREATE_PRIMARY:
|
991 |
PANIC_ON(val != 0);
|
992 |
dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n"); |
993 |
d->guest_primary.surface = d->ram->create_surface; |
994 |
qxl_create_guest_primary(d, 0);
|
995 |
break;
|
996 |
case QXL_IO_DESTROY_PRIMARY:
|
997 |
PANIC_ON(val != 0);
|
998 |
dprint(d, 1, "QXL_IO_DESTROY_PRIMARY\n"); |
999 |
qxl_destroy_primary(d); |
1000 |
break;
|
1001 |
case QXL_IO_DESTROY_SURFACE_WAIT:
|
1002 |
d->ssd.worker->destroy_surface_wait(d->ssd.worker, val); |
1003 |
break;
|
1004 |
case QXL_IO_DESTROY_ALL_SURFACES:
|
1005 |
d->ssd.worker->destroy_surfaces(d->ssd.worker); |
1006 |
break;
|
1007 |
default:
|
1008 |
fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
|
1009 |
abort(); |
1010 |
} |
1011 |
} |
1012 |
|
1013 |
static uint32_t ioport_read(void *opaque, uint32_t addr) |
1014 |
{ |
1015 |
PCIQXLDevice *d = opaque; |
1016 |
|
1017 |
dprint(d, 1, "%s: unexpected\n", __FUNCTION__); |
1018 |
return 0xff; |
1019 |
} |
1020 |
|
1021 |
static void qxl_map(PCIDevice *pci, int region_num, |
1022 |
pcibus_t addr, pcibus_t size, int type)
|
1023 |
{ |
1024 |
static const char *names[] = { |
1025 |
[ QXL_IO_RANGE_INDEX ] = "ioports",
|
1026 |
[ QXL_RAM_RANGE_INDEX ] = "devram",
|
1027 |
[ QXL_ROM_RANGE_INDEX ] = "rom",
|
1028 |
[ QXL_VRAM_RANGE_INDEX ] = "vram",
|
1029 |
}; |
1030 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci); |
1031 |
|
1032 |
dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__, |
1033 |
region_num, names[region_num], addr, size); |
1034 |
|
1035 |
switch (region_num) {
|
1036 |
case QXL_IO_RANGE_INDEX:
|
1037 |
register_ioport_write(addr, size, 1, ioport_write, pci);
|
1038 |
register_ioport_read(addr, size, 1, ioport_read, pci);
|
1039 |
qxl->io_base = addr; |
1040 |
break;
|
1041 |
case QXL_RAM_RANGE_INDEX:
|
1042 |
cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM); |
1043 |
qxl->vga.map_addr = addr; |
1044 |
qxl->vga.map_end = addr + size; |
1045 |
if (qxl->id == 0) { |
1046 |
vga_dirty_log_start(&qxl->vga); |
1047 |
} |
1048 |
break;
|
1049 |
case QXL_ROM_RANGE_INDEX:
|
1050 |
cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM); |
1051 |
break;
|
1052 |
case QXL_VRAM_RANGE_INDEX:
|
1053 |
cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM); |
1054 |
break;
|
1055 |
} |
1056 |
} |
1057 |
|
1058 |
static void pipe_read(void *opaque) |
1059 |
{ |
1060 |
PCIQXLDevice *d = opaque; |
1061 |
char dummy;
|
1062 |
int len;
|
1063 |
|
1064 |
do {
|
1065 |
len = read(d->pipe[0], &dummy, sizeof(dummy)); |
1066 |
} while (len == sizeof(dummy)); |
1067 |
qxl_set_irq(d); |
1068 |
} |
1069 |
|
1070 |
/* called from spice server thread context only */
|
1071 |
static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1072 |
{ |
1073 |
uint32_t old_pending; |
1074 |
uint32_t le_events = cpu_to_le32(events); |
1075 |
|
1076 |
assert(d->ssd.running); |
1077 |
old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
1078 |
if ((old_pending & le_events) == le_events) {
|
1079 |
return;
|
1080 |
} |
1081 |
if (pthread_self() == d->main) {
|
1082 |
qxl_set_irq(d); |
1083 |
} else {
|
1084 |
if (write(d->pipe[1], d, 1) != 1) { |
1085 |
dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__); |
1086 |
} |
1087 |
} |
1088 |
} |
1089 |
|
1090 |
static void init_pipe_signaling(PCIQXLDevice *d) |
1091 |
{ |
1092 |
if (pipe(d->pipe) < 0) { |
1093 |
dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__); |
1094 |
return;
|
1095 |
} |
1096 |
#ifdef CONFIG_IOTHREAD
|
1097 |
fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
|
1098 |
#else
|
1099 |
fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */); |
1100 |
#endif
|
1101 |
fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
|
1102 |
fcntl(d->pipe[0], F_SETOWN, getpid());
|
1103 |
|
1104 |
d->main = pthread_self(); |
1105 |
qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); |
1106 |
} |
1107 |
|
1108 |
/* graphics console */
|
1109 |
|
1110 |
static void qxl_hw_update(void *opaque) |
1111 |
{ |
1112 |
PCIQXLDevice *qxl = opaque; |
1113 |
VGACommonState *vga = &qxl->vga; |
1114 |
|
1115 |
switch (qxl->mode) {
|
1116 |
case QXL_MODE_VGA:
|
1117 |
vga->update(vga); |
1118 |
break;
|
1119 |
case QXL_MODE_COMPAT:
|
1120 |
case QXL_MODE_NATIVE:
|
1121 |
qxl_render_update(qxl); |
1122 |
break;
|
1123 |
default:
|
1124 |
break;
|
1125 |
} |
1126 |
} |
1127 |
|
1128 |
static void qxl_hw_invalidate(void *opaque) |
1129 |
{ |
1130 |
PCIQXLDevice *qxl = opaque; |
1131 |
VGACommonState *vga = &qxl->vga; |
1132 |
|
1133 |
vga->invalidate(vga); |
1134 |
} |
1135 |
|
1136 |
static void qxl_hw_screen_dump(void *opaque, const char *filename) |
1137 |
{ |
1138 |
PCIQXLDevice *qxl = opaque; |
1139 |
VGACommonState *vga = &qxl->vga; |
1140 |
|
1141 |
switch (qxl->mode) {
|
1142 |
case QXL_MODE_COMPAT:
|
1143 |
case QXL_MODE_NATIVE:
|
1144 |
qxl_render_update(qxl); |
1145 |
ppm_save(filename, qxl->ssd.ds->surface); |
1146 |
break;
|
1147 |
case QXL_MODE_VGA:
|
1148 |
vga->screen_dump(vga, filename); |
1149 |
break;
|
1150 |
default:
|
1151 |
break;
|
1152 |
} |
1153 |
} |
1154 |
|
1155 |
static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) |
1156 |
{ |
1157 |
PCIQXLDevice *qxl = opaque; |
1158 |
VGACommonState *vga = &qxl->vga; |
1159 |
|
1160 |
if (qxl->mode == QXL_MODE_VGA) {
|
1161 |
vga->text_update(vga, chardata); |
1162 |
return;
|
1163 |
} |
1164 |
} |
1165 |
|
1166 |
static void qxl_vm_change_state_handler(void *opaque, int running, int reason) |
1167 |
{ |
1168 |
PCIQXLDevice *qxl = opaque; |
1169 |
qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason); |
1170 |
|
1171 |
if (!running && qxl->mode == QXL_MODE_NATIVE) {
|
1172 |
/* dirty all vram (which holds surfaces) to make sure it is saved */
|
1173 |
/* FIXME #1: should go out during "live" stage */
|
1174 |
/* FIXME #2: we only need to save the areas which are actually used */
|
1175 |
ram_addr_t addr = qxl->vram_offset; |
1176 |
qxl_set_dirty(addr, addr + qxl->vram_size); |
1177 |
} |
1178 |
} |
1179 |
|
1180 |
/* display change listener */
|
1181 |
|
1182 |
static void display_update(struct DisplayState *ds, int x, int y, int w, int h) |
1183 |
{ |
1184 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1185 |
qemu_spice_display_update(&qxl0->ssd, x, y, w, h); |
1186 |
} |
1187 |
} |
1188 |
|
1189 |
static void display_resize(struct DisplayState *ds) |
1190 |
{ |
1191 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1192 |
qemu_spice_display_resize(&qxl0->ssd); |
1193 |
} |
1194 |
} |
1195 |
|
1196 |
static void display_refresh(struct DisplayState *ds) |
1197 |
{ |
1198 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1199 |
qemu_spice_display_refresh(&qxl0->ssd); |
1200 |
} |
1201 |
} |
1202 |
|
1203 |
static DisplayChangeListener display_listener = {
|
1204 |
.dpy_update = display_update, |
1205 |
.dpy_resize = display_resize, |
1206 |
.dpy_refresh = display_refresh, |
1207 |
}; |
1208 |
|
1209 |
static int qxl_init_common(PCIQXLDevice *qxl) |
1210 |
{ |
1211 |
uint8_t* config = qxl->pci.config; |
1212 |
uint32_t pci_device_id; |
1213 |
uint32_t pci_device_rev; |
1214 |
uint32_t io_size; |
1215 |
|
1216 |
qxl->mode = QXL_MODE_UNDEFINED; |
1217 |
qxl->generation = 1;
|
1218 |
qxl->num_memslots = NUM_MEMSLOTS; |
1219 |
qxl->num_surfaces = NUM_SURFACES; |
1220 |
|
1221 |
switch (qxl->revision) {
|
1222 |
case 1: /* spice 0.4 -- qxl-1 */ |
1223 |
pci_device_id = QXL_DEVICE_ID_STABLE; |
1224 |
pci_device_rev = QXL_REVISION_STABLE_V04; |
1225 |
break;
|
1226 |
case 2: /* spice 0.6 -- qxl-2 */ |
1227 |
pci_device_id = QXL_DEVICE_ID_STABLE; |
1228 |
pci_device_rev = QXL_REVISION_STABLE_V06; |
1229 |
break;
|
1230 |
default: /* experimental */ |
1231 |
pci_device_id = QXL_DEVICE_ID_DEVEL; |
1232 |
pci_device_rev = 1;
|
1233 |
break;
|
1234 |
} |
1235 |
|
1236 |
pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID); |
1237 |
pci_config_set_device_id(config, pci_device_id); |
1238 |
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1239 |
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
|
1240 |
|
1241 |
qxl->rom_size = qxl_rom_size(); |
1242 |
qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
|
1243 |
init_qxl_rom(qxl); |
1244 |
init_qxl_ram(qxl); |
1245 |
|
1246 |
if (qxl->vram_size < 16 * 1024 * 1024) { |
1247 |
qxl->vram_size = 16 * 1024 * 1024; |
1248 |
} |
1249 |
if (qxl->revision == 1) { |
1250 |
qxl->vram_size = 4096;
|
1251 |
} |
1252 |
qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1253 |
qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
|
1254 |
|
1255 |
io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
1256 |
if (qxl->revision == 1) { |
1257 |
io_size = 8;
|
1258 |
} |
1259 |
|
1260 |
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
1261 |
io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map); |
1262 |
|
1263 |
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
1264 |
qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY, |
1265 |
qxl_map); |
1266 |
|
1267 |
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
1268 |
qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY, |
1269 |
qxl_map); |
1270 |
|
1271 |
pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size, |
1272 |
PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map); |
1273 |
|
1274 |
qxl->ssd.qxl.base.sif = &qxl_interface.base; |
1275 |
qxl->ssd.qxl.id = qxl->id; |
1276 |
qemu_spice_add_interface(&qxl->ssd.qxl.base); |
1277 |
qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
1278 |
|
1279 |
init_pipe_signaling(qxl); |
1280 |
qxl_reset_state(qxl); |
1281 |
|
1282 |
return 0; |
1283 |
} |
1284 |
|
1285 |
static int qxl_init_primary(PCIDevice *dev) |
1286 |
{ |
1287 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
1288 |
VGACommonState *vga = &qxl->vga; |
1289 |
ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
1290 |
|
1291 |
qxl->id = 0;
|
1292 |
|
1293 |
if (ram_size < 32 * 1024 * 1024) { |
1294 |
ram_size = 32 * 1024 * 1024; |
1295 |
} |
1296 |
vga_common_init(vga, ram_size); |
1297 |
vga_init(vga); |
1298 |
register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga); |
1299 |
register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga); |
1300 |
register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga); |
1301 |
register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga); |
1302 |
register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga); |
1303 |
|
1304 |
vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, |
1305 |
qxl_hw_screen_dump, qxl_hw_text_update, qxl); |
1306 |
qxl->ssd.ds = vga->ds; |
1307 |
qxl->ssd.bufsize = (16 * 1024 * 1024); |
1308 |
qxl->ssd.buf = qemu_malloc(qxl->ssd.bufsize); |
1309 |
|
1310 |
qxl0 = qxl; |
1311 |
register_displaychangelistener(vga->ds, &display_listener); |
1312 |
|
1313 |
pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA); |
1314 |
return qxl_init_common(qxl);
|
1315 |
} |
1316 |
|
1317 |
static int qxl_init_secondary(PCIDevice *dev) |
1318 |
{ |
1319 |
static int device_id = 1; |
1320 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
1321 |
ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
1322 |
|
1323 |
qxl->id = device_id++; |
1324 |
|
1325 |
if (ram_size < 16 * 1024 * 1024) { |
1326 |
ram_size = 16 * 1024 * 1024; |
1327 |
} |
1328 |
qxl->vga.vram_size = ram_size; |
1329 |
qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
|
1330 |
qxl->vga.vram_size); |
1331 |
qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset); |
1332 |
|
1333 |
pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER); |
1334 |
return qxl_init_common(qxl);
|
1335 |
} |
1336 |
|
1337 |
static void qxl_pre_save(void *opaque) |
1338 |
{ |
1339 |
PCIQXLDevice* d = opaque; |
1340 |
uint8_t *ram_start = d->vga.vram_ptr; |
1341 |
|
1342 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
1343 |
if (d->last_release == NULL) { |
1344 |
d->last_release_offset = 0;
|
1345 |
} else {
|
1346 |
d->last_release_offset = (uint8_t *)d->last_release - ram_start; |
1347 |
} |
1348 |
assert(d->last_release_offset < d->vga.vram_size); |
1349 |
} |
1350 |
|
1351 |
static int qxl_pre_load(void *opaque) |
1352 |
{ |
1353 |
PCIQXLDevice* d = opaque; |
1354 |
|
1355 |
dprint(d, 1, "%s: start\n", __FUNCTION__); |
1356 |
qxl_hard_reset(d, 1);
|
1357 |
qxl_exit_vga_mode(d); |
1358 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
1359 |
return 0; |
1360 |
} |
1361 |
|
1362 |
static int qxl_post_load(void *opaque, int version) |
1363 |
{ |
1364 |
PCIQXLDevice* d = opaque; |
1365 |
uint8_t *ram_start = d->vga.vram_ptr; |
1366 |
QXLCommandExt *cmds; |
1367 |
int in, out, i, newmode;
|
1368 |
|
1369 |
dprint(d, 1, "%s: start\n", __FUNCTION__); |
1370 |
|
1371 |
assert(d->last_release_offset < d->vga.vram_size); |
1372 |
if (d->last_release_offset == 0) { |
1373 |
d->last_release = NULL;
|
1374 |
} else {
|
1375 |
d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); |
1376 |
} |
1377 |
|
1378 |
d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); |
1379 |
|
1380 |
dprint(d, 1, "%s: restore mode\n", __FUNCTION__); |
1381 |
newmode = d->mode; |
1382 |
d->mode = QXL_MODE_UNDEFINED; |
1383 |
switch (newmode) {
|
1384 |
case QXL_MODE_UNDEFINED:
|
1385 |
break;
|
1386 |
case QXL_MODE_VGA:
|
1387 |
qxl_enter_vga_mode(d); |
1388 |
break;
|
1389 |
case QXL_MODE_NATIVE:
|
1390 |
for (i = 0; i < NUM_MEMSLOTS; i++) { |
1391 |
if (!d->guest_slots[i].active) {
|
1392 |
continue;
|
1393 |
} |
1394 |
qxl_add_memslot(d, i, 0);
|
1395 |
} |
1396 |
qxl_create_guest_primary(d, 1);
|
1397 |
|
1398 |
/* replay surface-create and cursor-set commands */
|
1399 |
cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); |
1400 |
for (in = 0, out = 0; in < NUM_SURFACES; in++) { |
1401 |
if (d->guest_surfaces.cmds[in] == 0) { |
1402 |
continue;
|
1403 |
} |
1404 |
cmds[out].cmd.data = d->guest_surfaces.cmds[in]; |
1405 |
cmds[out].cmd.type = QXL_CMD_SURFACE; |
1406 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
1407 |
out++; |
1408 |
} |
1409 |
cmds[out].cmd.data = d->guest_cursor; |
1410 |
cmds[out].cmd.type = QXL_CMD_CURSOR; |
1411 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
1412 |
out++; |
1413 |
d->ssd.worker->loadvm_commands(d->ssd.worker, cmds, out); |
1414 |
qemu_free(cmds); |
1415 |
|
1416 |
break;
|
1417 |
case QXL_MODE_COMPAT:
|
1418 |
qxl_set_mode(d, d->shadow_rom.mode, 1);
|
1419 |
break;
|
1420 |
} |
1421 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
1422 |
|
1423 |
return 0; |
1424 |
} |
1425 |
|
1426 |
#define QXL_SAVE_VERSION 21 |
1427 |
|
1428 |
static VMStateDescription qxl_memslot = {
|
1429 |
.name = "qxl-memslot",
|
1430 |
.version_id = QXL_SAVE_VERSION, |
1431 |
.minimum_version_id = QXL_SAVE_VERSION, |
1432 |
.fields = (VMStateField[]) { |
1433 |
VMSTATE_UINT64(slot.mem_start, struct guest_slots),
|
1434 |
VMSTATE_UINT64(slot.mem_end, struct guest_slots),
|
1435 |
VMSTATE_UINT32(active, struct guest_slots),
|
1436 |
VMSTATE_END_OF_LIST() |
1437 |
} |
1438 |
}; |
1439 |
|
1440 |
static VMStateDescription qxl_surface = {
|
1441 |
.name = "qxl-surface",
|
1442 |
.version_id = QXL_SAVE_VERSION, |
1443 |
.minimum_version_id = QXL_SAVE_VERSION, |
1444 |
.fields = (VMStateField[]) { |
1445 |
VMSTATE_UINT32(width, QXLSurfaceCreate), |
1446 |
VMSTATE_UINT32(height, QXLSurfaceCreate), |
1447 |
VMSTATE_INT32(stride, QXLSurfaceCreate), |
1448 |
VMSTATE_UINT32(format, QXLSurfaceCreate), |
1449 |
VMSTATE_UINT32(position, QXLSurfaceCreate), |
1450 |
VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), |
1451 |
VMSTATE_UINT32(flags, QXLSurfaceCreate), |
1452 |
VMSTATE_UINT32(type, QXLSurfaceCreate), |
1453 |
VMSTATE_UINT64(mem, QXLSurfaceCreate), |
1454 |
VMSTATE_END_OF_LIST() |
1455 |
} |
1456 |
}; |
1457 |
|
1458 |
static VMStateDescription qxl_vmstate = {
|
1459 |
.name = "qxl",
|
1460 |
.version_id = QXL_SAVE_VERSION, |
1461 |
.minimum_version_id = QXL_SAVE_VERSION, |
1462 |
.pre_save = qxl_pre_save, |
1463 |
.pre_load = qxl_pre_load, |
1464 |
.post_load = qxl_post_load, |
1465 |
.fields = (VMStateField []) { |
1466 |
VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
1467 |
VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
|
1468 |
VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), |
1469 |
VMSTATE_UINT32(num_free_res, PCIQXLDevice), |
1470 |
VMSTATE_UINT32(last_release_offset, PCIQXLDevice), |
1471 |
VMSTATE_UINT32(mode, PCIQXLDevice), |
1472 |
VMSTATE_UINT32(ssd.unique, PCIQXLDevice), |
1473 |
VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
1474 |
VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
|
1475 |
qxl_memslot, struct guest_slots),
|
1476 |
VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
|
1477 |
qxl_surface, QXLSurfaceCreate), |
1478 |
VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), |
1479 |
VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
|
1480 |
vmstate_info_uint64, uint64_t), |
1481 |
VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
1482 |
VMSTATE_END_OF_LIST() |
1483 |
}, |
1484 |
}; |
1485 |
|
1486 |
static PCIDeviceInfo qxl_info_primary = {
|
1487 |
.qdev.name = "qxl-vga",
|
1488 |
.qdev.desc = "Spice QXL GPU (primary, vga compatible)",
|
1489 |
.qdev.size = sizeof(PCIQXLDevice),
|
1490 |
.qdev.reset = qxl_reset_handler, |
1491 |
.qdev.vmsd = &qxl_vmstate, |
1492 |
.no_hotplug = 1,
|
1493 |
.init = qxl_init_primary, |
1494 |
.config_write = qxl_write_config, |
1495 |
.romfile = "vgabios-qxl.bin",
|
1496 |
.qdev.props = (Property[]) { |
1497 |
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024), |
1498 |
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024), |
1499 |
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2), |
1500 |
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), |
1501 |
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), |
1502 |
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), |
1503 |
DEFINE_PROP_END_OF_LIST(), |
1504 |
} |
1505 |
}; |
1506 |
|
1507 |
static PCIDeviceInfo qxl_info_secondary = {
|
1508 |
.qdev.name = "qxl",
|
1509 |
.qdev.desc = "Spice QXL GPU (secondary)",
|
1510 |
.qdev.size = sizeof(PCIQXLDevice),
|
1511 |
.qdev.reset = qxl_reset_handler, |
1512 |
.qdev.vmsd = &qxl_vmstate, |
1513 |
.init = qxl_init_secondary, |
1514 |
.qdev.props = (Property[]) { |
1515 |
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024), |
1516 |
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024), |
1517 |
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2), |
1518 |
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), |
1519 |
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), |
1520 |
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), |
1521 |
DEFINE_PROP_END_OF_LIST(), |
1522 |
} |
1523 |
}; |
1524 |
|
1525 |
static void qxl_register(void) |
1526 |
{ |
1527 |
pci_qdev_register(&qxl_info_primary); |
1528 |
pci_qdev_register(&qxl_info_secondary); |
1529 |
} |
1530 |
|
1531 |
device_init(qxl_register); |