root / hw / mst_fpga.c @ 4487fd34
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/*
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* PXA270-based Intel Mainstone platforms.
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* FPGA driver
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*
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* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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* <akuster@mvista.com>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h" |
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#include "pxa.h" |
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#include "mainstone.h" |
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN 0 |
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#define MST_NUM_IRQS 16 |
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#define MST_BASE MST_FPGA_PHYS
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#define MST_LEDDAT1 0x10 |
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#define MST_LEDDAT2 0x14 |
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#define MST_LEDCTRL 0x40 |
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#define MST_GPSWR 0x60 |
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#define MST_MSCWR1 0x80 |
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#define MST_MSCWR2 0x84 |
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#define MST_MSCWR3 0x88 |
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#define MST_MSCRD 0x90 |
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#define MST_INTMSKENA 0xc0 |
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#define MST_INTSETCLR 0xd0 |
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#define MST_PCMCIA0 0xe0 |
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#define MST_PCMCIA1 0xe4 |
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typedef struct mst_irq_state{ |
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target_phys_addr_t target_base; |
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qemu_irq *parent; |
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qemu_irq *pins; |
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uint32_t prev_level; |
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uint32_t leddat1; |
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uint32_t leddat2; |
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uint32_t ledctrl; |
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uint32_t gpswr; |
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uint32_t mscwr1; |
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uint32_t mscwr2; |
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uint32_t mscwr3; |
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uint32_t mscrd; |
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uint32_t intmskena; |
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uint32_t intsetclr; |
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uint32_t pcmcia0; |
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uint32_t pcmcia1; |
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}mst_irq_state; |
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static void |
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mst_fpga_update_gpio(mst_irq_state *s) |
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{ |
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uint32_t level, diff; |
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int bit;
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level = s->prev_level ^ s->intsetclr; |
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
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bit = ffs(diff) - 1;
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qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
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} |
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s->prev_level = level; |
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} |
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static void |
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mst_fpga_set_irq(void *opaque, int irq, int level) |
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{ |
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mst_irq_state *s = (mst_irq_state *)opaque; |
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if (level)
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s->prev_level |= 1u << irq;
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else
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s->prev_level &= ~(1u << irq);
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if(s->intmskena & (1u << irq)) { |
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s->intsetclr = 1u << irq;
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qemu_set_irq(s->parent[0], level);
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} |
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} |
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static uint32_t
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mst_fpga_readb(void *opaque, target_phys_addr_t addr)
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{ |
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mst_irq_state *s = (mst_irq_state *) opaque; |
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addr -= s->target_base; |
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switch (addr) {
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case MST_LEDDAT1:
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return s->leddat1;
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case MST_LEDDAT2:
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return s->leddat2;
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case MST_LEDCTRL:
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return s->ledctrl;
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case MST_GPSWR:
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return s->gpswr;
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case MST_MSCWR1:
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return s->mscwr1;
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case MST_MSCWR2:
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return s->mscwr2;
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case MST_MSCWR3:
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return s->mscwr3;
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case MST_MSCRD:
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return s->mscrd;
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case MST_INTMSKENA:
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return s->intmskena;
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case MST_INTSETCLR:
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return s->intsetclr;
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case MST_PCMCIA0:
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return s->pcmcia0;
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case MST_PCMCIA1:
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return s->pcmcia1;
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default:
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printf("Mainstone - mst_fpga_readb: Bad register offset "
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REG_FMT " \n", addr);
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} |
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return 0; |
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} |
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static void |
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mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{ |
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mst_irq_state *s = (mst_irq_state *) opaque; |
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addr -= s->target_base; |
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value &= 0xffffffff;
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switch (addr) {
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case MST_LEDDAT1:
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s->leddat1 = value; |
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break;
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case MST_LEDDAT2:
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s->leddat2 = value; |
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break;
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case MST_LEDCTRL:
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s->ledctrl = value; |
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break;
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case MST_GPSWR:
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s->gpswr = value; |
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break;
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case MST_MSCWR1:
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s->mscwr1 = value; |
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break;
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case MST_MSCWR2:
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s->mscwr2 = value; |
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break;
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case MST_MSCWR3:
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s->mscwr3 = value; |
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break;
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case MST_MSCRD:
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s->mscrd = value; |
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break;
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case MST_INTMSKENA: /* Mask interupt */ |
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s->intmskena = (value & 0xFEEFF);
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mst_fpga_update_gpio(s); |
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break;
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case MST_INTSETCLR: /* clear or set interrupt */ |
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s->intsetclr = (value & 0xFEEFF);
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break;
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case MST_PCMCIA0:
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s->pcmcia0 = value; |
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break;
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case MST_PCMCIA1:
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s->pcmcia1 = value; |
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break;
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default:
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printf("Mainstone - mst_fpga_writeb: Bad register offset "
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REG_FMT " \n", addr);
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} |
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} |
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CPUReadMemoryFunc *mst_fpga_readfn[] = { |
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mst_fpga_readb, |
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mst_fpga_readb, |
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mst_fpga_readb, |
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}; |
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CPUWriteMemoryFunc *mst_fpga_writefn[] = { |
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mst_fpga_writeb, |
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mst_fpga_writeb, |
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mst_fpga_writeb, |
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}; |
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static void |
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mst_fpga_save(QEMUFile *f, void *opaque)
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{ |
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struct mst_irq_state *s = (mst_irq_state *) opaque;
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qemu_put_be32s(f, &s->prev_level); |
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qemu_put_be32s(f, &s->leddat1); |
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qemu_put_be32s(f, &s->leddat2); |
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qemu_put_be32s(f, &s->ledctrl); |
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qemu_put_be32s(f, &s->gpswr); |
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qemu_put_be32s(f, &s->mscwr1); |
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qemu_put_be32s(f, &s->mscwr2); |
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qemu_put_be32s(f, &s->mscwr3); |
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qemu_put_be32s(f, &s->mscrd); |
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qemu_put_be32s(f, &s->intmskena); |
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qemu_put_be32s(f, &s->intsetclr); |
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qemu_put_be32s(f, &s->pcmcia0); |
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qemu_put_be32s(f, &s->pcmcia1); |
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} |
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static int |
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mst_fpga_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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mst_irq_state *s = (mst_irq_state *) opaque; |
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qemu_get_be32s(f, &s->prev_level); |
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qemu_get_be32s(f, &s->leddat1); |
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qemu_get_be32s(f, &s->leddat2); |
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qemu_get_be32s(f, &s->ledctrl); |
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qemu_get_be32s(f, &s->gpswr); |
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qemu_get_be32s(f, &s->mscwr1); |
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qemu_get_be32s(f, &s->mscwr2); |
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qemu_get_be32s(f, &s->mscwr3); |
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qemu_get_be32s(f, &s->mscrd); |
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qemu_get_be32s(f, &s->intmskena); |
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qemu_get_be32s(f, &s->intsetclr); |
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qemu_get_be32s(f, &s->pcmcia0); |
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qemu_get_be32s(f, &s->pcmcia1); |
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return 0; |
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} |
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qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq) |
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{ |
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mst_irq_state *s; |
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int iomemtype;
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qemu_irq *qi; |
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s = (mst_irq_state *) |
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qemu_mallocz(sizeof(mst_irq_state));
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if (!s)
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return NULL; |
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s->target_base = base; |
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s->parent = &cpu->pic[irq]; |
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/* alloc the external 16 irqs */
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qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS); |
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s->pins = qi; |
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iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
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mst_fpga_writefn, s); |
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cpu_register_physical_memory(MST_BASE, 0x00100000, iomemtype);
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register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s); |
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return qi;
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} |