Revision 44e04d3b
| b/target-openrisc/cpu.h | ||
|---|---|---|
| 89 | 89 |
/* Interrupt */ |
| 90 | 90 |
#define NR_IRQS 32 |
| 91 | 91 |
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/* Registers */ |
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enum {
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R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, |
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R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, |
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R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, |
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R31 |
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}; |
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/* Register aliases */ |
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enum {
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R_ZERO = R0, |
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R_SP = R1, |
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R_FP = R2, |
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R_LR = R9, |
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R_RV = R11, |
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R_RVH = R12 |
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}; |
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| 110 | 92 |
/* Unit presece register */ |
| 111 | 93 |
enum {
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| 112 | 94 |
UPR_UP = (1 << 0), |
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