Archipelago » qemu

/*

 *  ARM translation

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *  Copyright (c) 2005-2007 CodeSourcery

 *  Copyright (c) 2007 OpenedHand, Ltd.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#define ENABLE_ARCH_5J    0

#define ENABLE_ARCH_6     arm_feature(env, ARM_FEATURE_V6)

#define ENABLE_ARCH_6K   arm_feature(env, ARM_FEATURE_V6K)

#define ENABLE_ARCH_6T2   arm_feature(env, ARM_FEATURE_THUMB2)

#define ENABLE_ARCH_7     arm_feature(env, ARM_FEATURE_V7)

#define ARCH(x) if (!ENABLE_ARCH_##x) goto illegal_op;

/* internal defines */

typedef struct DisasContext {

    target_ulong pc;

    int is_jmp;

    /* Nonzero if this instruction has been conditionally skipped.  */

    int condjmp;

    /* The label that will be jumped to when the instruction is skipped.  */

    int condlabel;

    /* Thumb-2 condtional execution bits.  */

    int condexec_mask;

    int condexec_cond;

    struct TranslationBlock *tb;

    int singlestep_enabled;

    int thumb;

    int is_mem;

#if !defined(CONFIG_USER_ONLY)

    int user;

#endif

} DisasContext;

#if defined(CONFIG_USER_ONLY)

#define IS_USER(s) 1

#else

#define IS_USER(s) (s->user)

#endif

/* These instructions trap after executing, so defer them until after the

   conditional executions state has been updated.  */

#define DISAS_WFI 4

#define DISAS_SWI 5

#ifdef USE_DIRECT_JUMP

#define TBPARAM(x)

#else

#define TBPARAM(x) (long)(x)

#endif

/* XXX: move that elsewhere */

static uint16_t *gen_opc_ptr;

static uint32_t *gen_opparam_ptr;

extern FILE *logfile;

extern int loglevel;

enum {

#define DEF(s, n, copy_size) INDEX_op_ ## s,

#include "opc.h"

#undef DEF

    NB_OPS,

};

#include "gen-op.h"

#define PAS_OP(pfx) {  \

    gen_op_ ## pfx ## add16_T0_T1, \

    gen_op_ ## pfx ## addsubx_T0_T1, \

    gen_op_ ## pfx ## subaddx_T0_T1, \

    gen_op_ ## pfx ## sub16_T0_T1, \

    gen_op_ ## pfx ## add8_T0_T1, \

    NULL, \

    NULL, \

    gen_op_ ## pfx ## sub8_T0_T1 }

static GenOpFunc *gen_arm_parallel_addsub[8][8] = {

    {},

    PAS_OP(s),

    PAS_OP(q),

    PAS_OP(sh),

    {},

    PAS_OP(u),

    PAS_OP(uq),

    PAS_OP(uh),

};

#undef PAS_OP

/* For unknown reasons Arm and Thumb-2 use arbitrarily diffenet encodings.  */

#define PAS_OP(pfx) {  \

    gen_op_ ## pfx ## add8_T0_T1, \

    gen_op_ ## pfx ## add16_T0_T1, \

    gen_op_ ## pfx ## addsubx_T0_T1, \

    NULL, \

    gen_op_ ## pfx ## sub8_T0_T1, \

    gen_op_ ## pfx ## sub16_T0_T1, \

    gen_op_ ## pfx ## subaddx_T0_T1, \

    NULL }

static GenOpFunc *gen_thumb2_parallel_addsub[8][8] = {

    PAS_OP(s),

    PAS_OP(q),

    PAS_OP(sh),

    {},

    PAS_OP(u),

    PAS_OP(uq),

    PAS_OP(uh),

    {}

};

#undef PAS_OP

static GenOpFunc1 *gen_test_cc[14] = {

    gen_op_test_eq,

    gen_op_test_ne,

    gen_op_test_cs,

    gen_op_test_cc,

    gen_op_test_mi,

    gen_op_test_pl,

    gen_op_test_vs,

    gen_op_test_vc,

    gen_op_test_hi,

    gen_op_test_ls,

    gen_op_test_ge,

    gen_op_test_lt,

    gen_op_test_gt,

    gen_op_test_le,

};

const uint8_t table_logic_cc[16] = {

    1, /* and */

    1, /* xor */

    0, /* sub */

    0, /* rsb */

    0, /* add */

    0, /* adc */

    0, /* sbc */

    0, /* rsc */

    1, /* andl */

    1, /* xorl */

    0, /* cmp */

    0, /* cmn */

    1, /* orr */

    1, /* mov */

    1, /* bic */

    1, /* mvn */

};

static GenOpFunc1 *gen_shift_T1_im[4] = {

    gen_op_shll_T1_im,

    gen_op_shrl_T1_im,

    gen_op_sarl_T1_im,

    gen_op_rorl_T1_im,

};

static GenOpFunc *gen_shift_T1_0[4] = {

    NULL,

    gen_op_shrl_T1_0,

    gen_op_sarl_T1_0,

    gen_op_rrxl_T1,

};

static GenOpFunc1 *gen_shift_T2_im[4] = {

    gen_op_shll_T2_im,

    gen_op_shrl_T2_im,

    gen_op_sarl_T2_im,

    gen_op_rorl_T2_im,

};

static GenOpFunc *gen_shift_T2_0[4] = {

    NULL,

    gen_op_shrl_T2_0,

    gen_op_sarl_T2_0,

    gen_op_rrxl_T2,

};

static GenOpFunc1 *gen_shift_T1_im_cc[4] = {

    gen_op_shll_T1_im_cc,

    gen_op_shrl_T1_im_cc,

    gen_op_sarl_T1_im_cc,

    gen_op_rorl_T1_im_cc,

};

static GenOpFunc *gen_shift_T1_0_cc[4] = {

    NULL,

    gen_op_shrl_T1_0_cc,

    gen_op_sarl_T1_0_cc,

    gen_op_rrxl_T1_cc,

};

static GenOpFunc *gen_shift_T1_T0[4] = {

    gen_op_shll_T1_T0,

    gen_op_shrl_T1_T0,

    gen_op_sarl_T1_T0,

    gen_op_rorl_T1_T0,

};

static GenOpFunc *gen_shift_T1_T0_cc[4] = {

    gen_op_shll_T1_T0_cc,

    gen_op_shrl_T1_T0_cc,

    gen_op_sarl_T1_T0_cc,

    gen_op_rorl_T1_T0_cc,

};

static GenOpFunc *gen_op_movl_TN_reg[3][16] = {

    {

        gen_op_movl_T0_r0,

        gen_op_movl_T0_r1,

        gen_op_movl_T0_r2,

        gen_op_movl_T0_r3,

        gen_op_movl_T0_r4,

        gen_op_movl_T0_r5,

        gen_op_movl_T0_r6,

        gen_op_movl_T0_r7,

        gen_op_movl_T0_r8,

        gen_op_movl_T0_r9,

        gen_op_movl_T0_r10,

        gen_op_movl_T0_r11,

        gen_op_movl_T0_r12,

        gen_op_movl_T0_r13,

        gen_op_movl_T0_r14,

        gen_op_movl_T0_r15,

    },

    {

        gen_op_movl_T1_r0,

        gen_op_movl_T1_r1,

        gen_op_movl_T1_r2,

        gen_op_movl_T1_r3,

        gen_op_movl_T1_r4,

        gen_op_movl_T1_r5,

        gen_op_movl_T1_r6,

        gen_op_movl_T1_r7,

        gen_op_movl_T1_r8,

        gen_op_movl_T1_r9,

        gen_op_movl_T1_r10,

        gen_op_movl_T1_r11,

        gen_op_movl_T1_r12,

        gen_op_movl_T1_r13,

        gen_op_movl_T1_r14,

        gen_op_movl_T1_r15,

    },

    {

        gen_op_movl_T2_r0,

        gen_op_movl_T2_r1,

        gen_op_movl_T2_r2,

        gen_op_movl_T2_r3,

        gen_op_movl_T2_r4,

        gen_op_movl_T2_r5,

        gen_op_movl_T2_r6,

        gen_op_movl_T2_r7,

        gen_op_movl_T2_r8,

        gen_op_movl_T2_r9,

        gen_op_movl_T2_r10,

        gen_op_movl_T2_r11,

        gen_op_movl_T2_r12,

        gen_op_movl_T2_r13,

        gen_op_movl_T2_r14,

        gen_op_movl_T2_r15,

    },

};

static GenOpFunc *gen_op_movl_reg_TN[2][16] = {

    {

        gen_op_movl_r0_T0,

        gen_op_movl_r1_T0,

        gen_op_movl_r2_T0,

        gen_op_movl_r3_T0,

        gen_op_movl_r4_T0,

        gen_op_movl_r5_T0,

        gen_op_movl_r6_T0,

        gen_op_movl_r7_T0,

        gen_op_movl_r8_T0,

        gen_op_movl_r9_T0,

        gen_op_movl_r10_T0,

        gen_op_movl_r11_T0,

        gen_op_movl_r12_T0,

        gen_op_movl_r13_T0,

        gen_op_movl_r14_T0,

        gen_op_movl_r15_T0,

    },

    {

        gen_op_movl_r0_T1,

        gen_op_movl_r1_T1,

        gen_op_movl_r2_T1,

        gen_op_movl_r3_T1,

        gen_op_movl_r4_T1,

        gen_op_movl_r5_T1,

        gen_op_movl_r6_T1,

        gen_op_movl_r7_T1,

        gen_op_movl_r8_T1,

        gen_op_movl_r9_T1,

        gen_op_movl_r10_T1,

        gen_op_movl_r11_T1,

        gen_op_movl_r12_T1,

        gen_op_movl_r13_T1,

        gen_op_movl_r14_T1,

        gen_op_movl_r15_T1,

    },

};

static GenOpFunc1 *gen_op_movl_TN_im[3] = {

    gen_op_movl_T0_im,

    gen_op_movl_T1_im,

    gen_op_movl_T2_im,

};

static GenOpFunc1 *gen_shift_T0_im_thumb_cc[3] = {

    gen_op_shll_T0_im_thumb_cc,

    gen_op_shrl_T0_im_thumb_cc,

    gen_op_sarl_T0_im_thumb_cc,

};

static GenOpFunc1 *gen_shift_T0_im_thumb[3] = {

    gen_op_shll_T0_im_thumb,

    gen_op_shrl_T0_im_thumb,

    gen_op_sarl_T0_im_thumb,

};

static inline void gen_bx(DisasContext *s)

{

  s->is_jmp = DISAS_UPDATE;

  gen_op_bx_T0();

}

#if defined(CONFIG_USER_ONLY)

#define gen_ldst(name, s) gen_op_##name##_raw()

#else

#define gen_ldst(name, s) do { \

    s->is_mem = 1; \

    if (IS_USER(s)) \

        gen_op_##name##_user(); \

    else \

        gen_op_##name##_kernel(); \

    } while (0)

#endif

static inline void gen_movl_TN_reg(DisasContext *s, int reg, int t)

{

    int val;

    if (reg == 15) {

        /* normaly, since we updated PC, we need only to add one insn */

        if (s->thumb)

            val = (long)s->pc + 2;

        else

            val = (long)s->pc + 4;

        gen_op_movl_TN_im[t](val);

    } else {

        gen_op_movl_TN_reg[t][reg]();

    }

}

static inline void gen_movl_T0_reg(DisasContext *s, int reg)

{

    gen_movl_TN_reg(s, reg, 0);

}

static inline void gen_movl_T1_reg(DisasContext *s, int reg)

{

    gen_movl_TN_reg(s, reg, 1);

}

static inline void gen_movl_T2_reg(DisasContext *s, int reg)

{

    gen_movl_TN_reg(s, reg, 2);

}

static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)

{

    gen_op_movl_reg_TN[t][reg]();

    if (reg == 15) {

        s->is_jmp = DISAS_JUMP;

    }

}

static inline void gen_movl_reg_T0(DisasContext *s, int reg)

{

    gen_movl_reg_TN(s, reg, 0);

}

static inline void gen_movl_reg_T1(DisasContext *s, int reg)

{

    gen_movl_reg_TN(s, reg, 1);

}

/* Force a TB lookup after an instruction that changes the CPU state.  */

static inline void gen_lookup_tb(DisasContext *s)

{

    gen_op_movl_T0_im(s->pc);

    gen_movl_reg_T0(s, 15);

    s->is_jmp = DISAS_UPDATE;

}

static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)

{

    int val, rm, shift, shiftop;

    if (!(insn & (1 << 25))) {

        /* immediate */

        val = insn & 0xfff;

        if (!(insn & (1 << 23)))

            val = -val;

        if (val != 0)

            gen_op_addl_T1_im(val);

    } else {

        /* shift/register */

        rm = (insn) & 0xf;

        shift = (insn >> 7) & 0x1f;

        gen_movl_T2_reg(s, rm);

        shiftop = (insn >> 5) & 3;

        if (shift != 0) {

            gen_shift_T2_im[shiftop](shift);

        } else if (shiftop != 0) {

            gen_shift_T2_0[shiftop]();

        }

        if (!(insn & (1 << 23)))

            gen_op_subl_T1_T2();

        else

            gen_op_addl_T1_T2();

    }

}

static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,

                                        int extra)

{

    int val, rm;

    if (insn & (1 << 22)) {

        /* immediate */

        val = (insn & 0xf) | ((insn >> 4) & 0xf0);

        if (!(insn & (1 << 23)))

            val = -val;

        val += extra;

        if (val != 0)

            gen_op_addl_T1_im(val);

    } else {

        /* register */

        if (extra)

            gen_op_addl_T1_im(extra);

        rm = (insn) & 0xf;

        gen_movl_T2_reg(s, rm);

        if (!(insn & (1 << 23)))

            gen_op_subl_T1_T2();

        else

            gen_op_addl_T1_T2();

    }

}

#define VFP_OP(name)                      \

static inline void gen_vfp_##name(int dp) \

{                                         \

    if (dp)                               \

        gen_op_vfp_##name##d();           \

    else                                  \

        gen_op_vfp_##name##s();           \

}

#define VFP_OP1(name)                               \

static inline void gen_vfp_##name(int dp, int arg)  \

{                                                   \

    if (dp)                                         \

        gen_op_vfp_##name##d(arg);                  \

    else                                            \

        gen_op_vfp_##name##s(arg);                  \

}

VFP_OP(add)

VFP_OP(sub)

VFP_OP(mul)

VFP_OP(div)

VFP_OP(neg)

VFP_OP(abs)

VFP_OP(sqrt)

VFP_OP(cmp)

VFP_OP(cmpe)

VFP_OP(F1_ld0)

VFP_OP(uito)

VFP_OP(sito)

VFP_OP(toui)

VFP_OP(touiz)

VFP_OP(tosi)

VFP_OP(tosiz)

VFP_OP1(tosh)

VFP_OP1(tosl)

VFP_OP1(touh)

VFP_OP1(toul)

VFP_OP1(shto)

VFP_OP1(slto)

VFP_OP1(uhto)

VFP_OP1(ulto)

#undef VFP_OP

static inline void gen_vfp_fconst(int dp, uint32_t val)

{

    if (dp)

        gen_op_vfp_fconstd(val);

    else

        gen_op_vfp_fconsts(val);

}

static inline void gen_vfp_ld(DisasContext *s, int dp)

{

    if (dp)

        gen_ldst(vfp_ldd, s);

    else

        gen_ldst(vfp_lds, s);

}

static inline void gen_vfp_st(DisasContext *s, int dp)

{

    if (dp)

        gen_ldst(vfp_std, s);

    else

        gen_ldst(vfp_sts, s);

}

static inline long

vfp_reg_offset (int dp, int reg)

{

    if (dp)

        return offsetof(CPUARMState, vfp.regs[reg]);

    else if (reg & 1) {

        return offsetof(CPUARMState, vfp.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.upper);

    } else {

        return offsetof(CPUARMState, vfp.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.lower);

    }

}

/* Return the offset of a 32-bit piece of a NEON register.

   zero is the least significant end of the register.  */

static inline long

neon_reg_offset (int reg, int n)

{

    int sreg;

    sreg = reg * 2 + n;

    return vfp_reg_offset(0, sreg);

}

#define NEON_GET_REG(T, reg, n) gen_op_neon_getreg_##T(neon_reg_offset(reg, n))

#define NEON_SET_REG(T, reg, n) gen_op_neon_setreg_##T(neon_reg_offset(reg, n))

static inline void gen_mov_F0_vreg(int dp, int reg)

{

    if (dp)

        gen_op_vfp_getreg_F0d(vfp_reg_offset(dp, reg));

    else

        gen_op_vfp_getreg_F0s(vfp_reg_offset(dp, reg));

}

static inline void gen_mov_F1_vreg(int dp, int reg)

{

    if (dp)

        gen_op_vfp_getreg_F1d(vfp_reg_offset(dp, reg));

    else

        gen_op_vfp_getreg_F1s(vfp_reg_offset(dp, reg));

}

static inline void gen_mov_vreg_F0(int dp, int reg)

{

    if (dp)

        gen_op_vfp_setreg_F0d(vfp_reg_offset(dp, reg));

    else

        gen_op_vfp_setreg_F0s(vfp_reg_offset(dp, reg));

}

#define ARM_CP_RW_BIT        (1 << 20)

static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)

{

    int rd;

    uint32_t offset;

    rd = (insn >> 16) & 0xf;

    gen_movl_T1_reg(s, rd);

    offset = (insn & 0xff) << ((insn >> 7) & 2);

    if (insn & (1 << 24)) {

        /* Pre indexed */

        if (insn & (1 << 23))

            gen_op_addl_T1_im(offset);

        else

            gen_op_addl_T1_im(-offset);

        if (insn & (1 << 21))

            gen_movl_reg_T1(s, rd);

    } else if (insn & (1 << 21)) {

        /* Post indexed */

        if (insn & (1 << 23))

            gen_op_movl_T0_im(offset);

        else

            gen_op_movl_T0_im(- offset);

        gen_op_addl_T0_T1();

        gen_movl_reg_T0(s, rd);

    } else if (!(insn & (1 << 23)))

        return 1;

    return 0;

}

static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)

{

    int rd = (insn >> 0) & 0xf;

    if (insn & (1 << 8))

        if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3)

            return 1;

        else

            gen_op_iwmmxt_movl_T0_wCx(rd);

    else

        gen_op_iwmmxt_movl_T0_T1_wRn(rd);

    gen_op_movl_T1_im(mask);

    gen_op_andl_T0_T1();

    return 0;

}

/* Disassemble an iwMMXt instruction.  Returns nonzero if an error occured

   (ie. an undefined instruction).  */

static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)

{

    int rd, wrd;

    int rdhi, rdlo, rd0, rd1, i;

    if ((insn & 0x0e000e00) == 0x0c000000) {

        if ((insn & 0x0fe00ff0) == 0x0c400000) {

            wrd = insn & 0xf;

            rdlo = (insn >> 12) & 0xf;

            rdhi = (insn >> 16) & 0xf;

            if (insn & ARM_CP_RW_BIT) {                        /* TMRRC */

                gen_op_iwmmxt_movl_T0_T1_wRn(wrd);

                gen_movl_reg_T0(s, rdlo);

                gen_movl_reg_T1(s, rdhi);

            } else {                                        /* TMCRR */

                gen_movl_T0_reg(s, rdlo);

                gen_movl_T1_reg(s, rdhi);

                gen_op_iwmmxt_movl_wRn_T0_T1(wrd);

                gen_op_iwmmxt_set_mup();

            }

            return 0;

        }

        wrd = (insn >> 12) & 0xf;

        if (gen_iwmmxt_address(s, insn))

            return 1;

        if (insn & ARM_CP_RW_BIT) {

            if ((insn >> 28) == 0xf) {                        /* WLDRW wCx */

                gen_ldst(ldl, s);

                gen_op_iwmmxt_movl_wCx_T0(wrd);

            } else {

                if (insn & (1 << 8))

                    if (insn & (1 << 22))                /* WLDRD */

                        gen_ldst(iwmmxt_ldq, s);

                    else                                /* WLDRW wRd */

                        gen_ldst(iwmmxt_ldl, s);

                else

                    if (insn & (1 << 22))                /* WLDRH */

                        gen_ldst(iwmmxt_ldw, s);

                    else                                /* WLDRB */

                        gen_ldst(iwmmxt_ldb, s);

                gen_op_iwmmxt_movq_wRn_M0(wrd);

            }

        } else {

            if ((insn >> 28) == 0xf) {                        /* WSTRW wCx */

                gen_op_iwmmxt_movl_T0_wCx(wrd);

                gen_ldst(stl, s);

            } else {

                gen_op_iwmmxt_movq_M0_wRn(wrd);

                if (insn & (1 << 8))

                    if (insn & (1 << 22))                /* WSTRD */

                        gen_ldst(iwmmxt_stq, s);

                    else                                /* WSTRW wRd */

                        gen_ldst(iwmmxt_stl, s);

                else

                    if (insn & (1 << 22))                /* WSTRH */

                        gen_ldst(iwmmxt_ldw, s);

                    else                                /* WSTRB */

                        gen_ldst(iwmmxt_stb, s);

            }

        }

        return 0;

    }

    if ((insn & 0x0f000000) != 0x0e000000)

        return 1;

    switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {

    case 0x000:                                                /* WOR */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 0) & 0xf;

        rd1 = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        gen_op_iwmmxt_orq_M0_wRn(rd1);

        gen_op_iwmmxt_setpsr_nz();

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x011:                                                /* TMCR */

        if (insn & 0xf)

            return 1;

        rd = (insn >> 12) & 0xf;

        wrd = (insn >> 16) & 0xf;

        switch (wrd) {

        case ARM_IWMMXT_wCID:

        case ARM_IWMMXT_wCASF:

            break;

        case ARM_IWMMXT_wCon:

            gen_op_iwmmxt_set_cup();

            /* Fall through.  */

        case ARM_IWMMXT_wCSSF:

            gen_op_iwmmxt_movl_T0_wCx(wrd);

            gen_movl_T1_reg(s, rd);

            gen_op_bicl_T0_T1();

            gen_op_iwmmxt_movl_wCx_T0(wrd);

            break;

        case ARM_IWMMXT_wCGR0:

        case ARM_IWMMXT_wCGR1:

        case ARM_IWMMXT_wCGR2:

        case ARM_IWMMXT_wCGR3:

            gen_op_iwmmxt_set_cup();

            gen_movl_reg_T0(s, rd);

            gen_op_iwmmxt_movl_wCx_T0(wrd);

            break;

        default:

            return 1;

        }

        break;

    case 0x100:                                                /* WXOR */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 0) & 0xf;

        rd1 = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        gen_op_iwmmxt_xorq_M0_wRn(rd1);

        gen_op_iwmmxt_setpsr_nz();

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x111:                                                /* TMRC */

        if (insn & 0xf)

            return 1;

        rd = (insn >> 12) & 0xf;

        wrd = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movl_T0_wCx(wrd);

        gen_movl_reg_T0(s, rd);

        break;

    case 0x300:                                                /* WANDN */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 0) & 0xf;

        rd1 = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        gen_op_iwmmxt_negq_M0();

        gen_op_iwmmxt_andq_M0_wRn(rd1);

        gen_op_iwmmxt_setpsr_nz();

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x200:                                                /* WAND */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 0) & 0xf;

        rd1 = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        gen_op_iwmmxt_andq_M0_wRn(rd1);

        gen_op_iwmmxt_setpsr_nz();

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x810: case 0xa10:                                /* WMADD */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 0) & 0xf;

        rd1 = (insn >> 16) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        if (insn & (1 << 21))

            gen_op_iwmmxt_maddsq_M0_wRn(rd1);

        else

            gen_op_iwmmxt_madduq_M0_wRn(rd1);

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        break;

    case 0x10e: case 0x50e: case 0x90e: case 0xd0e:        /* WUNPCKIL */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 16) & 0xf;

        rd1 = (insn >> 0) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        switch ((insn >> 22) & 3) {

        case 0:

            gen_op_iwmmxt_unpacklb_M0_wRn(rd1);

            break;

        case 1:

            gen_op_iwmmxt_unpacklw_M0_wRn(rd1);

            break;

        case 2:

            gen_op_iwmmxt_unpackll_M0_wRn(rd1);

            break;

        case 3:

            return 1;

        }

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x10c: case 0x50c: case 0x90c: case 0xd0c:        /* WUNPCKIH */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 16) & 0xf;

        rd1 = (insn >> 0) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        switch ((insn >> 22) & 3) {

        case 0:

            gen_op_iwmmxt_unpackhb_M0_wRn(rd1);

            break;

        case 1:

            gen_op_iwmmxt_unpackhw_M0_wRn(rd1);

            break;

        case 2:

            gen_op_iwmmxt_unpackhl_M0_wRn(rd1);

            break;

        case 3:

            return 1;

        }

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        gen_op_iwmmxt_set_cup();

        break;

    case 0x012: case 0x112: case 0x412: case 0x512:        /* WSAD */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 16) & 0xf;

        rd1 = (insn >> 0) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        if (insn & (1 << 22))

            gen_op_iwmmxt_sadw_M0_wRn(rd1);

        else

            gen_op_iwmmxt_sadb_M0_wRn(rd1);

        if (!(insn & (1 << 20)))

            gen_op_iwmmxt_addl_M0_wRn(wrd);

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        break;

    case 0x010: case 0x110: case 0x210: case 0x310:        /* WMUL */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 16) & 0xf;

        rd1 = (insn >> 0) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        if (insn & (1 << 21))

            gen_op_iwmmxt_mulsw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0);

        else

            gen_op_iwmmxt_muluw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0);

        gen_op_iwmmxt_movq_wRn_M0(wrd);

        gen_op_iwmmxt_set_mup();

        break;

    case 0x410: case 0x510: case 0x610: case 0x710:        /* WMAC */

        wrd = (insn >> 12) & 0xf;

        rd0 = (insn >> 16) & 0xf;

        rd1 = (insn >> 0) & 0xf;

        gen_op_iwmmxt_movq_M0_wRn(rd0);

        if (insn & (1 << 21))

            gen_op_iwmmxt_macsw_M0_wRn(rd1);