root / hw / slavio_misc.c @ 452efba6
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 2582cfa0 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sysemu.h" |
26 | 2582cfa0 | Blue Swirl | #include "sysbus.h" |
27 | 87ecb68b | pbrook | |
28 | 3475187d | bellard | /* debug misc */
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29 | 3475187d | bellard | //#define DEBUG_MISC
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30 | 3475187d | bellard | |
31 | 3475187d | bellard | /*
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32 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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33 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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34 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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35 | 3475187d | bellard | *
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36 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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37 | 3475187d | bellard | */
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38 | 3475187d | bellard | |
39 | 3475187d | bellard | #ifdef DEBUG_MISC
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40 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...) \
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41 | 001faf32 | Blue Swirl | do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0) |
42 | 3475187d | bellard | #else
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43 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...)
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44 | 3475187d | bellard | #endif
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45 | 3475187d | bellard | |
46 | 3475187d | bellard | typedef struct MiscState { |
47 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
48 | d537cf6c | pbrook | qemu_irq irq; |
49 | d37adb09 | Blue Swirl | uint32_t dummy; |
50 | 3475187d | bellard | uint8_t config; |
51 | 3475187d | bellard | uint8_t aux1, aux2; |
52 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
53 | d37adb09 | Blue Swirl | uint8_t sysctrl; |
54 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
55 | 2be17ebd | blueswir1 | qemu_irq fdc_tc; |
56 | 3475187d | bellard | } MiscState; |
57 | 3475187d | bellard | |
58 | 2582cfa0 | Blue Swirl | typedef struct APCState { |
59 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
60 | 2582cfa0 | Blue Swirl | qemu_irq cpu_halt; |
61 | 2582cfa0 | Blue Swirl | } APCState; |
62 | 2582cfa0 | Blue Swirl | |
63 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
64 | a8f48dcc | blueswir1 | #define SYSCTRL_SIZE 4 |
65 | 3475187d | bellard | |
66 | 2be17ebd | blueswir1 | #define AUX1_TC 0x02 |
67 | 2be17ebd | blueswir1 | |
68 | 7debeb82 | blueswir1 | #define AUX2_PWROFF 0x01 |
69 | 7debeb82 | blueswir1 | #define AUX2_PWRINTCLR 0x02 |
70 | 7debeb82 | blueswir1 | #define AUX2_PWRFAIL 0x20 |
71 | 7debeb82 | blueswir1 | |
72 | 7debeb82 | blueswir1 | #define CFG_PWRINTEN 0x08 |
73 | 7debeb82 | blueswir1 | |
74 | 7debeb82 | blueswir1 | #define SYS_RESET 0x01 |
75 | 7debeb82 | blueswir1 | #define SYS_RESETSTAT 0x02 |
76 | 7debeb82 | blueswir1 | |
77 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
78 | 3475187d | bellard | { |
79 | 3475187d | bellard | MiscState *s = opaque; |
80 | 3475187d | bellard | |
81 | 7debeb82 | blueswir1 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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82 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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83 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
84 | 3475187d | bellard | } else {
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85 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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86 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
87 | 3475187d | bellard | } |
88 | 3475187d | bellard | } |
89 | 3475187d | bellard | |
90 | 1795057a | Blue Swirl | static void slavio_misc_reset(DeviceState *d) |
91 | 3475187d | bellard | { |
92 | 1795057a | Blue Swirl | MiscState *s = container_of(d, MiscState, busdev.qdev); |
93 | 3475187d | bellard | |
94 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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95 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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96 | 3475187d | bellard | } |
97 | 3475187d | bellard | |
98 | b2b6f6ec | Blue Swirl | static void slavio_set_power_fail(void *opaque, int irq, int power_failing) |
99 | 3475187d | bellard | { |
100 | 3475187d | bellard | MiscState *s = opaque; |
101 | 3475187d | bellard | |
102 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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103 | 7debeb82 | blueswir1 | if (power_failing && (s->config & CFG_PWRINTEN)) {
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104 | 7debeb82 | blueswir1 | s->aux2 |= AUX2_PWRFAIL; |
105 | 3475187d | bellard | } else {
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106 | 7debeb82 | blueswir1 | s->aux2 &= ~AUX2_PWRFAIL; |
107 | 3475187d | bellard | } |
108 | 3475187d | bellard | slavio_misc_update_irq(s); |
109 | 3475187d | bellard | } |
110 | 3475187d | bellard | |
111 | c227f099 | Anthony Liguori | static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
112 | a8f48dcc | blueswir1 | uint32_t val) |
113 | a8f48dcc | blueswir1 | { |
114 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
115 | a8f48dcc | blueswir1 | |
116 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
117 | a8f48dcc | blueswir1 | s->config = val & 0xff;
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118 | a8f48dcc | blueswir1 | slavio_misc_update_irq(s); |
119 | a8f48dcc | blueswir1 | } |
120 | a8f48dcc | blueswir1 | |
121 | c227f099 | Anthony Liguori | static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
122 | a8f48dcc | blueswir1 | { |
123 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
124 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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125 | a8f48dcc | blueswir1 | |
126 | a8f48dcc | blueswir1 | ret = s->config; |
127 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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128 | a8f48dcc | blueswir1 | return ret;
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129 | a8f48dcc | blueswir1 | } |
130 | a8f48dcc | blueswir1 | |
131 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = { |
132 | a8f48dcc | blueswir1 | slavio_cfg_mem_readb, |
133 | a8f48dcc | blueswir1 | NULL,
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134 | a8f48dcc | blueswir1 | NULL,
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135 | a8f48dcc | blueswir1 | }; |
136 | a8f48dcc | blueswir1 | |
137 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = { |
138 | a8f48dcc | blueswir1 | slavio_cfg_mem_writeb, |
139 | a8f48dcc | blueswir1 | NULL,
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140 | a8f48dcc | blueswir1 | NULL,
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141 | a8f48dcc | blueswir1 | }; |
142 | a8f48dcc | blueswir1 | |
143 | c227f099 | Anthony Liguori | static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
144 | bfa30a38 | blueswir1 | uint32_t val) |
145 | 3475187d | bellard | { |
146 | 3475187d | bellard | MiscState *s = opaque; |
147 | 3475187d | bellard | |
148 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
149 | a8f48dcc | blueswir1 | s->diag = val & 0xff;
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150 | 3475187d | bellard | } |
151 | 3475187d | bellard | |
152 | c227f099 | Anthony Liguori | static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
153 | 3475187d | bellard | { |
154 | 3475187d | bellard | MiscState *s = opaque; |
155 | 3475187d | bellard | uint32_t ret = 0;
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156 | 3475187d | bellard | |
157 | a8f48dcc | blueswir1 | ret = s->diag; |
158 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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159 | a8f48dcc | blueswir1 | return ret;
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160 | a8f48dcc | blueswir1 | } |
161 | a8f48dcc | blueswir1 | |
162 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = { |
163 | a8f48dcc | blueswir1 | slavio_diag_mem_readb, |
164 | a8f48dcc | blueswir1 | NULL,
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165 | a8f48dcc | blueswir1 | NULL,
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166 | a8f48dcc | blueswir1 | }; |
167 | a8f48dcc | blueswir1 | |
168 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = { |
169 | a8f48dcc | blueswir1 | slavio_diag_mem_writeb, |
170 | a8f48dcc | blueswir1 | NULL,
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171 | a8f48dcc | blueswir1 | NULL,
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172 | a8f48dcc | blueswir1 | }; |
173 | a8f48dcc | blueswir1 | |
174 | c227f099 | Anthony Liguori | static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, |
175 | a8f48dcc | blueswir1 | uint32_t val) |
176 | a8f48dcc | blueswir1 | { |
177 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
178 | a8f48dcc | blueswir1 | |
179 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
180 | a8f48dcc | blueswir1 | s->mctrl = val & 0xff;
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181 | a8f48dcc | blueswir1 | } |
182 | a8f48dcc | blueswir1 | |
183 | c227f099 | Anthony Liguori | static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) |
184 | a8f48dcc | blueswir1 | { |
185 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
186 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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187 | a8f48dcc | blueswir1 | |
188 | a8f48dcc | blueswir1 | ret = s->mctrl; |
189 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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190 | 3475187d | bellard | return ret;
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191 | 3475187d | bellard | } |
192 | 3475187d | bellard | |
193 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = { |
194 | a8f48dcc | blueswir1 | slavio_mdm_mem_readb, |
195 | 7c560456 | blueswir1 | NULL,
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196 | 7c560456 | blueswir1 | NULL,
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197 | 3475187d | bellard | }; |
198 | 3475187d | bellard | |
199 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = { |
200 | a8f48dcc | blueswir1 | slavio_mdm_mem_writeb, |
201 | 7c560456 | blueswir1 | NULL,
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202 | 7c560456 | blueswir1 | NULL,
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203 | 3475187d | bellard | }; |
204 | 3475187d | bellard | |
205 | c227f099 | Anthony Liguori | static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
206 | 0019ad53 | blueswir1 | uint32_t val) |
207 | 0019ad53 | blueswir1 | { |
208 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
209 | 0019ad53 | blueswir1 | |
210 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
211 | 2be17ebd | blueswir1 | if (val & AUX1_TC) {
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212 | 2be17ebd | blueswir1 | // Send a pulse to floppy terminal count line
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213 | 2be17ebd | blueswir1 | if (s->fdc_tc) {
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214 | 2be17ebd | blueswir1 | qemu_irq_raise(s->fdc_tc); |
215 | 2be17ebd | blueswir1 | qemu_irq_lower(s->fdc_tc); |
216 | 2be17ebd | blueswir1 | } |
217 | 2be17ebd | blueswir1 | val &= ~AUX1_TC; |
218 | 2be17ebd | blueswir1 | } |
219 | 0019ad53 | blueswir1 | s->aux1 = val & 0xff;
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220 | 0019ad53 | blueswir1 | } |
221 | 0019ad53 | blueswir1 | |
222 | c227f099 | Anthony Liguori | static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
223 | 0019ad53 | blueswir1 | { |
224 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
225 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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226 | 0019ad53 | blueswir1 | |
227 | 0019ad53 | blueswir1 | ret = s->aux1; |
228 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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229 | 0019ad53 | blueswir1 | |
230 | 0019ad53 | blueswir1 | return ret;
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231 | 0019ad53 | blueswir1 | } |
232 | 0019ad53 | blueswir1 | |
233 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = { |
234 | 0019ad53 | blueswir1 | slavio_aux1_mem_readb, |
235 | 0019ad53 | blueswir1 | NULL,
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236 | 0019ad53 | blueswir1 | NULL,
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237 | 0019ad53 | blueswir1 | }; |
238 | 0019ad53 | blueswir1 | |
239 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = { |
240 | 0019ad53 | blueswir1 | slavio_aux1_mem_writeb, |
241 | 0019ad53 | blueswir1 | NULL,
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242 | 0019ad53 | blueswir1 | NULL,
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243 | 0019ad53 | blueswir1 | }; |
244 | 0019ad53 | blueswir1 | |
245 | c227f099 | Anthony Liguori | static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
246 | 0019ad53 | blueswir1 | uint32_t val) |
247 | 0019ad53 | blueswir1 | { |
248 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
249 | 0019ad53 | blueswir1 | |
250 | 0019ad53 | blueswir1 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
251 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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252 | 0019ad53 | blueswir1 | val |= s->aux2 & AUX2_PWRFAIL; |
253 | 0019ad53 | blueswir1 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
254 | 0019ad53 | blueswir1 | val &= AUX2_PWROFF; |
255 | 0019ad53 | blueswir1 | s->aux2 = val; |
256 | 0019ad53 | blueswir1 | if (val & AUX2_PWROFF)
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257 | 0019ad53 | blueswir1 | qemu_system_shutdown_request(); |
258 | 0019ad53 | blueswir1 | slavio_misc_update_irq(s); |
259 | 0019ad53 | blueswir1 | } |
260 | 0019ad53 | blueswir1 | |
261 | c227f099 | Anthony Liguori | static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
262 | 0019ad53 | blueswir1 | { |
263 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
264 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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265 | 0019ad53 | blueswir1 | |
266 | 0019ad53 | blueswir1 | ret = s->aux2; |
267 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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268 | 0019ad53 | blueswir1 | |
269 | 0019ad53 | blueswir1 | return ret;
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270 | 0019ad53 | blueswir1 | } |
271 | 0019ad53 | blueswir1 | |
272 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = { |
273 | 0019ad53 | blueswir1 | slavio_aux2_mem_readb, |
274 | 0019ad53 | blueswir1 | NULL,
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275 | 0019ad53 | blueswir1 | NULL,
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276 | 0019ad53 | blueswir1 | }; |
277 | 0019ad53 | blueswir1 | |
278 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = { |
279 | 0019ad53 | blueswir1 | slavio_aux2_mem_writeb, |
280 | 0019ad53 | blueswir1 | NULL,
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281 | 0019ad53 | blueswir1 | NULL,
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282 | 0019ad53 | blueswir1 | }; |
283 | 0019ad53 | blueswir1 | |
284 | c227f099 | Anthony Liguori | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
285 | 0019ad53 | blueswir1 | { |
286 | 2582cfa0 | Blue Swirl | APCState *s = opaque; |
287 | 0019ad53 | blueswir1 | |
288 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
289 | 6d0c293d | blueswir1 | qemu_irq_raise(s->cpu_halt); |
290 | 0019ad53 | blueswir1 | } |
291 | 0019ad53 | blueswir1 | |
292 | c227f099 | Anthony Liguori | static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
293 | 0019ad53 | blueswir1 | { |
294 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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295 | 0019ad53 | blueswir1 | |
296 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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297 | 0019ad53 | blueswir1 | return ret;
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298 | 0019ad53 | blueswir1 | } |
299 | 0019ad53 | blueswir1 | |
300 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apc_mem_read[3] = { |
301 | 0019ad53 | blueswir1 | apc_mem_readb, |
302 | 0019ad53 | blueswir1 | NULL,
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303 | 0019ad53 | blueswir1 | NULL,
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304 | 0019ad53 | blueswir1 | }; |
305 | 0019ad53 | blueswir1 | |
306 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apc_mem_write[3] = { |
307 | 0019ad53 | blueswir1 | apc_mem_writeb, |
308 | 0019ad53 | blueswir1 | NULL,
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309 | 0019ad53 | blueswir1 | NULL,
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310 | 0019ad53 | blueswir1 | }; |
311 | 0019ad53 | blueswir1 | |
312 | c227f099 | Anthony Liguori | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
313 | bfa30a38 | blueswir1 | { |
314 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
315 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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316 | bfa30a38 | blueswir1 | |
317 | a8f48dcc | blueswir1 | switch (addr) {
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318 | bfa30a38 | blueswir1 | case 0: |
319 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
320 | bfa30a38 | blueswir1 | break;
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321 | bfa30a38 | blueswir1 | default:
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322 | bfa30a38 | blueswir1 | break;
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323 | bfa30a38 | blueswir1 | } |
324 | 5626b017 | blueswir1 | MISC_DPRINTF("Read system control %08x\n", ret);
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325 | bfa30a38 | blueswir1 | return ret;
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326 | bfa30a38 | blueswir1 | } |
327 | bfa30a38 | blueswir1 | |
328 | c227f099 | Anthony Liguori | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
329 | bfa30a38 | blueswir1 | uint32_t val) |
330 | bfa30a38 | blueswir1 | { |
331 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
332 | bfa30a38 | blueswir1 | |
333 | 5626b017 | blueswir1 | MISC_DPRINTF("Write system control %08x\n", val);
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334 | a8f48dcc | blueswir1 | switch (addr) {
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335 | bfa30a38 | blueswir1 | case 0: |
336 | 7debeb82 | blueswir1 | if (val & SYS_RESET) {
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337 | 7debeb82 | blueswir1 | s->sysctrl = SYS_RESETSTAT; |
338 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
339 | bfa30a38 | blueswir1 | } |
340 | bfa30a38 | blueswir1 | break;
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341 | bfa30a38 | blueswir1 | default:
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342 | bfa30a38 | blueswir1 | break;
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343 | bfa30a38 | blueswir1 | } |
344 | bfa30a38 | blueswir1 | } |
345 | bfa30a38 | blueswir1 | |
346 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = { |
347 | 7c560456 | blueswir1 | NULL,
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348 | 7c560456 | blueswir1 | NULL,
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349 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
350 | bfa30a38 | blueswir1 | }; |
351 | bfa30a38 | blueswir1 | |
352 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = { |
353 | 7c560456 | blueswir1 | NULL,
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354 | 7c560456 | blueswir1 | NULL,
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355 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
356 | bfa30a38 | blueswir1 | }; |
357 | bfa30a38 | blueswir1 | |
358 | c227f099 | Anthony Liguori | static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
359 | 6a3b9cc9 | blueswir1 | { |
360 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
361 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
362 | 6a3b9cc9 | blueswir1 | |
363 | a8f48dcc | blueswir1 | switch (addr) {
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364 | 6a3b9cc9 | blueswir1 | case 0: |
365 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
366 | 6a3b9cc9 | blueswir1 | break;
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367 | 6a3b9cc9 | blueswir1 | default:
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368 | 6a3b9cc9 | blueswir1 | break;
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369 | 6a3b9cc9 | blueswir1 | } |
370 | 5626b017 | blueswir1 | MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
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371 | 6a3b9cc9 | blueswir1 | return ret;
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372 | 6a3b9cc9 | blueswir1 | } |
373 | 6a3b9cc9 | blueswir1 | |
374 | c227f099 | Anthony Liguori | static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
375 | 6a3b9cc9 | blueswir1 | uint32_t val) |
376 | 6a3b9cc9 | blueswir1 | { |
377 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
378 | 6a3b9cc9 | blueswir1 | |
379 | 5626b017 | blueswir1 | MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff); |
380 | a8f48dcc | blueswir1 | switch (addr) {
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381 | 6a3b9cc9 | blueswir1 | case 0: |
382 | d5296cb5 | blueswir1 | s->leds = val; |
383 | 6a3b9cc9 | blueswir1 | break;
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384 | 6a3b9cc9 | blueswir1 | default:
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385 | 6a3b9cc9 | blueswir1 | break;
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386 | 6a3b9cc9 | blueswir1 | } |
387 | 6a3b9cc9 | blueswir1 | } |
388 | 6a3b9cc9 | blueswir1 | |
389 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_led_mem_read[3] = { |
390 | 7c560456 | blueswir1 | NULL,
|
391 | 7c560456 | blueswir1 | slavio_led_mem_readw, |
392 | 7c560456 | blueswir1 | NULL,
|
393 | 6a3b9cc9 | blueswir1 | }; |
394 | 6a3b9cc9 | blueswir1 | |
395 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = { |
396 | 7c560456 | blueswir1 | NULL,
|
397 | 7c560456 | blueswir1 | slavio_led_mem_writew, |
398 | 7c560456 | blueswir1 | NULL,
|
399 | 6a3b9cc9 | blueswir1 | }; |
400 | 6a3b9cc9 | blueswir1 | |
401 | d37adb09 | Blue Swirl | static const VMStateDescription vmstate_misc = { |
402 | d37adb09 | Blue Swirl | .name ="slavio_misc",
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403 | d37adb09 | Blue Swirl | .version_id = 1,
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404 | d37adb09 | Blue Swirl | .minimum_version_id = 1,
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405 | d37adb09 | Blue Swirl | .minimum_version_id_old = 1,
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406 | d37adb09 | Blue Swirl | .fields = (VMStateField []) { |
407 | d37adb09 | Blue Swirl | VMSTATE_UINT32(dummy, MiscState), |
408 | d37adb09 | Blue Swirl | VMSTATE_UINT8(config, MiscState), |
409 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux1, MiscState), |
410 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux2, MiscState), |
411 | d37adb09 | Blue Swirl | VMSTATE_UINT8(diag, MiscState), |
412 | d37adb09 | Blue Swirl | VMSTATE_UINT8(mctrl, MiscState), |
413 | d37adb09 | Blue Swirl | VMSTATE_UINT8(sysctrl, MiscState), |
414 | d37adb09 | Blue Swirl | VMSTATE_END_OF_LIST() |
415 | d37adb09 | Blue Swirl | } |
416 | d37adb09 | Blue Swirl | }; |
417 | 3475187d | bellard | |
418 | 81a322d4 | Gerd Hoffmann | static int apc_init1(SysBusDevice *dev) |
419 | 2582cfa0 | Blue Swirl | { |
420 | 2582cfa0 | Blue Swirl | APCState *s = FROM_SYSBUS(APCState, dev); |
421 | 2582cfa0 | Blue Swirl | int io;
|
422 | 3475187d | bellard | |
423 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_halt); |
424 | 2582cfa0 | Blue Swirl | |
425 | 2582cfa0 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
426 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); |
427 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
428 | 81a322d4 | Gerd Hoffmann | return 0; |
429 | 2582cfa0 | Blue Swirl | } |
430 | 2582cfa0 | Blue Swirl | |
431 | 81a322d4 | Gerd Hoffmann | static int slavio_misc_init1(SysBusDevice *dev) |
432 | 2582cfa0 | Blue Swirl | { |
433 | 2582cfa0 | Blue Swirl | MiscState *s = FROM_SYSBUS(MiscState, dev); |
434 | 2582cfa0 | Blue Swirl | int io;
|
435 | 2582cfa0 | Blue Swirl | |
436 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
437 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->fdc_tc); |
438 | 2582cfa0 | Blue Swirl | |
439 | 2582cfa0 | Blue Swirl | /* 8 bit registers */
|
440 | 2582cfa0 | Blue Swirl | /* Slavio control */
|
441 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_cfg_mem_read, |
442 | 2582cfa0 | Blue Swirl | slavio_cfg_mem_write, s); |
443 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
444 | 2582cfa0 | Blue Swirl | |
445 | 2582cfa0 | Blue Swirl | /* Diagnostics */
|
446 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_diag_mem_read, |
447 | 2582cfa0 | Blue Swirl | slavio_diag_mem_write, s); |
448 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
449 | 2582cfa0 | Blue Swirl | |
450 | 2582cfa0 | Blue Swirl | /* Modem control */
|
451 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_mdm_mem_read, |
452 | 2582cfa0 | Blue Swirl | slavio_mdm_mem_write, s); |
453 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
454 | 2582cfa0 | Blue Swirl | |
455 | 2582cfa0 | Blue Swirl | /* 16 bit registers */
|
456 | 2582cfa0 | Blue Swirl | /* ss600mp diag LEDs */
|
457 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_led_mem_read, |
458 | 2582cfa0 | Blue Swirl | slavio_led_mem_write, s); |
459 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
460 | 2582cfa0 | Blue Swirl | |
461 | 2582cfa0 | Blue Swirl | /* 32 bit registers */
|
462 | 2582cfa0 | Blue Swirl | /* System control */
|
463 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_sysctrl_mem_read, |
464 | 2582cfa0 | Blue Swirl | slavio_sysctrl_mem_write, s); |
465 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, SYSCTRL_SIZE, io); |
466 | 2582cfa0 | Blue Swirl | |
467 | 2582cfa0 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
468 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux1_mem_read, |
469 | 2582cfa0 | Blue Swirl | slavio_aux1_mem_write, s); |
470 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
471 | 2582cfa0 | Blue Swirl | |
472 | 2582cfa0 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
473 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux2_mem_read, |
474 | 2582cfa0 | Blue Swirl | slavio_aux2_mem_write, s); |
475 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
476 | 2582cfa0 | Blue Swirl | |
477 | b2b6f6ec | Blue Swirl | qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
|
478 | b2b6f6ec | Blue Swirl | |
479 | 81a322d4 | Gerd Hoffmann | return 0; |
480 | 2582cfa0 | Blue Swirl | } |
481 | 0019ad53 | blueswir1 | |
482 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo slavio_misc_info = {
|
483 | 2582cfa0 | Blue Swirl | .init = slavio_misc_init1, |
484 | 2582cfa0 | Blue Swirl | .qdev.name = "slavio_misc",
|
485 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
486 | 1795057a | Blue Swirl | .qdev.vmsd = &vmstate_misc, |
487 | 1795057a | Blue Swirl | .qdev.reset = slavio_misc_reset, |
488 | 2582cfa0 | Blue Swirl | }; |
489 | 2582cfa0 | Blue Swirl | |
490 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo apc_info = {
|
491 | 2582cfa0 | Blue Swirl | .init = apc_init1, |
492 | 2582cfa0 | Blue Swirl | .qdev.name = "apc",
|
493 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
494 | 2582cfa0 | Blue Swirl | }; |
495 | 2582cfa0 | Blue Swirl | |
496 | 2582cfa0 | Blue Swirl | static void slavio_misc_register_devices(void) |
497 | 2582cfa0 | Blue Swirl | { |
498 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&slavio_misc_info); |
499 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&apc_info); |
500 | 3475187d | bellard | } |
501 | 2582cfa0 | Blue Swirl | |
502 | 2582cfa0 | Blue Swirl | device_init(slavio_misc_register_devices) |