Revision 45c7b743
| b/target-sparc/translate.c | ||
|---|---|---|
| 63 | 63 |
static TCGv_i32 cpu_tmp32; |
| 64 | 64 |
static TCGv_i64 cpu_tmp64; |
| 65 | 65 |
/* Floating point registers */ |
| 66 |
static TCGv_i32 cpu__fpr[TARGET_FPREGS];
|
|
| 66 |
static TCGv_i32 cpu_fpr[TARGET_FPREGS]; |
|
| 67 | 67 |
|
| 68 | 68 |
static target_ulong gen_opc_npc[OPC_BUF_SIZE]; |
| 69 | 69 |
static target_ulong gen_opc_jump_pc[2]; |
| ... | ... | |
| 126 | 126 |
/* floating point registers moves */ |
| 127 | 127 |
static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) |
| 128 | 128 |
{
|
| 129 |
return cpu__fpr[src];
|
|
| 129 |
return cpu_fpr[src]; |
|
| 130 | 130 |
} |
| 131 | 131 |
|
| 132 | 132 |
static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) |
| 133 | 133 |
{
|
| 134 |
tcg_gen_mov_i32(cpu__fpr[dst], v);
|
|
| 134 |
tcg_gen_mov_i32(cpu_fpr[dst], v); |
|
| 135 | 135 |
gen_update_fprs_dirty(dst); |
| 136 | 136 |
} |
| 137 | 137 |
|
| ... | ... | |
| 146 | 146 |
src = DFPREG(src); |
| 147 | 147 |
|
| 148 | 148 |
#if TCG_TARGET_REG_BITS == 32 |
| 149 |
tcg_gen_mov_i32(TCGV_HIGH(ret), cpu__fpr[src]);
|
|
| 150 |
tcg_gen_mov_i32(TCGV_LOW(ret), cpu__fpr[src + 1]);
|
|
| 149 |
tcg_gen_mov_i32(TCGV_HIGH(ret), cpu_fpr[src]); |
|
| 150 |
tcg_gen_mov_i32(TCGV_LOW(ret), cpu_fpr[src + 1]); |
|
| 151 | 151 |
#else |
| 152 | 152 |
{
|
| 153 | 153 |
TCGv_i64 t = tcg_temp_new_i64(); |
| 154 |
tcg_gen_extu_i32_i64(ret, cpu__fpr[src]);
|
|
| 155 |
tcg_gen_extu_i32_i64(t, cpu__fpr[src + 1]);
|
|
| 154 |
tcg_gen_extu_i32_i64(ret, cpu_fpr[src]); |
|
| 155 |
tcg_gen_extu_i32_i64(t, cpu_fpr[src + 1]); |
|
| 156 | 156 |
tcg_gen_shli_i64(ret, ret, 32); |
| 157 | 157 |
tcg_gen_or_i64(ret, ret, t); |
| 158 | 158 |
tcg_temp_free_i64(t); |
| ... | ... | |
| 173 | 173 |
tcg_gen_mov_i32(cpu__fpu[dst], TCGV_HIGH(v)); |
| 174 | 174 |
tcg_gen_mov_i32(cpu__fpu[dst + 1], TCGV_LOW(v)); |
| 175 | 175 |
#else |
| 176 |
tcg_gen_trunc_i64_i32(cpu__fpr[dst + 1], v);
|
|
| 176 |
tcg_gen_trunc_i64_i32(cpu_fpr[dst + 1], v); |
|
| 177 | 177 |
tcg_gen_shri_i64(v, v, 32); |
| 178 |
tcg_gen_trunc_i64_i32(cpu__fpr[dst], v);
|
|
| 178 |
tcg_gen_trunc_i64_i32(cpu_fpr[dst], v); |
|
| 179 | 179 |
#endif |
| 180 | 180 |
|
| 181 | 181 |
gen_update_fprs_dirty(dst); |
| ... | ... | |
| 188 | 188 |
|
| 189 | 189 |
static void gen_op_load_fpr_QT0(unsigned int src) |
| 190 | 190 |
{
|
| 191 |
tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 191 |
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 192 | 192 |
offsetof(CPU_QuadU, l.upmost)); |
| 193 |
tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 193 |
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 194 | 194 |
offsetof(CPU_QuadU, l.upper)); |
| 195 |
tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 195 |
tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 196 | 196 |
offsetof(CPU_QuadU, l.lower)); |
| 197 |
tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 197 |
tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 198 | 198 |
offsetof(CPU_QuadU, l.lowest)); |
| 199 | 199 |
} |
| 200 | 200 |
|
| 201 | 201 |
static void gen_op_load_fpr_QT1(unsigned int src) |
| 202 | 202 |
{
|
| 203 |
tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
|
|
| 203 |
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
|
| 204 | 204 |
offsetof(CPU_QuadU, l.upmost)); |
| 205 |
tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
|
|
| 205 |
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) + |
|
| 206 | 206 |
offsetof(CPU_QuadU, l.upper)); |
| 207 |
tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
|
|
| 207 |
tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) + |
|
| 208 | 208 |
offsetof(CPU_QuadU, l.lower)); |
| 209 |
tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
|
|
| 209 |
tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) + |
|
| 210 | 210 |
offsetof(CPU_QuadU, l.lowest)); |
| 211 | 211 |
} |
| 212 | 212 |
|
| 213 | 213 |
static void gen_op_store_QT0_fpr(unsigned int dst) |
| 214 | 214 |
{
|
| 215 |
tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 215 |
tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 216 | 216 |
offsetof(CPU_QuadU, l.upmost)); |
| 217 |
tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 217 |
tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 218 | 218 |
offsetof(CPU_QuadU, l.upper)); |
| 219 |
tcg_gen_ld_i32(cpu__fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 219 |
tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 220 | 220 |
offsetof(CPU_QuadU, l.lower)); |
| 221 |
tcg_gen_ld_i32(cpu__fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
|
| 221 |
tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) + |
|
| 222 | 222 |
offsetof(CPU_QuadU, l.lowest)); |
| 223 | 223 |
} |
| 224 | 224 |
|
| ... | ... | |
| 228 | 228 |
rd = QFPREG(rd); |
| 229 | 229 |
rs = QFPREG(rs); |
| 230 | 230 |
|
| 231 |
tcg_gen_mov_i32(cpu__fpr[rd], cpu__fpr[rs]);
|
|
| 232 |
tcg_gen_mov_i32(cpu__fpr[rd + 1], cpu__fpr[rs + 1]);
|
|
| 233 |
tcg_gen_mov_i32(cpu__fpr[rd + 2], cpu__fpr[rs + 2]);
|
|
| 234 |
tcg_gen_mov_i32(cpu__fpr[rd + 3], cpu__fpr[rs + 3]);
|
|
| 231 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs]);
|
|
| 232 |
tcg_gen_mov_i32(cpu_fpr[rd + 1], cpu_fpr[rs + 1]);
|
|
| 233 |
tcg_gen_mov_i32(cpu_fpr[rd + 2], cpu_fpr[rs + 2]);
|
|
| 234 |
tcg_gen_mov_i32(cpu_fpr[rd + 3], cpu_fpr[rs + 3]);
|
|
| 235 | 235 |
gen_update_fprs_dirty(rd); |
| 236 | 236 |
} |
| 237 | 237 |
#endif |
| ... | ... | |
| 5251 | 5251 |
offsetof(CPUState, gregs[i]), |
| 5252 | 5252 |
gregnames[i]); |
| 5253 | 5253 |
for (i = 0; i < TARGET_FPREGS; i++) |
| 5254 |
cpu__fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 5255 |
offsetof(CPUState, fpr[i]),
|
|
| 5256 |
fregnames[i]);
|
|
| 5254 |
cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
|
| 5255 |
offsetof(CPUState, fpr[i]), |
|
| 5256 |
fregnames[i]); |
|
| 5257 | 5257 |
|
| 5258 | 5258 |
/* register helpers */ |
| 5259 | 5259 |
|
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