Revision 45d827d2 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 38 | 38 |
#define GDBSTUB_SINGLE_STEP 0x4 |
| 39 | 39 |
|
| 40 | 40 |
/* Include definitions for instructions classes and implementations flags */ |
| 41 |
//#define DO_SINGLE_STEP
|
|
| 41 |
#define DO_SINGLE_STEP |
|
| 42 | 42 |
//#define PPC_DEBUG_DISAS |
| 43 | 43 |
//#define DO_PPC_STATISTICS |
| 44 | 44 |
//#define OPTIMIZE_FPRF_UPDATE |
| ... | ... | |
| 71 | 71 |
static TCGv_i32 cpu_fpscr; |
| 72 | 72 |
static TCGv_i32 cpu_access_type; |
| 73 | 73 |
|
| 74 |
/* dyngen register indexes */ |
|
| 75 |
static TCGv cpu_T[1]; |
|
| 76 |
|
|
| 77 | 74 |
#include "gen-icount.h" |
| 78 | 75 |
|
| 79 | 76 |
void ppc_translate_init(void) |
| ... | ... | |
| 86 | 83 |
return; |
| 87 | 84 |
|
| 88 | 85 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
| 89 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
| 90 |
cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0"); |
|
| 91 |
#else |
|
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cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0"); |
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| 93 |
#endif |
|
| 94 | 86 |
|
| 95 | 87 |
p = cpu_reg_names; |
| 96 | 88 |
|
| ... | ... | |
| 3886 | 3878 |
/* mfspr */ |
| 3887 | 3879 |
static always_inline void gen_op_mfspr (DisasContext *ctx) |
| 3888 | 3880 |
{
|
| 3889 |
void (*read_cb)(void *opaque, int sprn); |
|
| 3881 |
void (*read_cb)(void *opaque, int gprn, int sprn);
|
|
| 3890 | 3882 |
uint32_t sprn = SPR(ctx->opcode); |
| 3891 | 3883 |
|
| 3892 | 3884 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 3899 | 3891 |
read_cb = ctx->spr_cb[sprn].uea_read; |
| 3900 | 3892 |
if (likely(read_cb != NULL)) {
|
| 3901 | 3893 |
if (likely(read_cb != SPR_NOACCESS)) {
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| 3902 |
(*read_cb)(ctx, sprn); |
|
| 3903 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
|
| 3894 |
(*read_cb)(ctx, rD(ctx->opcode), sprn); |
|
| 3904 | 3895 |
} else {
|
| 3905 | 3896 |
/* Privilege exception */ |
| 3906 | 3897 |
/* This is a hack to avoid warnings when running Linux: |
| ... | ... | |
| 3972 | 3963 |
GEN_EXCP_PRIVREG(ctx); |
| 3973 | 3964 |
return; |
| 3974 | 3965 |
} |
| 3975 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
| 3976 | 3966 |
if (ctx->opcode & 0x00010000) {
|
| 3977 | 3967 |
/* Special form that does not need any synchronisation */ |
| 3978 | 3968 |
TCGv t0 = tcg_temp_new(); |
| ... | ... | |
| 4004 | 3994 |
GEN_EXCP_PRIVREG(ctx); |
| 4005 | 3995 |
return; |
| 4006 | 3996 |
} |
| 4007 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
| 4008 | 3997 |
if (ctx->opcode & 0x00010000) {
|
| 4009 | 3998 |
/* Special form that does not need any synchronisation */ |
| 4010 | 3999 |
TCGv t0 = tcg_temp_new(); |
| ... | ... | |
| 4041 | 4030 |
/* mtspr */ |
| 4042 | 4031 |
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
| 4043 | 4032 |
{
|
| 4044 |
void (*write_cb)(void *opaque, int sprn); |
|
| 4033 |
void (*write_cb)(void *opaque, int sprn, int gprn);
|
|
| 4045 | 4034 |
uint32_t sprn = SPR(ctx->opcode); |
| 4046 | 4035 |
|
| 4047 | 4036 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 4054 | 4043 |
write_cb = ctx->spr_cb[sprn].uea_write; |
| 4055 | 4044 |
if (likely(write_cb != NULL)) {
|
| 4056 | 4045 |
if (likely(write_cb != SPR_NOACCESS)) {
|
| 4057 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
| 4058 |
(*write_cb)(ctx, sprn); |
|
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(*write_cb)(ctx, sprn, rS(ctx->opcode)); |
|
| 4059 | 4047 |
} else {
|
| 4060 | 4048 |
/* Privilege exception */ |
| 4061 | 4049 |
if (loglevel != 0) {
|
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