Revision 45d827d2 target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 66 | 66 |
/* Generic callbacks: |
| 67 | 67 |
* do nothing but store/retrieve spr value |
| 68 | 68 |
*/ |
| 69 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
| 70 |
static void spr_read_generic (void *opaque, int sprn) |
|
| 71 |
{
|
|
| 72 |
gen_op_load_dump_spr(sprn); |
|
| 73 |
} |
|
| 74 |
|
|
| 75 |
static void spr_write_generic (void *opaque, int sprn) |
|
| 69 |
static void spr_read_generic (void *opaque, int gprn, int sprn) |
|
| 76 | 70 |
{
|
| 77 |
gen_op_store_dump_spr(sprn); |
|
| 78 |
} |
|
| 79 |
#else |
|
| 80 |
static void spr_read_generic (void *opaque, int sprn) |
|
| 81 |
{
|
|
| 82 |
gen_op_load_spr(sprn); |
|
| 71 |
gen_load_spr(cpu_gpr[gprn], sprn); |
|
| 72 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
| 73 |
{
|
|
| 74 |
TCGv t0 = tcg_const_i32(sprn); |
|
| 75 |
gen_helper_load_dump_spr(t0); |
|
| 76 |
tcg_temp_free_i32(t0); |
|
| 77 |
} |
|
| 78 |
#endif |
|
| 83 | 79 |
} |
| 84 | 80 |
|
| 85 |
static void spr_write_generic (void *opaque, int sprn) |
|
| 81 |
static void spr_write_generic (void *opaque, int sprn, int gprn)
|
|
| 86 | 82 |
{
|
| 87 |
gen_op_store_spr(sprn); |
|
| 88 |
} |
|
| 83 |
gen_store_spr(sprn, cpu_gpr[gprn]); |
|
| 84 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
| 85 |
{
|
|
| 86 |
TCGv t0 = tcg_const_i32(sprn); |
|
| 87 |
gen_helper_store_dump_spr(t0); |
|
| 88 |
tcg_temp_free_i32(t0); |
|
| 89 |
} |
|
| 89 | 90 |
#endif |
| 91 |
} |
|
| 90 | 92 |
|
| 91 | 93 |
#if !defined(CONFIG_USER_ONLY) |
| 92 |
static void spr_write_clear (void *opaque, int sprn) |
|
| 94 |
static void spr_write_clear (void *opaque, int sprn, int gprn)
|
|
| 93 | 95 |
{
|
| 94 |
gen_op_mask_spr(sprn); |
|
| 96 |
TCGv t0 = tcg_temp_new(); |
|
| 97 |
TCGv t1 = tcg_temp_new(); |
|
| 98 |
gen_load_spr(t0, sprn); |
|
| 99 |
tcg_gen_neg_tl(t1, cpu_gpr[gprn]); |
|
| 100 |
tcg_gen_and_tl(t0, t0, t1); |
|
| 101 |
gen_store_spr(sprn, t0); |
|
| 102 |
tcg_temp_free(t0); |
|
| 103 |
tcg_temp_free(t1); |
|
| 95 | 104 |
} |
| 96 | 105 |
#endif |
| 97 | 106 |
|
| 98 | 107 |
/* SPR common to all PowerPC */ |
| 99 | 108 |
/* XER */ |
| 100 |
static void spr_read_xer (void *opaque, int sprn) |
|
| 109 |
static void spr_read_xer (void *opaque, int gprn, int sprn)
|
|
| 101 | 110 |
{
|
| 102 |
tcg_gen_mov_tl(cpu_T[0], cpu_xer);
|
|
| 111 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
|
|
| 103 | 112 |
} |
| 104 | 113 |
|
| 105 |
static void spr_write_xer (void *opaque, int sprn) |
|
| 114 |
static void spr_write_xer (void *opaque, int sprn, int gprn)
|
|
| 106 | 115 |
{
|
| 107 |
tcg_gen_mov_tl(cpu_xer, cpu_T[0]);
|
|
| 116 |
tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
|
|
| 108 | 117 |
} |
| 109 | 118 |
|
| 110 | 119 |
/* LR */ |
| 111 |
static void spr_read_lr (void *opaque, int sprn) |
|
| 120 |
static void spr_read_lr (void *opaque, int gprn, int sprn)
|
|
| 112 | 121 |
{
|
| 113 |
tcg_gen_mov_tl(cpu_T[0], cpu_lr);
|
|
| 122 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
|
|
| 114 | 123 |
} |
| 115 | 124 |
|
| 116 |
static void spr_write_lr (void *opaque, int sprn) |
|
| 125 |
static void spr_write_lr (void *opaque, int sprn, int gprn)
|
|
| 117 | 126 |
{
|
| 118 |
tcg_gen_mov_tl(cpu_lr, cpu_T[0]);
|
|
| 127 |
tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
|
|
| 119 | 128 |
} |
| 120 | 129 |
|
| 121 | 130 |
/* CTR */ |
| 122 |
static void spr_read_ctr (void *opaque, int sprn) |
|
| 131 |
static void spr_read_ctr (void *opaque, int gprn, int sprn)
|
|
| 123 | 132 |
{
|
| 124 |
tcg_gen_mov_tl(cpu_T[0], cpu_ctr);
|
|
| 133 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
|
|
| 125 | 134 |
} |
| 126 | 135 |
|
| 127 |
static void spr_write_ctr (void *opaque, int sprn) |
|
| 136 |
static void spr_write_ctr (void *opaque, int sprn, int gprn)
|
|
| 128 | 137 |
{
|
| 129 |
tcg_gen_mov_tl(cpu_ctr, cpu_T[0]);
|
|
| 138 |
tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
|
|
| 130 | 139 |
} |
| 131 | 140 |
|
| 132 | 141 |
/* User read access to SPR */ |
| ... | ... | |
| 135 | 144 |
/* UPMCx */ |
| 136 | 145 |
/* USIA */ |
| 137 | 146 |
/* UDECR */ |
| 138 |
static void spr_read_ureg (void *opaque, int sprn) |
|
| 147 |
static void spr_read_ureg (void *opaque, int gprn, int sprn)
|
|
| 139 | 148 |
{
|
| 140 |
gen_op_load_spr(sprn + 0x10);
|
|
| 149 |
gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
|
|
| 141 | 150 |
} |
| 142 | 151 |
|
| 143 | 152 |
/* SPR common to all non-embedded PowerPC */ |
| 144 | 153 |
/* DECR */ |
| 145 | 154 |
#if !defined(CONFIG_USER_ONLY) |
| 146 |
static void spr_read_decr (void *opaque, int sprn) |
|
| 155 |
static void spr_read_decr (void *opaque, int gprn, int sprn)
|
|
| 147 | 156 |
{
|
| 148 |
gen_op_load_decr();
|
|
| 157 |
gen_helper_load_decr(cpu_gpr[gprn]);
|
|
| 149 | 158 |
} |
| 150 | 159 |
|
| 151 |
static void spr_write_decr (void *opaque, int sprn) |
|
| 160 |
static void spr_write_decr (void *opaque, int sprn, int gprn)
|
|
| 152 | 161 |
{
|
| 153 |
gen_op_store_decr();
|
|
| 162 |
gen_helper_store_decr(cpu_gpr[gprn]);
|
|
| 154 | 163 |
} |
| 155 | 164 |
#endif |
| 156 | 165 |
|
| 157 | 166 |
/* SPR common to all non-embedded PowerPC, except 601 */ |
| 158 | 167 |
/* Time base */ |
| 159 |
static void spr_read_tbl (void *opaque, int sprn) |
|
| 168 |
static void spr_read_tbl (void *opaque, int gprn, int sprn)
|
|
| 160 | 169 |
{
|
| 161 |
gen_op_load_tbl();
|
|
| 170 |
gen_helper_load_tbl(cpu_gpr[gprn]);
|
|
| 162 | 171 |
} |
| 163 | 172 |
|
| 164 |
static void spr_read_tbu (void *opaque, int sprn) |
|
| 173 |
static void spr_read_tbu (void *opaque, int gprn, int sprn)
|
|
| 165 | 174 |
{
|
| 166 |
gen_op_load_tbu();
|
|
| 175 |
gen_helper_load_tbu(cpu_gpr[gprn]);
|
|
| 167 | 176 |
} |
| 168 | 177 |
|
| 169 | 178 |
__attribute__ (( unused )) |
| 170 |
static void spr_read_atbl (void *opaque, int sprn) |
|
| 179 |
static void spr_read_atbl (void *opaque, int gprn, int sprn)
|
|
| 171 | 180 |
{
|
| 172 |
gen_op_load_atbl();
|
|
| 181 |
gen_helper_load_atbl(cpu_gpr[gprn]);
|
|
| 173 | 182 |
} |
| 174 | 183 |
|
| 175 | 184 |
__attribute__ (( unused )) |
| 176 |
static void spr_read_atbu (void *opaque, int sprn) |
|
| 185 |
static void spr_read_atbu (void *opaque, int gprn, int sprn)
|
|
| 177 | 186 |
{
|
| 178 |
gen_op_load_atbu();
|
|
| 187 |
gen_helper_load_atbu(cpu_gpr[gprn]);
|
|
| 179 | 188 |
} |
| 180 | 189 |
|
| 181 | 190 |
#if !defined(CONFIG_USER_ONLY) |
| 182 |
static void spr_write_tbl (void *opaque, int sprn) |
|
| 191 |
static void spr_write_tbl (void *opaque, int sprn, int gprn)
|
|
| 183 | 192 |
{
|
| 184 |
gen_op_store_tbl();
|
|
| 193 |
gen_helper_store_tbl(cpu_gpr[gprn]);
|
|
| 185 | 194 |
} |
| 186 | 195 |
|
| 187 |
static void spr_write_tbu (void *opaque, int sprn) |
|
| 196 |
static void spr_write_tbu (void *opaque, int sprn, int gprn)
|
|
| 188 | 197 |
{
|
| 189 |
gen_op_store_tbu();
|
|
| 198 |
gen_helper_store_tbu(cpu_gpr[gprn]);
|
|
| 190 | 199 |
} |
| 191 | 200 |
|
| 192 | 201 |
__attribute__ (( unused )) |
| 193 |
static void spr_write_atbl (void *opaque, int sprn) |
|
| 202 |
static void spr_write_atbl (void *opaque, int sprn, int gprn)
|
|
| 194 | 203 |
{
|
| 195 |
gen_op_store_atbl();
|
|
| 204 |
gen_helper_store_atbl(cpu_gpr[gprn]);
|
|
| 196 | 205 |
} |
| 197 | 206 |
|
| 198 | 207 |
__attribute__ (( unused )) |
| 199 |
static void spr_write_atbu (void *opaque, int sprn) |
|
| 208 |
static void spr_write_atbu (void *opaque, int sprn, int gprn)
|
|
| 200 | 209 |
{
|
| 201 |
gen_op_store_atbu();
|
|
| 210 |
gen_helper_store_atbu(cpu_gpr[gprn]);
|
|
| 202 | 211 |
} |
| 203 | 212 |
#endif |
| 204 | 213 |
|
| 205 | 214 |
#if !defined(CONFIG_USER_ONLY) |
| 206 | 215 |
/* IBAT0U...IBAT0U */ |
| 207 | 216 |
/* IBAT0L...IBAT7L */ |
| 208 |
static void spr_read_ibat (void *opaque, int sprn) |
|
| 217 |
static void spr_read_ibat (void *opaque, int gprn, int sprn)
|
|
| 209 | 218 |
{
|
| 210 |
gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
|
|
| 219 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
|
|
| 211 | 220 |
} |
| 212 | 221 |
|
| 213 |
static void spr_read_ibat_h (void *opaque, int sprn) |
|
| 222 |
static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
|
|
| 214 | 223 |
{
|
| 215 |
gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
|
|
| 224 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
|
|
| 216 | 225 |
} |
| 217 | 226 |
|
| 218 |
static void spr_write_ibatu (void *opaque, int sprn) |
|
| 227 |
static void spr_write_ibatu (void *opaque, int sprn, int gprn)
|
|
| 219 | 228 |
{
|
| 220 |
gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2); |
|
| 229 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
| 230 |
gen_helper_store_ibatu(t0, cpu_gpr[gprn]); |
|
| 231 |
tcg_temp_free_i32(t0); |
|
| 221 | 232 |
} |
| 222 | 233 |
|
| 223 |
static void spr_write_ibatu_h (void *opaque, int sprn) |
|
| 234 |
static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
|
|
| 224 | 235 |
{
|
| 225 |
gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2); |
|
| 236 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2); |
|
| 237 |
gen_helper_store_ibatu(t0, cpu_gpr[gprn]); |
|
| 238 |
tcg_temp_free_i32(t0); |
|
| 226 | 239 |
} |
| 227 | 240 |
|
| 228 |
static void spr_write_ibatl (void *opaque, int sprn) |
|
| 241 |
static void spr_write_ibatl (void *opaque, int sprn, int gprn)
|
|
| 229 | 242 |
{
|
| 230 |
gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2); |
|
| 243 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
|
| 244 |
gen_helper_store_ibatl(t0, cpu_gpr[gprn]); |
|
| 245 |
tcg_temp_free_i32(t0); |
|
| 231 | 246 |
} |
| 232 | 247 |
|
| 233 |
static void spr_write_ibatl_h (void *opaque, int sprn) |
|
| 248 |
static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
|
|
| 234 | 249 |
{
|
| 235 |
gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2); |
|
| 250 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2); |
|
| 251 |
gen_helper_store_ibatl(t0, cpu_gpr[gprn]); |
|
| 252 |
tcg_temp_free_i32(t0); |
|
| 236 | 253 |
} |
| 237 | 254 |
|
| 238 | 255 |
/* DBAT0U...DBAT7U */ |
| 239 | 256 |
/* DBAT0L...DBAT7L */ |
| 240 |
static void spr_read_dbat (void *opaque, int sprn) |
|
| 257 |
static void spr_read_dbat (void *opaque, int gprn, int sprn)
|
|
| 241 | 258 |
{
|
| 242 |
gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
|
|
| 259 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
|
|
| 243 | 260 |
} |
| 244 | 261 |
|
| 245 |
static void spr_read_dbat_h (void *opaque, int sprn) |
|
| 262 |
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
|
|
| 246 | 263 |
{
|
| 247 |
gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
|
|
| 264 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
|
|
| 248 | 265 |
} |
| 249 | 266 |
|
| 250 |
static void spr_write_dbatu (void *opaque, int sprn) |
|
| 267 |
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
|
|
| 251 | 268 |
{
|
| 252 |
gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2); |
|
| 269 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
|
| 270 |
gen_helper_store_dbatu(t0, cpu_gpr[gprn]); |
|
| 271 |
tcg_temp_free_i32(t0); |
|
| 253 | 272 |
} |
| 254 | 273 |
|
| 255 |
static void spr_write_dbatu_h (void *opaque, int sprn) |
|
| 274 |
static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
|
|
| 256 | 275 |
{
|
| 257 |
gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4); |
|
| 276 |
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
|
| 277 |
gen_helper_store_dbatu(t0, cpu_gpr[gprn]); |
|
| 278 |
tcg_temp_free_i32(t0); |
|
| 258 | 279 |
} |
| 259 | 280 |
|
| 260 |
static void spr_write_dbatl (void *opaque, int sprn) |
|
| 281 |
static void spr_write_dbatl (void *opaque, int sprn, int gprn)
|
|
| 261 | 282 |
{
|
| 262 |
gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2); |
|
| 283 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
|
| 284 |
gen_helper_store_dbatl(t0, cpu_gpr[gprn]); |
|
| 285 |
tcg_temp_free_i32(t0); |
|
| 263 | 286 |
} |
| 264 | 287 |
|
| 265 |
static void spr_write_dbatl_h (void *opaque, int sprn) |
|
| 288 |
static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
|
|
| 266 | 289 |
{
|
| 267 |
gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4); |
|
| 290 |
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
|
| 291 |
gen_helper_store_dbatl(t0, cpu_gpr[gprn]); |
|
| 292 |
tcg_temp_free_i32(t0); |
|
| 268 | 293 |
} |
| 269 | 294 |
|
| 270 | 295 |
/* SDR1 */ |
| 271 |
static void spr_read_sdr1 (void *opaque, int sprn) |
|
| 296 |
static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
|
|
| 272 | 297 |
{
|
| 273 |
gen_op_load_sdr1();
|
|
| 298 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
|
|
| 274 | 299 |
} |
| 275 | 300 |
|
| 276 |
static void spr_write_sdr1 (void *opaque, int sprn) |
|
| 301 |
static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
|
|
| 277 | 302 |
{
|
| 278 |
gen_op_store_sdr1();
|
|
| 303 |
gen_helper_store_sdr1(cpu_gpr[gprn]);
|
|
| 279 | 304 |
} |
| 280 | 305 |
|
| 281 | 306 |
/* 64 bits PowerPC specific SPRs */ |
| 282 | 307 |
/* ASR */ |
| 283 | 308 |
#if defined(TARGET_PPC64) |
| 284 |
static void spr_read_asr (void *opaque, int sprn) |
|
| 309 |
static void spr_read_asr (void *opaque, int gprn, int sprn)
|
|
| 285 | 310 |
{
|
| 286 |
gen_op_load_asr();
|
|
| 311 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
|
|
| 287 | 312 |
} |
| 288 | 313 |
|
| 289 |
static void spr_write_asr (void *opaque, int sprn) |
|
| 314 |
static void spr_write_asr (void *opaque, int sprn, int gprn)
|
|
| 290 | 315 |
{
|
| 291 |
gen_op_store_asr();
|
|
| 316 |
gen_helper_store_asr(cpu_gpr[gprn]);
|
|
| 292 | 317 |
} |
| 293 | 318 |
#endif |
| 294 | 319 |
#endif |
| 295 | 320 |
|
| 296 | 321 |
/* PowerPC 601 specific registers */ |
| 297 | 322 |
/* RTC */ |
| 298 |
static void spr_read_601_rtcl (void *opaque, int sprn) |
|
| 323 |
static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
|
|
| 299 | 324 |
{
|
| 300 |
gen_op_load_601_rtcl();
|
|
| 325 |
gen_helper_load_601_rtcl(cpu_gpr[gprn]);
|
|
| 301 | 326 |
} |
| 302 | 327 |
|
| 303 |
static void spr_read_601_rtcu (void *opaque, int sprn) |
|
| 328 |
static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
|
|
| 304 | 329 |
{
|
| 305 |
gen_op_load_601_rtcu();
|
|
| 330 |
gen_helper_load_601_rtcu(cpu_gpr[gprn]);
|
|
| 306 | 331 |
} |
| 307 | 332 |
|
| 308 | 333 |
#if !defined(CONFIG_USER_ONLY) |
| 309 |
static void spr_write_601_rtcu (void *opaque, int sprn) |
|
| 334 |
static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
|
|
| 310 | 335 |
{
|
| 311 |
gen_op_store_601_rtcu();
|
|
| 336 |
gen_helper_store_601_rtcu(cpu_gpr[gprn]);
|
|
| 312 | 337 |
} |
| 313 | 338 |
|
| 314 |
static void spr_write_601_rtcl (void *opaque, int sprn) |
|
| 339 |
static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
|
|
| 315 | 340 |
{
|
| 316 |
gen_op_store_601_rtcl();
|
|
| 341 |
gen_helper_store_601_rtcl(cpu_gpr[gprn]);
|
|
| 317 | 342 |
} |
| 318 | 343 |
|
| 319 |
static void spr_write_hid0_601 (void *opaque, int sprn) |
|
| 344 |
static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
|
|
| 320 | 345 |
{
|
| 321 | 346 |
DisasContext *ctx = opaque; |
| 322 | 347 |
|
| 323 |
gen_op_store_hid0_601();
|
|
| 348 |
gen_helper_store_hid0_601(cpu_gpr[gprn]);
|
|
| 324 | 349 |
/* Must stop the translation as endianness may have changed */ |
| 325 | 350 |
GEN_STOP(ctx); |
| 326 | 351 |
} |
| ... | ... | |
| 328 | 353 |
|
| 329 | 354 |
/* Unified bats */ |
| 330 | 355 |
#if !defined(CONFIG_USER_ONLY) |
| 331 |
static void spr_read_601_ubat (void *opaque, int sprn) |
|
| 356 |
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
|
|
| 332 | 357 |
{
|
| 333 |
gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
|
|
| 358 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
|
|
| 334 | 359 |
} |
| 335 | 360 |
|
| 336 |
static void spr_write_601_ubatu (void *opaque, int sprn) |
|
| 361 |
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
|
|
| 337 | 362 |
{
|
| 338 |
gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2); |
|
| 363 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
| 364 |
gen_helper_store_601_batl(t0, cpu_gpr[gprn]); |
|
| 365 |
tcg_temp_free_i32(t0); |
|
| 339 | 366 |
} |
| 340 | 367 |
|
| 341 |
static void spr_write_601_ubatl (void *opaque, int sprn) |
|
| 368 |
static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
|
|
| 342 | 369 |
{
|
| 343 |
gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2); |
|
| 370 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
| 371 |
gen_helper_store_601_batu(t0, cpu_gpr[gprn]); |
|
| 372 |
tcg_temp_free_i32(t0); |
|
| 344 | 373 |
} |
| 345 | 374 |
#endif |
| 346 | 375 |
|
| 347 | 376 |
/* PowerPC 40x specific registers */ |
| 348 | 377 |
#if !defined(CONFIG_USER_ONLY) |
| 349 |
static void spr_read_40x_pit (void *opaque, int sprn) |
|
| 378 |
static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
|
|
| 350 | 379 |
{
|
| 351 |
gen_op_load_40x_pit();
|
|
| 380 |
gen_helper_load_40x_pit(cpu_gpr[gprn]);
|
|
| 352 | 381 |
} |
| 353 | 382 |
|
| 354 |
static void spr_write_40x_pit (void *opaque, int sprn) |
|
| 383 |
static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
|
|
| 355 | 384 |
{
|
| 356 |
gen_op_store_40x_pit();
|
|
| 385 |
gen_helper_store_40x_pit(cpu_gpr[gprn]);
|
|
| 357 | 386 |
} |
| 358 | 387 |
|
| 359 |
static void spr_write_40x_dbcr0 (void *opaque, int sprn) |
|
| 388 |
static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
|
|
| 360 | 389 |
{
|
| 361 | 390 |
DisasContext *ctx = opaque; |
| 362 | 391 |
|
| 363 |
gen_op_store_40x_dbcr0();
|
|
| 392 |
gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
|
|
| 364 | 393 |
/* We must stop translation as we may have rebooted */ |
| 365 | 394 |
GEN_STOP(ctx); |
| 366 | 395 |
} |
| 367 | 396 |
|
| 368 |
static void spr_write_40x_sler (void *opaque, int sprn) |
|
| 397 |
static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
|
|
| 369 | 398 |
{
|
| 370 |
gen_op_store_40x_sler();
|
|
| 399 |
gen_helper_store_40x_sler(cpu_gpr[gprn]);
|
|
| 371 | 400 |
} |
| 372 | 401 |
|
| 373 |
static void spr_write_booke_tcr (void *opaque, int sprn) |
|
| 402 |
static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
|
|
| 374 | 403 |
{
|
| 375 |
gen_op_store_booke_tcr();
|
|
| 404 |
gen_helper_store_booke_tcr(cpu_gpr[gprn]);
|
|
| 376 | 405 |
} |
| 377 | 406 |
|
| 378 |
static void spr_write_booke_tsr (void *opaque, int sprn) |
|
| 407 |
static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
|
|
| 379 | 408 |
{
|
| 380 |
gen_op_store_booke_tsr();
|
|
| 409 |
gen_helper_store_booke_tsr(cpu_gpr[gprn]);
|
|
| 381 | 410 |
} |
| 382 | 411 |
#endif |
| 383 | 412 |
|
| 384 | 413 |
/* PowerPC 403 specific registers */ |
| 385 | 414 |
/* PBL1 / PBU1 / PBL2 / PBU2 */ |
| 386 | 415 |
#if !defined(CONFIG_USER_ONLY) |
| 387 |
static void spr_read_403_pbr (void *opaque, int sprn) |
|
| 416 |
static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
|
|
| 388 | 417 |
{
|
| 389 |
gen_op_load_403_pb(sprn - SPR_403_PBL1);
|
|
| 418 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
|
|
| 390 | 419 |
} |
| 391 | 420 |
|
| 392 |
static void spr_write_403_pbr (void *opaque, int sprn) |
|
| 421 |
static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
|
|
| 393 | 422 |
{
|
| 394 |
gen_op_store_403_pb(sprn - SPR_403_PBL1); |
|
| 423 |
TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
|
| 424 |
gen_helper_store_403_pbr(t0, cpu_gpr[gprn]); |
|
| 425 |
tcg_temp_free_i32(t0); |
|
| 395 | 426 |
} |
| 396 | 427 |
|
| 397 |
static void spr_write_pir (void *opaque, int sprn) |
|
| 428 |
static void spr_write_pir (void *opaque, int sprn, int gprn)
|
|
| 398 | 429 |
{
|
| 399 |
gen_op_store_pir(); |
|
| 430 |
TCGv t0 = tcg_temp_new(); |
|
| 431 |
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); |
|
| 432 |
gen_store_spr(SPR_PIR, t0); |
|
| 433 |
tcg_temp_free(t0); |
|
| 400 | 434 |
} |
| 401 | 435 |
#endif |
| 402 | 436 |
|
| 403 | 437 |
#if !defined(CONFIG_USER_ONLY) |
| 404 | 438 |
/* Callback used to write the exception vector base */ |
| 405 |
static void spr_write_excp_prefix (void *opaque, int sprn) |
|
| 439 |
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
|
|
| 406 | 440 |
{
|
| 407 |
gen_op_store_excp_prefix(); |
|
| 408 |
gen_op_store_spr(sprn); |
|
| 441 |
TCGv t0 = tcg_temp_new(); |
|
| 442 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask)); |
|
| 443 |
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
|
| 444 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix)); |
|
| 445 |
gen_store_spr(sprn, t0); |
|
| 409 | 446 |
} |
| 410 | 447 |
|
| 411 |
static void spr_write_excp_vector (void *opaque, int sprn) |
|
| 448 |
static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
|
|
| 412 | 449 |
{
|
| 413 | 450 |
DisasContext *ctx = opaque; |
| 414 | 451 |
|
| 415 | 452 |
if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
|
| 416 |
gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0); |
|
| 417 |
gen_op_store_spr(sprn); |
|
| 453 |
TCGv t0 = tcg_temp_new(); |
|
| 454 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); |
|
| 455 |
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
|
| 456 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0])); |
|
| 457 |
gen_store_spr(sprn, t0); |
|
| 458 |
tcg_temp_free(t0); |
|
| 418 | 459 |
} else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
|
| 419 |
gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32); |
|
| 420 |
gen_op_store_spr(sprn); |
|
| 460 |
TCGv t0 = tcg_temp_new(); |
|
| 461 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); |
|
| 462 |
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
|
| 463 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32])); |
|
| 464 |
gen_store_spr(sprn, t0); |
|
| 465 |
tcg_temp_free(t0); |
|
| 421 | 466 |
} else {
|
| 422 | 467 |
printf("Trying to write an unknown exception vector %d %03x\n",
|
| 423 | 468 |
sprn, sprn); |
| ... | ... | |
| 434 | 479 |
} while (0) |
| 435 | 480 |
static inline void _spr_register (CPUPPCState *env, int num, |
| 436 | 481 |
const char *name, |
| 437 |
void (*uea_read)(void *opaque, int sprn), |
|
| 438 |
void (*uea_write)(void *opaque, int sprn), |
|
| 482 |
void (*uea_read)(void *opaque, int gprn, int sprn),
|
|
| 483 |
void (*uea_write)(void *opaque, int sprn, int gprn),
|
|
| 439 | 484 |
target_ulong initial_value) |
| 440 | 485 |
#else |
| 441 | 486 |
static inline void spr_register (CPUPPCState *env, int num, |
| 442 | 487 |
const char *name, |
| 443 |
void (*uea_read)(void *opaque, int sprn), |
|
| 444 |
void (*uea_write)(void *opaque, int sprn), |
|
| 445 |
void (*oea_read)(void *opaque, int sprn), |
|
| 446 |
void (*oea_write)(void *opaque, int sprn), |
|
| 488 |
void (*uea_read)(void *opaque, int gprn, int sprn),
|
|
| 489 |
void (*uea_write)(void *opaque, int sprn, int gprn),
|
|
| 490 |
void (*oea_read)(void *opaque, int gprn, int sprn),
|
|
| 491 |
void (*oea_write)(void *opaque, int sprn, int gprn),
|
|
| 447 | 492 |
target_ulong initial_value) |
| 448 | 493 |
#endif |
| 449 | 494 |
{
|
Also available in: Unified diff