Archipelago » qemu

  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }

   __exidx_start = .;

  .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }

   __exidx_end = .;

  .tbss           : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }

  .preinit_array     :

  {

    PROVIDE_HIDDEN (__preinit_array_start = .);

    KEEP (*(.preinit_array))

    PROVIDE_HIDDEN (__preinit_array_end = .);

  }

  .init_array     :

  {

     PROVIDE_HIDDEN (__init_array_start = .);

     KEEP (*(SORT(.init_array.*)))

     KEEP (*(.init_array))

     PROVIDE_HIDDEN (__init_array_end = .);

  }

  .fini_array     :

  {

    PROVIDE_HIDDEN (__fini_array_start = .);

    KEEP (*(.fini_array))

    KEEP (*(SORT(.fini_array.*)))

    PROVIDE_HIDDEN (__fini_array_end = .);

  }

#else

/* The host CPU doesn't have an easily accessible cycle counter.

   Just return a monotonically increasing vlue.  This will be totally wrong,

   but hopefully better than nothing.  */

static inline int64_t cpu_get_real_ticks (void)

{

    static int64_t ticks = 0;

    return ticks++;

}

        /* since data is included in the code, it is better to

        fprintf(out, "%08x  ", (int)bfd_getl32((const bfd_byte *)pc));

    int offset, min_offset, pc_offset, data_size, spare, max_pool;

    int type;

    spare = 0x7fffffff;

        /* TODO: Armv5e ldrd.  */

        /* TODO: VFP load.  */

                offset = -offset;

            max_pool = 4096;

            type = 0;

        } else if ((insn & 0x0e5f0f00) == 0x0c1f0100) {

            /* FPA ldf.  */

            offset = (insn & 0xff) << 2;

            if (!(insn & 0x00800000))

                offset = -offset;

            max_pool = 1024;

            type = 1;

        } else if ((insn & 0x0fff0000) == 0x028f0000) {

            /* Some gcc load a doubleword immediate with

               add regN, pc, #imm

               ldmia regN, {regN, regM}

               Hope and pray the compiler never generates somethin like

               add reg, pc, #imm1; ldr reg, [reg, #-imm2]; */

            int r;

            r = (insn & 0xf00) >> 7;

            offset = ((insn & 0xff) >> r) | ((insn & 0xff) << (32 - r));

            max_pool = 1024;

            type = 2;

        } else {

            max_pool = 0;

            type = -1;

        }

        if (type >= 0) {

            /* PC-relative load needs fixing up.  */

            if (spare > max_pool - offset)

                spare = max_pool - offset;

                error("%s:%04x: pc offset must be 32 bit aligned", 

                      name, start_offset + p - p_start);

            if (offset < 0)

                error("%s:%04x: Embedded literal value",

                error("%s:%04x: pc offset must point inside the function code", 

                /* The intruction position */

                /* The position of the constant pool data.  */

                data_index = ((p_end - p_start) - pc_offset) >> 2;

                fprintf(outfile, "    arm_ldr_ptr->data_ptr = arm_data_ptr - %d;\n", 

                fprintf(outfile, "    arm_ldr_ptr->type = %d;\n", type);

    /* Copy and relocate the constant pool data.  */

        spare += min_offset;

        fprintf(outfile, "    arm_data_ptr -= %d;\n", data_size >> 2);

        fprintf(outfile, "    arm_pool_ptr -= %d;\n", data_size);

        fprintf(outfile, "    if (arm_pool_ptr > gen_code_ptr + %d)\n"

                         "        arm_pool_ptr = gen_code_ptr + %d;\n",

                         spare, spare);

        data_index = 0;

        for (pc_offset = min_offset;

             pc_offset < p_end - p_start;

             pc_offset += 4) {

            ELF_RELOC *rel;

            int i, addend, type;

            const char *sym_name;

            char relname[1024];

            /* data value */

            addend = get32((uint32_t *)(p_start + pc_offset));

            relname[0] = '\0';

            for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) {

                if (rel->r_offset == (pc_offset + start_offset)) {

                    sym_name = get_rel_sym_name(rel);

                    /* the compiler leave some unnecessary references to the code */

                    get_reloc_expr(relname, sizeof(relname), sym_name);

                    type = ELF32_R_TYPE(rel->r_info);

                    if (type != R_ARM_ABS32)

                        error("%s: unsupported data relocation", name);

                    break;

                }

            }

            fprintf(outfile, "    arm_data_ptr[%d] = 0x%x",

                    data_index, addend);

            if (relname[0] != '\0')

                fprintf(outfile, " + %s", relname);

            fprintf(outfile, ";\n");

            data_index++;

        }

    /* The last instruction must be an ldm instruction.  There are several

       forms generated by gcc:

        ldmib sp, {..., pc}  (implies a sp adjustment of +4)

        ldmia sp, {..., pc}

        ldmea fp, {..., pc} */

    if ((insn & 0xffff8000) == 0xe99d8000) {

        if (outfile) {

            fprintf(outfile,

                    "    *(uint32_t *)(gen_code_ptr + %d) = 0xe28dd004;\n",

                    p - p_start);

        }

        p += 4;

    } else if ((insn & 0xffff8000) != 0xe89d8000

        && (insn & 0xffff8000) != 0xe91b8000) {

    return p - p_start;

        uint32_t insn;

        insn = get32((uint32_t *)p_start);

        if ((insn & 0xffffff00) == 0xe24dd000) {

            /* Stack adjustment.  Assume op uses the frame pointer.  */

            p_start -= 4;

            start_offset -= 4;

        }

                uint32_t insn;

                insn = get32((uint32_t *)(p_start + 4));

                /* If prologue ends in sub sp, sp, #const then assume

                   op has a stack frame and needs the frame pointer.  */

                if ((insn & 0xffffff00) == 0xe24dd000) {

                    int i;

                    uint32_t opcode;

                    opcode = 0xe28db000; /* add fp, sp, #0.  */

#if 0

/* ??? Need to undo the extra stack adjustment at the end of the op.

   For now just leave the stack misaligned and hope it doesn't break anything

   too important.  */

                    if ((insn & 4) != 0) {

                        /* Preserve doubleword stack alignment.  */

                        fprintf(outfile,

                                "    *(uint32_t *)(gen_code_ptr + 4)= 0x%x;\n",

                                insn + 4);

                        opcode -= 4;

                    }

#endif

                    insn = get32((uint32_t *)(p_start - 4));

                    /* Calculate the size of the saved registers,

                       excluding pc.  */

                    for (i = 0; i < 15; i++) {

                        if (insn & (1 << i))

                            opcode += 4;

                    }

                    fprintf(outfile,

                            "    *(uint32_t *)gen_code_ptr = 0x%x;\n", opcode);

                }

                    case R_ARM_JUMP24:

                    case R_ARM_CALL:

#ifdef HOST_ARM

        /* We need to know the size of all the ops so we can figure out when

           to emit constant pools.  This must be consistent with opc.h.  */

fprintf(outfile,

"static const uint32_t arm_opc_size[] = {\n"

"  0,\n" /* end */

"  0,\n" /* nop */

"  0,\n" /* nop1 */

"  0,\n" /* nop2 */

"  0,\n"); /* nop3 */

        for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {

            const char *name;

            name = get_sym_name(sym);

            if (strstart(name, OP_PREFIX, NULL)) {

                fprintf(outfile, "  %d,\n", sym->st_size);

            }

	}

fprintf(outfile,

"};\n");

#endif

/* Arm is tricky because it uses constant pools for loading immediate values.

   We assume (and require) each function is code followed by a constant pool.

   All the ops are small so this should be ok.  For each op we figure

   out how much "spare" range we have in the load instructions.  This allows

   us to insert subsequent ops in between the op and the constant pool,

   eliminating the neeed to jump around the pool.

   We currently generate:

   [ For this example we assume merging would move op1_pool out of range.

     In practice we should be able to combine many ops before the offset

     limits are reached. ]

   op1_code;

   op2_code;

   goto op3;

   op2_pool;

   op1_pool;

op3:

   op3_code;

   ret;

   op3_pool;

   Ideally we'd put op1_pool before op2_pool, but that requires two passes.

 */

"    uint32_t *arm_data_ptr = arm_data_table + ARM_LDR_TABLE_SIZE;\n"

/* Initialise the parmissible pool offset to an arbitary large value.  */

"    uint8_t *arm_pool_ptr = gen_code_buf + 0x1000000;\n");

"    for(;;) {\n");

#ifdef HOST_ARM

/* Generate constant pool if needed */

fprintf(outfile,

"            if (gen_code_ptr + arm_opc_size[*opc_ptr] >= arm_pool_ptr) {\n"

"                gen_code_ptr = arm_flush_ldr(gen_code_ptr, arm_ldr_table, "

"arm_ldr_ptr, arm_data_ptr, arm_data_table + ARM_LDR_TABLE_SIZE, 1);\n"

"                last_gen_code_ptr = gen_code_ptr;\n"

"                arm_ldr_ptr = arm_ldr_table;\n"

"                arm_data_ptr = arm_data_table + ARM_LDR_TABLE_SIZE;\n"

"                arm_pool_ptr = gen_code_ptr + 0x1000000;\n"

"            }\n");

#endif

fprintf(outfile,

"        switch(*opc_ptr++) {\n");

fprintf(outfile,

"if (arm_data_ptr != arm_data_table + ARM_LDR_TABLE_SIZE)\n"

"    gen_code_ptr = arm_flush_ldr(gen_code_ptr, arm_ldr_table, "

"arm_ldr_ptr, arm_data_ptr, arm_data_table + ARM_LDR_TABLE_SIZE, 0);\n");

#if defined(__sparc__) || defined(__arm__)

#define ARM_LDR_TABLE_SIZE 1024

    unsigned type:2;

static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];

    uint32_t mask;

    data_size = (data_end - data_start) << 2;

            fprintf(stderr, "Negative constant pool offset\n");

        switch (le->type) {

          case 0: /* ldr */

            mask = ~0x00800fff;

            if (offset >= 4096) {

                fprintf(stderr, "Bad ldr offset\n");

                abort();

            }

            break;

          case 1: /* ldc */

            mask = ~0x008000ff;

            if (offset >= 1024 ) {

                fprintf(stderr, "Bad ldc offset\n");

                abort();

            }

            break;

          case 2: /* add */

            mask = ~0xfff;

            if (offset >= 1024 ) {

                fprintf(stderr, "Bad add offset\n");

                abort();

            }

            break;

          default:

            fprintf(stderr, "Bad pc relative fixup\n");

            abort();

          }

        insn = *ptr & mask;

        switch (le->type) {

          case 0: /* ldr */

            insn |= offset | 0x00800000;

            break;

          case 1: /* ldc */

            insn |= (offset >> 2) | 0x00800000;

            break;

          case 2: /* add */

            insn |= (offset >> 2) | 0xf00;

            break;

          }

#define R_ARM_CALL              28

#define R_ARM_JUMP24            29