root / target-ppc / mmu-hash32.c @ 469296f1
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/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "helper.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "mmu-hash32.h" |
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|
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//#define DEBUG_MMU
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//#define DEBUG_BAT
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) |
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#else
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# define LOG_MMU(...) do { } while (0) |
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# define LOG_MMU_STATE(cpu) do { } while (0) |
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#endif
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|
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0) |
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#endif
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|
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struct mmu_ctx_hash32 {
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hwaddr raddr; /* Real address */
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int prot; /* Protection bits */ |
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int key; /* Access key */ |
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}; |
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|
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static int ppc_hash32_pp_prot(int key, int pp, int nx) |
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{
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int prot;
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|
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if (key == 0) { |
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switch (pp) {
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case 0x0: |
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case 0x1: |
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case 0x2: |
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prot = PAGE_READ | PAGE_WRITE; |
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break;
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|
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case 0x3: |
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prot = PAGE_READ; |
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break;
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default:
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abort(); |
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} |
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} else {
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switch (pp) {
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case 0x0: |
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prot = 0;
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break;
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case 0x1: |
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case 0x3: |
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prot = PAGE_READ; |
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break;
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case 0x2: |
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prot = PAGE_READ | PAGE_WRITE; |
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break;
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default:
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abort(); |
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} |
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} |
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if (nx == 0) { |
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prot |= PAGE_EXEC; |
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} |
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return prot;
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} |
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static int ppc_hash32_pte_prot(CPUPPCState *env, |
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target_ulong sr, ppc_hash_pte32_t pte) |
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{
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unsigned pp, key;
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key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); |
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pp = pte.pte1 & HPTE32_R_PP; |
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|
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return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
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} |
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static target_ulong hash32_bat_size(CPUPPCState *env,
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target_ulong batu, target_ulong batl) |
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{
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if ((msr_pr && !(batu & BATU32_VP))
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|| (!msr_pr && !(batu & BATU32_VS))) {
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return 0; |
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} |
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return BATU32_BEPI & ~((batu & BATU32_BL) << 15); |
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} |
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static int hash32_bat_prot(CPUPPCState *env, |
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target_ulong batu, target_ulong batl) |
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{
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int pp, prot;
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prot = 0;
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pp = batl & BATL32_PP; |
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if (pp != 0) { |
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prot = PAGE_READ | PAGE_EXEC; |
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if (pp == 0x2) { |
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prot |= PAGE_WRITE; |
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} |
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} |
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return prot;
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} |
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static target_ulong hash32_bat_601_size(CPUPPCState *env,
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target_ulong batu, target_ulong batl) |
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{
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if (!(batl & BATL32_601_V)) {
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return 0; |
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} |
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return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17); |
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} |
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static int hash32_bat_601_prot(CPUPPCState *env, |
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target_ulong batu, target_ulong batl) |
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{
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int key, pp;
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pp = batu & BATU32_601_PP; |
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if (msr_pr == 0) { |
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key = !!(batu & BATU32_601_KS); |
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} else {
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key = !!(batu & BATU32_601_KP); |
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} |
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return ppc_hash32_pp_prot(key, pp, 0); |
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} |
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static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx, |
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int *prot)
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{
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target_ulong *BATlt, *BATut; |
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int i;
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LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, |
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rwx == 2 ? 'I' : 'D', ea); |
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if (rwx == 2) { |
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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} else {
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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} |
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for (i = 0; i < env->nb_BATs; i++) { |
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target_ulong batu = BATut[i]; |
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target_ulong batl = BATlt[i]; |
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target_ulong mask; |
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if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
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mask = hash32_bat_601_size(env, batu, batl); |
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} else {
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mask = hash32_bat_size(env, batu, batl); |
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} |
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
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" BATl " TARGET_FMT_lx "\n", __func__, |
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type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl); |
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if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
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hwaddr raddr = (batl & mask) | (ea & ~mask); |
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if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
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*prot = hash32_bat_601_prot(env, batu, batl); |
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} else {
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*prot = hash32_bat_prot(env, batu, batl); |
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} |
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return raddr & TARGET_PAGE_MASK;
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} |
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} |
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/* No hit */
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#if defined(DEBUG_BATS)
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if (qemu_log_enabled()) {
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LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea); |
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for (i = 0; i < 4; i++) { |
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BATu = &BATut[i]; |
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BATl = &BATlt[i]; |
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BEPIu = *BATu & BATU32_BEPIU; |
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BEPIl = *BATu & BATU32_BEPIL; |
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bl = (*BATu & 0x00001FFC) << 15; |
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
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" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " |
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TARGET_FMT_lx " " TARGET_FMT_lx "\n", |
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, ea, |
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*BATu, *BATl, BEPIu, BEPIl, bl); |
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} |
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} |
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#endif
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return -1; |
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} |
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static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, |
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target_ulong eaddr, int rwx,
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hwaddr *raddr, int *prot)
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{
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int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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LOG_MMU("direct store...\n");
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if ((sr & 0x1FF00000) >> 20 == 0x07f) { |
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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*raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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if (rwx == 2) { |
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/* No code fetch is allowed in direct-store areas */
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env->exception_index = POWERPC_EXCP_ISI; |
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env->error_code = 0x10000000;
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return 1; |
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} |
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|
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switch (env->access_type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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env->exception_index = POWERPC_EXCP_ALIGN; |
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env->error_code = POWERPC_EXCP_ALIGN_FP; |
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env->spr[SPR_DAR] = eaddr; |
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return 1; |
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr; |
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if (rwx == 1) { |
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env->spr[SPR_DSISR] = 0x06000000;
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} else {
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env->spr[SPR_DSISR] = 0x04000000;
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} |
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return 1; |
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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*raddr = eaddr; |
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return 0; |
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case ACCESS_EXT:
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/* eciwx or ecowx */
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env->exception_index = POWERPC_EXCP_DSI; |
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr; |
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if (rwx == 1) { |
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env->spr[SPR_DSISR] = 0x06100000;
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} else {
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env->spr[SPR_DSISR] = 0x04100000;
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} |
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return 1; |
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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abort(); |
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} |
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if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) { |
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*raddr = eaddr; |
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return 0; |
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} else {
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env->exception_index = POWERPC_EXCP_DSI; |
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr; |
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if (rwx == 1) { |
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env->spr[SPR_DSISR] = 0x0a000000;
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} else {
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env->spr[SPR_DSISR] = 0x08000000;
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} |
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return 1; |
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} |
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} |
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|
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hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash) |
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{
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return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
|
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} |
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|
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static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
|
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bool secondary, target_ulong ptem,
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ppc_hash_pte32_t *pte) |
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{
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hwaddr pte_offset = pteg_off; |
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target_ulong pte0, pte1; |
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int i;
|
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|
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for (i = 0; i < HPTES_PER_GROUP; i++) { |
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pte0 = ppc_hash32_load_hpte0(env, pte_offset); |
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pte1 = ppc_hash32_load_hpte1(env, pte_offset); |
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|
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if ((pte0 & HPTE32_V_VALID)
|
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&& (secondary == !!(pte0 & HPTE32_V_SECONDARY)) |
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&& HPTE32_V_COMPARE(pte0, ptem)) {
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pte->pte0 = pte0; |
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pte->pte1 = pte1; |
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return pte_offset;
|
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} |
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|
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pte_offset += HASH_PTE_SIZE_32; |
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} |
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|
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return -1; |
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} |
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|
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static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
|
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target_ulong sr, target_ulong eaddr, |
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ppc_hash_pte32_t *pte) |
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{
|
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hwaddr pteg_off, pte_offset; |
| 341 |
hwaddr hash; |
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uint32_t vsid, pgidx, ptem; |
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|
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vsid = sr & SR32_VSID; |
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS; |
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hash = vsid ^ pgidx; |
| 347 |
ptem = (vsid << 7) | (pgidx >> 10); |
| 348 |
|
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/* Page address translation */
|
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx |
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" hash " TARGET_FMT_plx "\n", |
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env->htab_base, env->htab_mask, hash); |
| 353 |
|
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/* Primary PTEG lookup */
|
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
| 356 |
" vsid=%" PRIx32 " ptem=%" PRIx32 |
| 357 |
" hash=" TARGET_FMT_plx "\n", |
| 358 |
env->htab_base, env->htab_mask, vsid, ptem, hash); |
| 359 |
pteg_off = get_pteg_offset32(env, hash); |
| 360 |
pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
|
| 361 |
if (pte_offset == -1) { |
| 362 |
/* Secondary PTEG lookup */
|
| 363 |
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
| 364 |
" vsid=%" PRIx32 " api=%" PRIx32 |
| 365 |
" hash=" TARGET_FMT_plx "\n", env->htab_base, |
| 366 |
env->htab_mask, vsid, ptem, ~hash); |
| 367 |
pteg_off = get_pteg_offset32(env, ~hash); |
| 368 |
pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
|
| 369 |
} |
| 370 |
|
| 371 |
return pte_offset;
|
| 372 |
} |
| 373 |
|
| 374 |
static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
|
| 375 |
target_ulong eaddr) |
| 376 |
{
|
| 377 |
hwaddr rpn = pte.pte1 & HPTE32_R_RPN; |
| 378 |
hwaddr mask = ~TARGET_PAGE_MASK; |
| 379 |
|
| 380 |
return (rpn & ~mask) | (eaddr & mask);
|
| 381 |
} |
| 382 |
|
| 383 |
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, |
| 384 |
int mmu_idx)
|
| 385 |
{
|
| 386 |
target_ulong sr; |
| 387 |
hwaddr pte_offset; |
| 388 |
ppc_hash_pte32_t pte; |
| 389 |
int prot;
|
| 390 |
uint32_t new_pte1; |
| 391 |
const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
| 392 |
hwaddr raddr; |
| 393 |
|
| 394 |
assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
| 395 |
|
| 396 |
/* 1. Handle real mode accesses */
|
| 397 |
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { |
| 398 |
/* Translation is off */
|
| 399 |
raddr = eaddr; |
| 400 |
tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
| 401 |
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, |
| 402 |
TARGET_PAGE_SIZE); |
| 403 |
return 0; |
| 404 |
} |
| 405 |
|
| 406 |
/* 2. Check Block Address Translation entries (BATs) */
|
| 407 |
if (env->nb_BATs != 0) { |
| 408 |
raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot); |
| 409 |
if (raddr != -1) { |
| 410 |
if (need_prot[rwx] & ~prot) {
|
| 411 |
if (rwx == 2) { |
| 412 |
env->exception_index = POWERPC_EXCP_ISI; |
| 413 |
env->error_code = 0x08000000;
|
| 414 |
} else {
|
| 415 |
env->exception_index = POWERPC_EXCP_DSI; |
| 416 |
env->error_code = 0;
|
| 417 |
env->spr[SPR_DAR] = eaddr; |
| 418 |
if (rwx == 1) { |
| 419 |
env->spr[SPR_DSISR] = 0x0a000000;
|
| 420 |
} else {
|
| 421 |
env->spr[SPR_DSISR] = 0x08000000;
|
| 422 |
} |
| 423 |
} |
| 424 |
return 1; |
| 425 |
} |
| 426 |
|
| 427 |
tlb_set_page(env, eaddr & TARGET_PAGE_MASK, |
| 428 |
raddr & TARGET_PAGE_MASK, prot, mmu_idx, |
| 429 |
TARGET_PAGE_SIZE); |
| 430 |
return 0; |
| 431 |
} |
| 432 |
} |
| 433 |
|
| 434 |
/* 3. Look up the Segment Register */
|
| 435 |
sr = env->sr[eaddr >> 28];
|
| 436 |
|
| 437 |
/* 4. Handle direct store segments */
|
| 438 |
if (sr & SR32_T) {
|
| 439 |
if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
|
| 440 |
&raddr, &prot) == 0) {
|
| 441 |
tlb_set_page(env, eaddr & TARGET_PAGE_MASK, |
| 442 |
raddr & TARGET_PAGE_MASK, prot, mmu_idx, |
| 443 |
TARGET_PAGE_SIZE); |
| 444 |
return 0; |
| 445 |
} else {
|
| 446 |
return 1; |
| 447 |
} |
| 448 |
} |
| 449 |
|
| 450 |
/* 5. Check for segment level no-execute violation */
|
| 451 |
if ((rwx == 2) && (sr & SR32_NX)) { |
| 452 |
env->exception_index = POWERPC_EXCP_ISI; |
| 453 |
env->error_code = 0x10000000;
|
| 454 |
return 1; |
| 455 |
} |
| 456 |
|
| 457 |
/* 6. Locate the PTE in the hash table */
|
| 458 |
pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); |
| 459 |
if (pte_offset == -1) { |
| 460 |
if (rwx == 2) { |
| 461 |
env->exception_index = POWERPC_EXCP_ISI; |
| 462 |
env->error_code = 0x40000000;
|
| 463 |
} else {
|
| 464 |
env->exception_index = POWERPC_EXCP_DSI; |
| 465 |
env->error_code = 0;
|
| 466 |
env->spr[SPR_DAR] = eaddr; |
| 467 |
if (rwx == 1) { |
| 468 |
env->spr[SPR_DSISR] = 0x42000000;
|
| 469 |
} else {
|
| 470 |
env->spr[SPR_DSISR] = 0x40000000;
|
| 471 |
} |
| 472 |
} |
| 473 |
|
| 474 |
return 1; |
| 475 |
} |
| 476 |
LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); |
| 477 |
|
| 478 |
/* 7. Check access permissions */
|
| 479 |
|
| 480 |
prot = ppc_hash32_pte_prot(env, sr, pte); |
| 481 |
|
| 482 |
if (need_prot[rwx] & ~prot) {
|
| 483 |
/* Access right violation */
|
| 484 |
LOG_MMU("PTE access rejected\n");
|
| 485 |
if (rwx == 2) { |
| 486 |
env->exception_index = POWERPC_EXCP_ISI; |
| 487 |
env->error_code = 0x08000000;
|
| 488 |
} else {
|
| 489 |
env->exception_index = POWERPC_EXCP_DSI; |
| 490 |
env->error_code = 0;
|
| 491 |
env->spr[SPR_DAR] = eaddr; |
| 492 |
if (rwx == 1) { |
| 493 |
env->spr[SPR_DSISR] = 0x0a000000;
|
| 494 |
} else {
|
| 495 |
env->spr[SPR_DSISR] = 0x08000000;
|
| 496 |
} |
| 497 |
} |
| 498 |
return 1; |
| 499 |
} |
| 500 |
|
| 501 |
LOG_MMU("PTE access granted !\n");
|
| 502 |
|
| 503 |
/* 8. Update PTE referenced and changed bits if necessary */
|
| 504 |
|
| 505 |
new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
|
| 506 |
if (rwx == 1) { |
| 507 |
new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
|
| 508 |
} else {
|
| 509 |
/* Treat the page as read-only for now, so that a later write
|
| 510 |
* will pass through this function again to set the C bit */
|
| 511 |
prot &= ~PAGE_WRITE; |
| 512 |
} |
| 513 |
|
| 514 |
if (new_pte1 != pte.pte1) {
|
| 515 |
ppc_hash32_store_hpte1(env, pte_offset, new_pte1); |
| 516 |
} |
| 517 |
|
| 518 |
/* 9. Determine the real address from the PTE */
|
| 519 |
|
| 520 |
raddr = ppc_hash32_pte_raddr(sr, pte, eaddr); |
| 521 |
|
| 522 |
tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
| 523 |
prot, mmu_idx, TARGET_PAGE_SIZE); |
| 524 |
|
| 525 |
return 0; |
| 526 |
} |
| 527 |
|
| 528 |
hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr) |
| 529 |
{
|
| 530 |
target_ulong sr; |
| 531 |
hwaddr pte_offset; |
| 532 |
ppc_hash_pte32_t pte; |
| 533 |
int prot;
|
| 534 |
|
| 535 |
if (msr_dr == 0) { |
| 536 |
/* Translation is off */
|
| 537 |
return eaddr;
|
| 538 |
} |
| 539 |
|
| 540 |
if (env->nb_BATs != 0) { |
| 541 |
hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
|
| 542 |
if (raddr != -1) { |
| 543 |
return raddr;
|
| 544 |
} |
| 545 |
} |
| 546 |
|
| 547 |
sr = env->sr[eaddr >> 28];
|
| 548 |
|
| 549 |
if (sr & SR32_T) {
|
| 550 |
/* FIXME: Add suitable debug support for Direct Store segments */
|
| 551 |
return -1; |
| 552 |
} |
| 553 |
|
| 554 |
pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); |
| 555 |
if (pte_offset == -1) { |
| 556 |
return -1; |
| 557 |
} |
| 558 |
|
| 559 |
return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
|
| 560 |
} |