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/*
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 * QEMU Soundblaster 16 emulation
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 * 
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 * Copyright (c) 2003 Vassili Karpov (malc)
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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#define MIN(a, b) ((a)>(b)?(b):(a))
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#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
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#define DEREF(x) (void)x
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#define log(...) fprintf (stderr, "sb16: " __VA_ARGS__)
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/* #define DEBUG_SB16 */
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#ifdef DEBUG_SB16
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#define lwarn(...) fprintf (stderr, "sb16: " __VA_ARGS__)
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#define linfo(...) fprintf (stderr, "sb16: " __VA_ARGS__)
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#define ldebug(...) fprintf (stderr, "sb16: " __VA_ARGS__)
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#else
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#define lwarn(...)
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#define linfo(...)
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#define ldebug(...)
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#endif
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#define IO_READ_PROTO(name) \
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    uint32_t name (void *opaque, uint32_t nport)
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#define IO_WRITE_PROTO(name) \
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    void name (void *opaque, uint32_t nport, uint32_t val)
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static struct {
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    int ver_lo;
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    int ver_hi;
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    int irq;
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    int dma;
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    int hdma;
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    int port;
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    int mix_block;
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} sb = {5, 4, 5, 1, 5, 0x220, -1};
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static int mix_block, noirq;
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typedef struct SB16State {
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    int in_index;
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    int out_data_len;
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    int fmt_stereo;
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    int fmt_signed;
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    int fmt_bits;
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    int dma_auto;
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    int dma_buffer_size;
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    int fifo;
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    int freq;
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    int time_const;
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    int speaker;
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    int needed_bytes;
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    int cmd;
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    int dma_pos;
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    int use_hdma;
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    int v2x6;
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    uint8_t in_data[10];
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    uint8_t out_data[10];
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    int left_till_irq;
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    /* mixer state */
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    int mixer_nreg;
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    uint8_t mixer_regs[0x83];
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} SB16State;
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/* XXX: suppress that and use a context */
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static struct SB16State dsp;
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static void log_dsp (SB16State *dsp)
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{
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    linfo ("%c:%c:%d:%c:dmabuf=%d:pos=%d:freq=%d:timeconst=%d:speaker=%d\n",
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           dsp->fmt_stereo ? 'S' : 'M',
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           dsp->fmt_signed ? 'S' : 'U',
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           dsp->fmt_bits,
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           dsp->dma_auto ? 'a' : 's',
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           dsp->dma_buffer_size,
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           dsp->dma_pos,
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           dsp->freq,
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           dsp->time_const,
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           dsp->speaker);
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}
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static void control (int hold)
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{
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    linfo ("%d high %d\n", hold, dsp.use_hdma);
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    if (hold) {
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        if (dsp.use_hdma)
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            DMA_hold_DREQ (sb.hdma);
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        else
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            DMA_hold_DREQ (sb.dma);
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    }
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    else {
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        if (dsp.use_hdma)
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            DMA_release_DREQ (sb.hdma);
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        else
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            DMA_release_DREQ (sb.dma);
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    }
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}
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static void dma_cmd (uint8_t cmd, uint8_t d0, int dma_len)
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{
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    int bps;
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    audfmt_e fmt;
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    dsp.use_hdma = cmd < 0xc0;
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    dsp.fifo = (cmd >> 1) & 1;
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    dsp.dma_auto = (cmd >> 2) & 1;
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    switch (cmd >> 4) {
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    case 11:
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        dsp.fmt_bits = 16;
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        break;
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    case 12:
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        dsp.fmt_bits = 8;
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        break;
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    }
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    dsp.fmt_signed = (d0 >> 4) & 1;
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    dsp.fmt_stereo = (d0 >> 5) & 1;
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    if (-1 != dsp.time_const) {
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        int tmp;
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        tmp = 256 - dsp.time_const;
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        dsp.freq = (1000000 + (tmp / 2)) / tmp;
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    }
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    bps = 1 << (16 == dsp.fmt_bits);
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    if (-1 != dma_len)
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        dsp.dma_buffer_size = (dma_len + 1) * bps;
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    linfo ("frequency %d, stereo %d, signed %d, bits %d, size %d, auto %d\n",
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           dsp.freq, dsp.fmt_stereo, dsp.fmt_signed, dsp.fmt_bits,
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           dsp.dma_buffer_size, dsp.dma_auto);
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    if (16 == dsp.fmt_bits) {
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        if (dsp.fmt_signed) {
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            fmt = AUD_FMT_S16;
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        }
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        else {
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            fmt = AUD_FMT_U16;
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        }
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    }
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    else {
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        if (dsp.fmt_signed) {
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            fmt = AUD_FMT_S8;
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        }
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        else {
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            fmt = AUD_FMT_U8;
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        }
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    }
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    dsp.dma_pos = 0;
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    dsp.left_till_irq = dsp.dma_buffer_size;
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    if (sb.mix_block) {
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        mix_block = sb.mix_block;
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    }
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    else {
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        int align;
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        align = bps << dsp.fmt_stereo;
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        mix_block = ((dsp.freq * align) / 100) & ~(align - 1);
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    }
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    AUD_reset (dsp.freq, 1 << dsp.fmt_stereo, fmt);
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    control (1);
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    dsp.speaker = 1;
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}
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static void command (SB16State *dsp, uint8_t cmd)
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{
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    linfo ("%#x\n", cmd);
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    if (cmd > 0xaf && cmd < 0xd0) {
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        if (cmd & 8)
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            goto error;
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        switch (cmd >> 4) {
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        case 11:
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        case 12:
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            break;
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        default:
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            log("%#x wrong bits", cmd);
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            goto error;
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        }
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        dsp->needed_bytes = 3;
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    }
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    else {
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        switch (cmd) {
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        case 0x00:
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        case 0x03:
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        case 0xe7:
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            /* IMS uses those when probing for sound devices */
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            return;
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        case 0x10:
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            dsp->needed_bytes = 1;
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            break;
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        case 0x14:
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            dsp->needed_bytes = 2;
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            dsp->dma_buffer_size = 0;
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            break;
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        case 0x20:
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            dsp->out_data[dsp->out_data_len++] = 0xff;
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            break;
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        case 0x35:
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            lwarn ("MIDI commands not implemented\n");
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            break;
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        case 0x40:
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            dsp->freq = -1;
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            dsp->time_const = -1;
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            dsp->needed_bytes = 1;
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            break;
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        case 0x41:
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        case 0x42:
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            dsp->freq = -1;
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            dsp->time_const = -1;
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            dsp->needed_bytes = 2;
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            break;
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        case 0x47:                /* Continue Auto-Initialize DMA 16bit */
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            break;
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        case 0x48:
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            dsp->needed_bytes = 2;
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            break;
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        case 0x27:                /* ????????? */
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        case 0x4e:
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            return;
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        case 0x80:
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            cmd = -1;
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            break;
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        case 0x90:
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        case 0x91:
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            {
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                uint8_t d0;
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                d0 = 4;
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                if (dsp->fmt_signed) d0 |= 16;
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                if (dsp->fmt_stereo) d0 |= 32;
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                dma_cmd (cmd == 0x90 ? 0xc4 : 0xc0, d0, -1);
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                cmd = -1;
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                break;
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            }
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        case 0xd0:                /* XXX */
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            control (0);
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            return;
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        case 0xd1:
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            dsp->speaker = 1;
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            break;
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        case 0xd3:
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            dsp->speaker = 0;
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            return;
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        case 0xd4:
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            control (1);
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            break;
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        case 0xd5:
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            control (0);
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            break;
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        case 0xd6:
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            control (1);
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            break;
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        case 0xd9:
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            control (0);
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            dsp->dma_auto = 0;
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            return;
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        case 0xda:
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            control (0);
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            dsp->dma_auto = 0;
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            break;
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        case 0xe0:
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            dsp->needed_bytes = 1;
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            break;
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        case 0xe1:
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            dsp->out_data[dsp->out_data_len++] = sb.ver_lo;
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            dsp->out_data[dsp->out_data_len++] = sb.ver_hi;
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            return;
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        case 0xf2:
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            dsp->out_data[dsp->out_data_len++] = 0xaa;
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            dsp->mixer_regs[0x82] |= dsp->mixer_regs[0x80];
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            pic_set_irq (sb.irq, 1);
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            return;
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        default:
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            log("%#x is unknown", cmd);
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            goto error;
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        }
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    }
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    dsp->cmd = cmd;
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    return;
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336 27503323 bellard
 error:
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    return;
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}
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static void complete (SB16State *dsp)
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{
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    linfo ("complete command %#x, in_index %d, needed_bytes %d\n",
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           dsp->cmd, dsp->in_index, dsp->needed_bytes);
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    if (dsp->cmd > 0xaf && dsp->cmd < 0xd0) {
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        int d0, d1, d2;
347 27503323 bellard
348 5e2a6443 bellard
        d0 = dsp->in_data[0];
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        d1 = dsp->in_data[1];
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        d2 = dsp->in_data[2];
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        ldebug ("d0 = %d, d1 = %d, d2 = %d\n",
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                d0, d1, d2);
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        dma_cmd (dsp->cmd, d0, d1 + (d2 << 8));
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    }
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    else {
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        switch (dsp->cmd) {
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        case 0x10:
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            break;
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        case 0x14:
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            {
364 27503323 bellard
                int d0, d1;
365 27503323 bellard
                int save_left;
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                int save_pos;
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368 5e2a6443 bellard
                d0 = dsp->in_data[0];
369 5e2a6443 bellard
                d1 = dsp->in_data[1];
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371 5e2a6443 bellard
                save_left = dsp->left_till_irq;
372 5e2a6443 bellard
                save_pos = dsp->dma_pos;
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                dma_cmd (0xc0, 0, d0 + (d1 << 8));
374 5e2a6443 bellard
                dsp->left_till_irq = save_left;
375 5e2a6443 bellard
                dsp->dma_pos = save_pos;
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377 27503323 bellard
                linfo ("set buffer size data[%d, %d] %d pos %d\n",
378 5e2a6443 bellard
                       d0, d1, dsp->dma_buffer_size, dsp->dma_pos);
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                break;
380 27503323 bellard
            }
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        case 0x40:
383 5e2a6443 bellard
            dsp->time_const = dsp->in_data[0];
384 5e2a6443 bellard
            linfo ("set time const %d\n", dsp->time_const);
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            break;
386 27503323 bellard
387 27503323 bellard
        case 0x41:
388 27503323 bellard
        case 0x42:
389 5e2a6443 bellard
            dsp->freq = dsp->in_data[1] + (dsp->in_data[0] << 8);
390 27503323 bellard
            linfo ("set freq %#x, %#x = %d\n",
391 5e2a6443 bellard
                   dsp->in_data[1], dsp->in_data[0], dsp->freq);
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            break;
393 27503323 bellard
394 27503323 bellard
        case 0x48:
395 5e2a6443 bellard
            dsp->dma_buffer_size = dsp->in_data[1] + (dsp->in_data[0] << 8);
396 27503323 bellard
            linfo ("set dma len %#x, %#x = %d\n",
397 5e2a6443 bellard
                   dsp->in_data[1], dsp->in_data[0], dsp->dma_buffer_size);
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            break;
399 27503323 bellard
400 27503323 bellard
        case 0xe0:
401 5e2a6443 bellard
            dsp->out_data_len = 1;
402 5e2a6443 bellard
            linfo ("data = %#x\n", dsp->in_data[0]);
403 5e2a6443 bellard
            dsp->out_data[0] = dsp->in_data[0] ^ 0xff;
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            break;
405 27503323 bellard
406 27503323 bellard
        default:
407 5e2a6443 bellard
            log ("unrecognized command %#x", dsp->cmd);
408 5e2a6443 bellard
            return;
409 27503323 bellard
        }
410 27503323 bellard
    }
411 27503323 bellard
412 5e2a6443 bellard
    dsp->cmd = -1;
413 27503323 bellard
    return;
414 27503323 bellard
}
415 27503323 bellard
416 27503323 bellard
static IO_WRITE_PROTO (dsp_write)
417 27503323 bellard
{
418 5e2a6443 bellard
    SB16State *dsp = opaque;
419 27503323 bellard
    int iport;
420 27503323 bellard
421 27503323 bellard
    iport = nport - sb.port;
422 27503323 bellard
423 27503323 bellard
    switch (iport) {
424 27503323 bellard
    case 0x6:
425 27503323 bellard
        if (0 == val)
426 5e2a6443 bellard
            dsp->v2x6 = 0;
427 5e2a6443 bellard
        else if ((1 == val) && (0 == dsp->v2x6)) {
428 5e2a6443 bellard
            dsp->v2x6 = 1;
429 5e2a6443 bellard
            dsp->out_data[dsp->out_data_len++] = 0xaa;
430 27503323 bellard
        }
431 27503323 bellard
        else
432 5e2a6443 bellard
            dsp->v2x6 = ~0;
433 27503323 bellard
        break;
434 27503323 bellard
435 27503323 bellard
    case 0xc:                   /* write data or command | write status */
436 5e2a6443 bellard
        if (0 == dsp->needed_bytes) {
437 5e2a6443 bellard
            command (dsp, val);
438 5e2a6443 bellard
            if (0 == dsp->needed_bytes) {
439 5e2a6443 bellard
                log_dsp (dsp);
440 27503323 bellard
            }
441 27503323 bellard
        }
442 27503323 bellard
        else {
443 5e2a6443 bellard
            dsp->in_data[dsp->in_index++] = val;
444 5e2a6443 bellard
            if (dsp->in_index == dsp->needed_bytes) {
445 5e2a6443 bellard
                dsp->needed_bytes = 0;
446 5e2a6443 bellard
                dsp->in_index = 0;
447 5e2a6443 bellard
                complete (dsp);
448 5e2a6443 bellard
                log_dsp (dsp);
449 27503323 bellard
            }
450 27503323 bellard
        }
451 27503323 bellard
        break;
452 27503323 bellard
453 27503323 bellard
    default:
454 5e2a6443 bellard
        log ("(nport=%#x, val=%#x)", nport, val);
455 5e2a6443 bellard
        break;
456 27503323 bellard
    }
457 27503323 bellard
}
458 27503323 bellard
459 27503323 bellard
static IO_READ_PROTO (dsp_read)
460 27503323 bellard
{
461 5e2a6443 bellard
    SB16State *dsp = opaque;
462 27503323 bellard
    int iport, retval;
463 27503323 bellard
464 27503323 bellard
    iport = nport - sb.port;
465 27503323 bellard
466 27503323 bellard
    switch (iport) {
467 27503323 bellard
468 27503323 bellard
    case 0x6:                   /* reset */
469 27503323 bellard
        return 0;
470 27503323 bellard
471 27503323 bellard
    case 0xa:                   /* read data */
472 5e2a6443 bellard
        if (dsp->out_data_len) {
473 5e2a6443 bellard
            retval = dsp->out_data[--dsp->out_data_len];
474 5e2a6443 bellard
        } else {
475 5e2a6443 bellard
            log("empty output buffer\n");
476 27503323 bellard
            goto error;
477 27503323 bellard
        }
478 27503323 bellard
        break;
479 27503323 bellard
480 27503323 bellard
    case 0xc:                   /* 0 can write */
481 27503323 bellard
        retval = 0;
482 27503323 bellard
        break;
483 27503323 bellard
484 27503323 bellard
    case 0xd:                   /* timer interrupt clear */
485 5e2a6443 bellard
        log("timer interrupt clear\n");
486 27503323 bellard
        goto error;
487 27503323 bellard
488 27503323 bellard
    case 0xe:                   /* data available status | irq 8 ack */
489 bc0b1dc1 bellard
        /* XXX drop pic irq line here? */
490 bc0b1dc1 bellard
        ldebug ("8 ack\n");
491 5e2a6443 bellard
        retval = (0 == dsp->out_data_len) ? 0 : 0x80;
492 5e2a6443 bellard
        dsp->mixer_regs[0x82] &= ~dsp->mixer_regs[0x80];
493 bc0b1dc1 bellard
        pic_set_irq (sb.irq, 0);
494 27503323 bellard
        break;
495 27503323 bellard
496 27503323 bellard
    case 0xf:                   /* irq 16 ack */
497 bc0b1dc1 bellard
        /* XXX drop pic irq line here? */
498 27503323 bellard
        ldebug ("16 ack\n");
499 bc0b1dc1 bellard
        retval = 0xff;
500 5e2a6443 bellard
        dsp->mixer_regs[0x82] &= ~dsp->mixer_regs[0x80];
501 bc0b1dc1 bellard
        pic_set_irq (sb.irq, 0);
502 27503323 bellard
        break;
503 27503323 bellard
504 27503323 bellard
    default:
505 27503323 bellard
        goto error;
506 27503323 bellard
    }
507 27503323 bellard
508 27503323 bellard
    if ((0xc != iport) && (0xe != iport)) {
509 bc0b1dc1 bellard
        ldebug ("nport=%#x iport %#x = %#x\n",
510 bc0b1dc1 bellard
                nport, iport, retval);
511 27503323 bellard
    }
512 27503323 bellard
513 27503323 bellard
    return retval;
514 27503323 bellard
515 27503323 bellard
 error:
516 5e2a6443 bellard
    return 0;
517 27503323 bellard
}
518 27503323 bellard
519 27503323 bellard
static IO_WRITE_PROTO(mixer_write_indexb)
520 27503323 bellard
{
521 5e2a6443 bellard
    SB16State *dsp = opaque;
522 5e2a6443 bellard
    dsp->mixer_nreg = val & 0xff;
523 27503323 bellard
}
524 27503323 bellard
525 27503323 bellard
static IO_WRITE_PROTO(mixer_write_datab)
526 27503323 bellard
{
527 5e2a6443 bellard
    SB16State *dsp = opaque;
528 5e2a6443 bellard
    dsp->mixer_regs[dsp->mixer_nreg] = val;
529 27503323 bellard
}
530 27503323 bellard
531 27503323 bellard
static IO_WRITE_PROTO(mixer_write_indexw)
532 27503323 bellard
{
533 7d977de7 bellard
    mixer_write_indexb (opaque, nport, val & 0xff);
534 7d977de7 bellard
    mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
535 27503323 bellard
}
536 27503323 bellard
537 27503323 bellard
static IO_READ_PROTO(mixer_read)
538 27503323 bellard
{
539 5e2a6443 bellard
    SB16State *dsp = opaque;
540 5e2a6443 bellard
    return dsp->mixer_regs[dsp->mixer_nreg];
541 27503323 bellard
}
542 27503323 bellard
543 27503323 bellard
void SB16_run (void)
544 27503323 bellard
{
545 27503323 bellard
    if (0 == dsp.speaker)
546 27503323 bellard
        return;
547 27503323 bellard
548 27503323 bellard
    AUD_run ();
549 27503323 bellard
}
550 27503323 bellard
551 27503323 bellard
static int write_audio (uint32_t addr, int len, int size)
552 27503323 bellard
{
553 27503323 bellard
    int temp, net;
554 f9e92e97 bellard
    uint8_t tmpbuf[4096];
555 27503323 bellard
556 27503323 bellard
    temp = size;
557 27503323 bellard
558 27503323 bellard
    net = 0;
559 27503323 bellard
560 27503323 bellard
    while (temp) {
561 27503323 bellard
        int left_till_end;
562 27503323 bellard
        int to_copy;
563 27503323 bellard
        int copied;
564 27503323 bellard
565 27503323 bellard
        left_till_end = len - dsp.dma_pos;
566 27503323 bellard
567 27503323 bellard
        to_copy = MIN (temp, left_till_end);
568 f9e92e97 bellard
        if (to_copy > sizeof(tmpbuf))
569 f9e92e97 bellard
            to_copy = sizeof(tmpbuf);
570 f9e92e97 bellard
        cpu_physical_memory_read(addr + dsp.dma_pos, tmpbuf, to_copy);
571 f9e92e97 bellard
        copied = AUD_write (tmpbuf, to_copy);
572 27503323 bellard
573 27503323 bellard
        temp -= copied;
574 27503323 bellard
        dsp.dma_pos += copied;
575 27503323 bellard
576 27503323 bellard
        if (dsp.dma_pos == len) {
577 27503323 bellard
            dsp.dma_pos = 0;
578 27503323 bellard
        }
579 27503323 bellard
580 27503323 bellard
        net += copied;
581 27503323 bellard
582 27503323 bellard
        if (copied != to_copy)
583 27503323 bellard
            return net;
584 27503323 bellard
    }
585 27503323 bellard
586 27503323 bellard
    return net;
587 27503323 bellard
}
588 27503323 bellard
589 f9e92e97 bellard
static int SB_read_DMA (void *opaque, target_ulong addr, int size)
590 27503323 bellard
{
591 5e2a6443 bellard
    SB16State *dsp = opaque;
592 27503323 bellard
    int free, till, copy, written;
593 27503323 bellard
594 5e2a6443 bellard
    if (0 == dsp->speaker)
595 27503323 bellard
        return 0;
596 27503323 bellard
597 5e2a6443 bellard
    if (dsp->left_till_irq < 0) {
598 5e2a6443 bellard
        dsp->left_till_irq += dsp->dma_buffer_size;
599 5e2a6443 bellard
        return dsp->dma_pos;
600 27503323 bellard
    }
601 27503323 bellard
602 27503323 bellard
    free = AUD_get_free ();
603 27503323 bellard
604 27503323 bellard
    if ((free <= 0) || (0 == size)) {
605 5e2a6443 bellard
        return dsp->dma_pos;
606 27503323 bellard
    }
607 27503323 bellard
608 27503323 bellard
    if (mix_block > 0) {
609 27503323 bellard
        copy = MIN (free, mix_block);
610 27503323 bellard
    }
611 27503323 bellard
    else {
612 27503323 bellard
        copy = free;
613 27503323 bellard
    }
614 27503323 bellard
615 5e2a6443 bellard
    till = dsp->left_till_irq;
616 27503323 bellard
617 27503323 bellard
    ldebug ("addr:%#010x free:%d till:%d size:%d\n",
618 27503323 bellard
            addr, free, till, size);
619 27503323 bellard
    if (till <= copy) {
620 5e2a6443 bellard
        if (0 == dsp->dma_auto) {
621 27503323 bellard
            copy = till;
622 27503323 bellard
        }
623 27503323 bellard
    }
624 27503323 bellard
625 27503323 bellard
    written = write_audio (addr, size, copy);
626 5e2a6443 bellard
    dsp->left_till_irq -= written;
627 27503323 bellard
    AUD_adjust_estimate (free - written);
628 27503323 bellard
629 5e2a6443 bellard
    if (dsp->left_till_irq <= 0) {
630 5e2a6443 bellard
        dsp->mixer_regs[0x82] |= dsp->mixer_regs[0x80];
631 bc0b1dc1 bellard
        if (0 == noirq) {
632 bc0b1dc1 bellard
            ldebug ("request irq\n");
633 f9e92e97 bellard
            pic_set_irq(sb.irq, 1);
634 bc0b1dc1 bellard
        }
635 27503323 bellard
636 5e2a6443 bellard
        if (0 == dsp->dma_auto) {
637 27503323 bellard
            control (0);
638 27503323 bellard
        }
639 27503323 bellard
    }
640 27503323 bellard
641 27503323 bellard
    ldebug ("pos %5d free %5d size %5d till % 5d copy %5d dma size %5d\n",
642 5e2a6443 bellard
            dsp->dma_pos, free, size, dsp->left_till_irq, copy,
643 5e2a6443 bellard
            dsp->dma_buffer_size);
644 27503323 bellard
645 5e2a6443 bellard
    if (dsp->left_till_irq <= 0) {
646 5e2a6443 bellard
        dsp->left_till_irq += dsp->dma_buffer_size;
647 27503323 bellard
    }
648 27503323 bellard
649 5e2a6443 bellard
    return dsp->dma_pos;
650 27503323 bellard
}
651 27503323 bellard
652 27503323 bellard
static int magic_of_irq (int irq)
653 27503323 bellard
{
654 27503323 bellard
    switch (irq) {
655 27503323 bellard
    case 2:
656 27503323 bellard
        return 1;
657 27503323 bellard
    case 5:
658 27503323 bellard
        return 2;
659 27503323 bellard
    case 7:
660 27503323 bellard
        return 4;
661 27503323 bellard
    case 10:
662 27503323 bellard
        return 8;
663 27503323 bellard
    default:
664 27503323 bellard
        log ("bad irq %d\n", irq);
665 27503323 bellard
        return 2;
666 27503323 bellard
    }
667 27503323 bellard
}
668 27503323 bellard
669 27503323 bellard
static int irq_of_magic (int magic)
670 27503323 bellard
{
671 27503323 bellard
    switch (magic) {
672 27503323 bellard
    case 1:
673 27503323 bellard
        return 2;
674 27503323 bellard
    case 2:
675 27503323 bellard
        return 5;
676 27503323 bellard
    case 4:
677 27503323 bellard
        return 7;
678 27503323 bellard
    case 8:
679 27503323 bellard
        return 10;
680 27503323 bellard
    default:
681 27503323 bellard
        log ("bad irq magic %d\n", magic);
682 27503323 bellard
        return 2;
683 27503323 bellard
    }
684 27503323 bellard
}
685 27503323 bellard
686 27503323 bellard
void SB16_init (void)
687 27503323 bellard
{
688 5e2a6443 bellard
    SB16State *s = &dsp;
689 27503323 bellard
    int i;
690 27503323 bellard
    static const uint8_t dsp_write_ports[] = {0x6, 0xc};
691 27503323 bellard
    static const uint8_t dsp_read_ports[] = {0x6, 0xa, 0xc, 0xd, 0xe, 0xf};
692 27503323 bellard
693 5e2a6443 bellard
    s->mixer_regs[0x0e] = ~0;
694 5e2a6443 bellard
    s->mixer_regs[0x80] = magic_of_irq (sb.irq);
695 5e2a6443 bellard
    s->mixer_regs[0x81] = 0x20 | (sb.dma << 1);
696 27503323 bellard
697 27503323 bellard
    DEREF (irq_of_magic);
698 27503323 bellard
699 27503323 bellard
    for (i = 0x30; i < 0x48; i++) {
700 5e2a6443 bellard
        s->mixer_regs[i] = 0x20;
701 27503323 bellard
    }
702 27503323 bellard
703 27503323 bellard
    for (i = 0; i < LENOFA (dsp_write_ports); i++) {
704 5e2a6443 bellard
        register_ioport_write (sb.port + dsp_write_ports[i], 1, 1, dsp_write, s);
705 27503323 bellard
    }
706 27503323 bellard
707 27503323 bellard
    for (i = 0; i < LENOFA (dsp_read_ports); i++) {
708 5e2a6443 bellard
        register_ioport_read (sb.port + dsp_read_ports[i], 1, 1, dsp_read, s);
709 27503323 bellard
    }
710 27503323 bellard
711 5e2a6443 bellard
    register_ioport_write (sb.port + 0x4, 1, 1, mixer_write_indexb, s);
712 5e2a6443 bellard
    register_ioport_write (sb.port + 0x4, 1, 2, mixer_write_indexw, s);
713 5e2a6443 bellard
    register_ioport_read (sb.port + 0x5, 1, 1, mixer_read, s);
714 5e2a6443 bellard
    register_ioport_write (sb.port + 0x5, 1, 1, mixer_write_datab, s);
715 27503323 bellard
716 5e2a6443 bellard
    DMA_register_channel (sb.hdma, SB_read_DMA, s);
717 5e2a6443 bellard
    DMA_register_channel (sb.dma, SB_read_DMA, s);
718 27503323 bellard
}