Archipelago » qemu

/*

 * QEMU VGA Emulator.

 * 

 * Copyright (c) 2003 Fabrice Bellard

 * 

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

//#define DEBUG_VGA

//#define DEBUG_VGA_MEM

//#define DEBUG_VGA_REG

//#define DEBUG_S3

//#define DEBUG_BOCHS_VBE

#define CONFIG_S3VGA

#define MSR_COLOR_EMULATION 0x01

#define MSR_PAGE_SELECT     0x20

#define ST01_V_RETRACE      0x08

#define ST01_DISP_ENABLE    0x01

/* bochs VBE support */

#define CONFIG_BOCHS_VBE

#define VBE_DISPI_MAX_XRES              1024

#define VBE_DISPI_MAX_YRES              768

#define VBE_DISPI_INDEX_ID              0x0

#define VBE_DISPI_INDEX_XRES            0x1

#define VBE_DISPI_INDEX_YRES            0x2

#define VBE_DISPI_INDEX_BPP             0x3

#define VBE_DISPI_INDEX_ENABLE          0x4

#define VBE_DISPI_INDEX_BANK            0x5

#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6

#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7

#define VBE_DISPI_INDEX_X_OFFSET        0x8

#define VBE_DISPI_INDEX_Y_OFFSET        0x9

#define VBE_DISPI_INDEX_NB              0xa

#define VBE_DISPI_ID0                   0xB0C0

#define VBE_DISPI_ID1                   0xB0C1

#define VBE_DISPI_ID2                   0xB0C2

#define VBE_DISPI_DISABLED              0x00

#define VBE_DISPI_ENABLED               0x01

#define VBE_DISPI_LFB_ENABLED           0x40

#define VBE_DISPI_NOCLEARMEM            0x80

#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

typedef struct VGAState {

    uint8_t *vram_ptr;

    unsigned long vram_offset;

    unsigned int vram_size;

    uint32_t latch;

    uint8_t sr_index;

    uint8_t sr[8];

    uint8_t gr_index;

    uint8_t gr[16];

    uint8_t ar_index;

    uint8_t ar[21];

    int ar_flip_flop;

    uint8_t cr_index;

    uint8_t cr[256]; /* CRT registers */

    uint8_t msr; /* Misc Output Register */

    uint8_t fcr; /* Feature Control Register */

    uint8_t st00; /* status 0 */

    uint8_t st01; /* status 1 */

    uint8_t dac_state;

    uint8_t dac_sub_index;

    uint8_t dac_read_index;

    uint8_t dac_write_index;

    uint8_t dac_cache[3]; /* used when writing */

    uint8_t palette[768];

    uint32_t bank_offset;

#ifdef CONFIG_BOCHS_VBE

    uint16_t vbe_index;

    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];

    uint32_t vbe_start_addr;

    uint32_t vbe_line_offset;

    uint32_t vbe_bank_mask;

#endif

    /* display refresh support */

    DisplayState *ds;

    uint32_t font_offsets[2];

    int graphic_mode;

    uint8_t shift_control;

    uint8_t double_scan;

    uint32_t line_offset;

    uint32_t line_compare;

    uint32_t start_addr;

    uint8_t last_cw, last_ch;

    uint32_t last_width, last_height;

    uint8_t cursor_start, cursor_end;

    uint32_t cursor_offset;

    unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b);

    /* tell for each page if it has been updated since the last time */

    uint32_t last_palette[256];

#define CH_ATTR_SIZE (160 * 100)

    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */

} VGAState;

/* force some bits to zero */

static const uint8_t sr_mask[8] = {

    (uint8_t)~0xfc,

    (uint8_t)~0xc2,

    (uint8_t)~0xf0,

    (uint8_t)~0xc0,

    (uint8_t)~0xf1,

    (uint8_t)~0xff,

    (uint8_t)~0xff,

    (uint8_t)~0x00,

};

static const uint8_t gr_mask[16] = {

    (uint8_t)~0xf0, /* 0x00 */

    (uint8_t)~0xf0, /* 0x01 */

    (uint8_t)~0xf0, /* 0x02 */

    (uint8_t)~0xe0, /* 0x03 */

    (uint8_t)~0xfc, /* 0x04 */

    (uint8_t)~0x84, /* 0x05 */

    (uint8_t)~0xf0, /* 0x06 */

    (uint8_t)~0xf0, /* 0x07 */

    (uint8_t)~0x00, /* 0x08 */

    (uint8_t)~0xff, /* 0x09 */

    (uint8_t)~0xff, /* 0x0a */

    (uint8_t)~0xff, /* 0x0b */

    (uint8_t)~0xff, /* 0x0c */

    (uint8_t)~0xff, /* 0x0d */

    (uint8_t)~0xff, /* 0x0e */

    (uint8_t)~0xff, /* 0x0f */

};

#define cbswap_32(__x) \

((uint32_t)( \

                (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \

                (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \

                (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \

                (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))

#ifdef WORDS_BIGENDIAN

#define PAT(x) cbswap_32(x)

#else

#define PAT(x) (x)

#endif

#ifdef WORDS_BIGENDIAN

#define BIG 1

#else

#define BIG 0

#endif

#ifdef WORDS_BIGENDIAN

#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)

#else

#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)

#endif

static const uint32_t mask16[16] = {

    PAT(0x00000000),

    PAT(0x000000ff),

    PAT(0x0000ff00),

    PAT(0x0000ffff),

    PAT(0x00ff0000),

    PAT(0x00ff00ff),

    PAT(0x00ffff00),

    PAT(0x00ffffff),

    PAT(0xff000000),

    PAT(0xff0000ff),

    PAT(0xff00ff00),

    PAT(0xff00ffff),

    PAT(0xffff0000),

    PAT(0xffff00ff),

    PAT(0xffffff00),

    PAT(0xffffffff),

};

#undef PAT

#ifdef WORDS_BIGENDIAN

#define PAT(x) (x)

#else

#define PAT(x) cbswap_32(x)

#endif

static const uint32_t dmask16[16] = {

    PAT(0x00000000),

    PAT(0x000000ff),

    PAT(0x0000ff00),

    PAT(0x0000ffff),

    PAT(0x00ff0000),

    PAT(0x00ff00ff),

    PAT(0x00ffff00),

    PAT(0x00ffffff),

    PAT(0xff000000),

    PAT(0xff0000ff),

    PAT(0xff00ff00),

    PAT(0xff00ffff),

    PAT(0xffff0000),

    PAT(0xffff00ff),

    PAT(0xffffff00),

    PAT(0xffffffff),

};

static const uint32_t dmask4[4] = {

    PAT(0x00000000),

    PAT(0x0000ffff),

    PAT(0xffff0000),

    PAT(0xffffffff),

};

static uint32_t expand4[256];

static uint16_t expand2[256];

static uint8_t expand4to8[16];

VGAState vga_state;

int vga_io_memory;

static uint32_t vga_ioport_read(void *opaque, uint32_t addr)

{

    VGAState *s = opaque;

    int val, index;

    /* check port range access depending on color/monochrome mode */

    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||

        (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {

        val = 0xff;

    } else {

        switch(addr) {

        case 0x3c0:

            if (s->ar_flip_flop == 0) {

                val = s->ar_index;

            } else {

                val = 0;

            }

            break;

        case 0x3c1:

            index = s->ar_index & 0x1f;

            if (index < 21) 

                val = s->ar[index];

            else

                val = 0;

            break;

        case 0x3c2:

            val = s->st00;

            break;

        case 0x3c4:

            val = s->sr_index;

            break;

        case 0x3c5:

            val = s->sr[s->sr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);

#endif

            break;

        case 0x3c7:

            val = s->dac_state;

            break;

        case 0x3c9:

            val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];

            if (++s->dac_sub_index == 3) {

                s->dac_sub_index = 0;

                s->dac_read_index++;

            }

            break;

        case 0x3ca:

            val = s->fcr;

            break;

        case 0x3cc:

            val = s->msr;

            break;

        case 0x3ce:

            val = s->gr_index;

            break;

        case 0x3cf:

            val = s->gr[s->gr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);

#endif

            break;

        case 0x3b4:

        case 0x3d4:

            val = s->cr_index;

            break;

        case 0x3b5:

        case 0x3d5:

            val = s->cr[s->cr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);

#endif

#ifdef DEBUG_S3

            if (s->cr_index >= 0x20)

                printf("S3: CR read index=0x%x val=0x%x\n",

                       s->cr_index, val);

#endif

            break;

        case 0x3ba:

        case 0x3da:

            /* just toggle to fool polling */

            s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;

            val = s->st01;

            s->ar_flip_flop = 0;

            break;

        default:

            val = 0x00;

            break;

        }

    }

#if defined(DEBUG_VGA)

    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);

#endif

    return val;

}

static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)

{

    VGAState *s = opaque;

    int index, v;

    /* check port range access depending on color/monochrome mode */

    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||

        (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))

        return;

#ifdef DEBUG_VGA

    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);

#endif

    switch(addr) {

    case 0x3c0:

        if (s->ar_flip_flop == 0) {

            val &= 0x3f;

            s->ar_index = val;

        } else {

            index = s->ar_index & 0x1f;

            switch(index) {

            case 0x00 ... 0x0f:

                s->ar[index] = val & 0x3f;

                break;

            case 0x10:

                s->ar[index] = val & ~0x10;

                break;

            case 0x11:

                s->ar[index] = val;

                break;

            case 0x12:

                s->ar[index] = val & ~0xc0;

                break;

            case 0x13:

                s->ar[index] = val & ~0xf0;

                break;

            case 0x14:

                s->ar[index] = val & ~0xf0;

                break;

            default:

                break;

            }

        }

        s->ar_flip_flop ^= 1;

        break;

    case 0x3c2:

        s->msr = val & ~0x10;

        break;

    case 0x3c4:

        s->sr_index = val & 7;

        break;

    case 0x3c5:

#ifdef DEBUG_VGA_REG

        printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);

#endif

        s->sr[s->sr_index] = val & sr_mask[s->sr_index];

        break;

    case 0x3c7:

        s->dac_read_index = val;

        s->dac_sub_index = 0;

        s->dac_state = 3;

        break;

    case 0x3c8:

        s->dac_write_index = val;

        s->dac_sub_index = 0;

        s->dac_state = 0;

        break;

    case 0x3c9:

        s->dac_cache[s->dac_sub_index] = val;

        if (++s->dac_sub_index == 3) {

            memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);

            s->dac_sub_index = 0;

            s->dac_write_index++;

        }

        break;

    case 0x3ce:

        s->gr_index = val & 0x0f;

        break;

    case 0x3cf:

#ifdef DEBUG_VGA_REG

        printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);

#endif

        s->gr[s->gr_index] = val & gr_mask[s->gr_index];

        break;

    case 0x3b4:

    case 0x3d4:

        s->cr_index = val;

        break;

    case 0x3b5:

    case 0x3d5:

#ifdef DEBUG_VGA_REG

        printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);

#endif

        /* handle CR0-7 protection */

        if ((s->cr[11] & 0x80) && s->cr_index <= 7) {

            /* can always write bit 4 of CR7 */

            if (s->cr_index == 7)

                s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);

            return;

        }

        switch(s->cr_index) {

        case 0x01: /* horizontal display end */

        case 0x07:

        case 0x09:

        case 0x0c:

        case 0x0d:

        case 0x12: /* veritcal display end */

            s->cr[s->cr_index] = val;

            break;

#ifdef CONFIG_S3VGA

            /* S3 registers */

        case 0x2d:

        case 0x2e:

        case 0x2f:

        case 0x30:

            /* chip ID, cannot write */

            break;

        case 0x31:

            /* update start address */

            s->cr[s->cr_index] = val;

            v = (val >> 4) & 3;

            s->cr[0x69] = (s->cr[69] & ~0x03) | v;

            break;

        case 0x51:

            /* update start address */

            s->cr[s->cr_index] = val;

            v = val & 3;

            s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2);

            break;

#endif

        default:

            s->cr[s->cr_index] = val;

            break;

        }

#ifdef DEBUG_S3

        if (s->cr_index >= 0x20)

            printf("S3: CR write index=0x%x val=0x%x\n",

                   s->cr_index, val);

#endif

        break;

    case 0x3ba:

    case 0x3da:

        s->fcr = val & 0x10;

        break;

    }

}

#ifdef CONFIG_BOCHS_VBE

static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)

{

    VGAState *s = opaque;

    uint32_t val;

    addr &= 1;

    if (addr == 0) {

        val = s->vbe_index;

    } else {

        if (s->vbe_index <= VBE_DISPI_INDEX_NB)

            val = s->vbe_regs[s->vbe_index];

        else

            val = 0;

#ifdef DEBUG_BOCHS_VBE

        printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);

#endif

    }

    return val;

}

static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)

{

    VGAState *s = opaque;

    addr &= 1;

    if (addr == 0) {

        s->vbe_index = val;

    } else if (s->vbe_index <= VBE_DISPI_INDEX_NB) {

#ifdef DEBUG_BOCHS_VBE

        printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);

#endif

        switch(s->vbe_index) {

        case VBE_DISPI_INDEX_ID:

            if (val == VBE_DISPI_ID0 ||

                val == VBE_DISPI_ID1 ||

                val == VBE_DISPI_ID2) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_XRES:

            if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_YRES:

            if (val <= VBE_DISPI_MAX_YRES) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_BPP:

            if (val == 0)

                val = 8;

            if (val == 4 || val == 8 || val == 15 || 

                val == 16 || val == 24 || val == 32) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_BANK:

            val &= s->vbe_bank_mask;

            s->vbe_regs[s->vbe_index] = val;

            s->bank_offset = (val << 16) - 0xa0000;

            break;

        case VBE_DISPI_INDEX_ENABLE:

            if (val & VBE_DISPI_ENABLED) {

                int h, shift_control;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 

                    s->vbe_regs[VBE_DISPI_INDEX_XRES];

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = 

                    s->vbe_regs[VBE_DISPI_INDEX_YRES];

                s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;

                s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;

                else

                    s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * 

                        ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                s->vbe_start_addr = 0;

                /* clear the screen (should be done in BIOS) */

                if (!(val & VBE_DISPI_NOCLEARMEM)) {

                    memset(s->vram_ptr, 0, 

                           s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);

                }

                /* we initialize the VGA graphic mode (should be done

                   in BIOS) */

                s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */

                s->cr[0x17] |= 3; /* no CGA modes */

                s->cr[0x13] = s->vbe_line_offset >> 3;

                /* width */

                s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;

                /* height */

                h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;

                s->cr[0x12] = h;

                s->cr[0x07] = (s->cr[0x07] & ~0x42) | 

                    ((h >> 7) & 0x02) | ((h >> 3) & 0x40);

                /* line compare to 1023 */

                s->cr[0x18] = 0xff;

                s->cr[0x07] |= 0x10;

                s->cr[0x09] |= 0x40;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {

                    shift_control = 0;

                    s->sr[0x01] &= ~8; /* no double line */

                } else {

                    shift_control = 2;

                }

                s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);

                s->cr[0x09] &= ~0x9f; /* no double scan */

                s->vbe_regs[s->vbe_index] = val;

            } else {

                /* XXX: the bios should do that */

                s->bank_offset = -0xa0000;

            }

            break;

        case VBE_DISPI_INDEX_VIRT_WIDTH:

            {

                int w, h, line_offset;

                if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])

                    return;

                w = val;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    line_offset = w >> 1;

                else

                    line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                h = s->vram_size / line_offset;

                /* XXX: support weird bochs semantics ? */

                if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])

                    return;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;

                s->vbe_line_offset = line_offset;

            }

            break;

        case VBE_DISPI_INDEX_X_OFFSET:

        case VBE_DISPI_INDEX_Y_OFFSET:

            {

                int x;

                s->vbe_regs[s->vbe_index] = val;

                s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];

                x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    s->vbe_start_addr += x >> 1;

                else

                    s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                s->vbe_start_addr >>= 2;

            }

            break;

        default:

            break;

        }

    }

}

#endif

/* called for accesses between 0xa0000 and 0xc0000 */

static uint32_t vga_mem_readb(uint32_t addr)

{

    VGAState *s = &vga_state;

    int memory_map_mode, plane;

    uint32_t ret;

    /* convert to VGA memory offset */

    memory_map_mode = (s->gr[6] >> 2) & 3;

    switch(memory_map_mode) {

    case 0:

        addr -= 0xa0000;

        break;

    case 1:

        if (addr >= 0xb0000)

            return 0xff;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0xb0000;

        if (addr >= 0x8000)

            return 0xff;

        break;

    default:

    case 3:

        addr -= 0xb8000;

        if (addr >= 0x8000)

            return 0xff;

        break;

    }

    if (s->sr[4] & 0x08) {

        /* chain 4 mode : simplest access */

        ret = s->vram_ptr[addr];

    } else if (s->gr[5] & 0x10) {

        /* odd/even mode (aka text mode mapping) */

        plane = (s->gr[4] & 2) | (addr & 1);

        ret = s->vram_ptr[((addr & ~1) << 1) | plane];

    } else {

        /* standard VGA latched access */

        s->latch = ((uint32_t *)s->vram_ptr)[addr];

        if (!(s->gr[5] & 0x08)) {

            /* read mode 0 */

            plane = s->gr[4];

            ret = GET_PLANE(s->latch, plane);

        } else {

            /* read mode 1 */

            ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];

            ret |= ret >> 16;

            ret |= ret >> 8;

            ret = (~ret) & 0xff;

        }

    }

    return ret;

}

static uint32_t vga_mem_readw(uint32_t addr)

{

    uint32_t v;

    v = vga_mem_readb(addr);

    v |= vga_mem_readb(addr + 1) << 8;

    return v;

}

static uint32_t vga_mem_readl(uint32_t addr)

{

    uint32_t v;

    v = vga_mem_readb(addr);

    v |= vga_mem_readb(addr + 1) << 8;

    v |= vga_mem_readb(addr + 2) << 16;

    v |= vga_mem_readb(addr + 3) << 24;

    return v;

}

/* called for accesses between 0xa0000 and 0xc0000 */

static void vga_mem_writeb(uint32_t addr, uint32_t val, uint32_t vaddr)

{

    VGAState *s = &vga_state;

    int memory_map_mode, plane, write_mode, b, func_select;

    uint32_t write_mask, bit_mask, set_mask;

#ifdef DEBUG_VGA_MEM

    printf("vga: [0x%x] = 0x%02x\n", addr, val);

#endif

    /* convert to VGA memory offset */

    memory_map_mode = (s->gr[6] >> 2) & 3;

    switch(memory_map_mode) {

    case 0:

        addr -= 0xa0000;

        break;

    case 1:

        if (addr >= 0xb0000)

            return;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0xb0000;

        if (addr >= 0x8000)

            return;

        break;

    default:

    case 3:

        addr -= 0xb8000;

        if (addr >= 0x8000)

            return;

        break;

    }

    if (s->sr[4] & 0x08) {

        /* chain 4 mode : simplest access */

        plane = addr & 3;

        if (s->sr[2] & (1 << plane)) {

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: chain4: [0x%x]\n", addr);

#endif

            cpu_physical_memory_set_dirty(s->vram_offset + addr);

        }

    } else if (s->gr[5] & 0x10) {

        /* odd/even mode (aka text mode mapping) */

        plane = (s->gr[4] & 2) | (addr & 1);

        if (s->sr[2] & (1 << plane)) {

            addr = ((addr & ~1) << 1) | plane;

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: odd/even: [0x%x]\n", addr);

#endif

            cpu_physical_memory_set_dirty(s->vram_offset + addr);

        }

    } else {

        /* standard VGA latched access */

        write_mode = s->gr[5] & 3;

        switch(write_mode) {

        default:

        case 0:

            /* rotate */

            b = s->gr[3] & 7;

            val = ((val >> b) | (val << (8 - b))) & 0xff;

            val |= val << 8;

            val |= val << 16;

            /* apply set/reset mask */

            set_mask = mask16[s->gr[1]];

            val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);

            bit_mask = s->gr[8];

            break;

        case 1:

            val = s->latch;

            goto do_write;

        case 2:

            val = mask16[val & 0x0f];

            bit_mask = s->gr[8];

            break;

        case 3:

            /* rotate */

            b = s->gr[3] & 7;

            val = (val >> b) | (val << (8 - b));

            bit_mask = s->gr[8] & val;

            val = mask16[s->gr[0]];

            break;

        }

        /* apply logical operation */

        func_select = s->gr[3] >> 3;

        switch(func_select) {

        case 0:

        default:

            /* nothing to do */

            break;

        case 1:

            /* and */

            val &= s->latch;

            break;

        case 2:

            /* or */

            val |= s->latch;

            break;

        case 3:

            /* xor */

            val ^= s->latch;

            break;

        }

        /* apply bit mask */

        bit_mask |= bit_mask << 8;

        bit_mask |= bit_mask << 16;

        val = (val & bit_mask) | (s->latch & ~bit_mask);

    do_write:

        /* mask data according to sr[2] */

        write_mask = mask16[s->sr[2]];

        ((uint32_t *)s->vram_ptr)[addr] = 

            (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | 

            (val & write_mask);

#ifdef DEBUG_VGA_MEM

            printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n", 

                   addr * 4, write_mask, val);

#endif

            cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));

    }

}

static void vga_mem_writew(uint32_t addr, uint32_t val, uint32_t vaddr)

{

    vga_mem_writeb(addr, val & 0xff, vaddr);

    vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);

}

static void vga_mem_writel(uint32_t addr, uint32_t val, uint32_t vaddr)

{

    vga_mem_writeb(addr, val & 0xff, vaddr);

    vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);

    vga_mem_writeb(addr + 2, (val >> 16) & 0xff, vaddr);

    vga_mem_writeb(addr + 3, (val >> 24) & 0xff, vaddr);

}

typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,

                             const uint8_t *font_ptr, int h,

                             uint32_t fgcol, uint32_t bgcol);

typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,

                                  const uint8_t *font_ptr, int h, 

                                  uint32_t fgcol, uint32_t bgcol, int dup9);

typedef void vga_draw_line_func(VGAState *s1, uint8_t *d, 

                                const uint8_t *s, int width);