Revision 472b24ce
| b/target-ppc/translate.c | ||
|---|---|---|
| 51 | 51 |
#endif |
| 52 | 52 |
+ 10*4 + 22*5 /* FPR */ |
| 53 | 53 |
+ 2*(10*6 + 22*7) /* AVRh, AVRl */ |
| 54 |
+ 10*5 + 22*6 /* VSR */ |
|
| 54 | 55 |
+ 8*5 /* CRF */]; |
| 55 | 56 |
static TCGv cpu_gpr[32]; |
| 56 | 57 |
#if !defined(TARGET_PPC64) |
| ... | ... | |
| 58 | 59 |
#endif |
| 59 | 60 |
static TCGv_i64 cpu_fpr[32]; |
| 60 | 61 |
static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
| 62 |
static TCGv_i64 cpu_vsr[32]; |
|
| 61 | 63 |
static TCGv_i32 cpu_crf[8]; |
| 62 | 64 |
static TCGv cpu_nip; |
| 63 | 65 |
static TCGv cpu_msr; |
| ... | ... | |
| 137 | 139 |
#endif |
| 138 | 140 |
p += (i < 10) ? 6 : 7; |
| 139 | 141 |
cpu_reg_names_size -= (i < 10) ? 6 : 7; |
| 142 |
snprintf(p, cpu_reg_names_size, "vsr%d", i); |
|
| 143 |
cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
|
| 144 |
offsetof(CPUPPCState, vsr[i]), p); |
|
| 145 |
p += (i < 10) ? 5 : 6; |
|
| 146 |
cpu_reg_names_size -= (i < 10) ? 5 : 6; |
|
| 140 | 147 |
} |
| 141 | 148 |
|
| 142 | 149 |
cpu_nip = tcg_global_mem_new(TCG_AREG0, |
| ... | ... | |
| 6976 | 6983 |
GEN_VAFORM_PAIRED(vsel, vperm, 21) |
| 6977 | 6984 |
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
| 6978 | 6985 |
|
| 6986 |
/*** VSX extension ***/ |
|
| 6987 |
|
|
| 6988 |
static inline TCGv_i64 cpu_vsrh(int n) |
|
| 6989 |
{
|
|
| 6990 |
if (n < 32) {
|
|
| 6991 |
return cpu_fpr[n]; |
|
| 6992 |
} else {
|
|
| 6993 |
return cpu_avrh[n-32]; |
|
| 6994 |
} |
|
| 6995 |
} |
|
| 6996 |
|
|
| 6997 |
static inline TCGv_i64 cpu_vsrl(int n) |
|
| 6998 |
{
|
|
| 6999 |
if (n < 32) {
|
|
| 7000 |
return cpu_vsr[n]; |
|
| 7001 |
} else {
|
|
| 7002 |
return cpu_avrl[n-32]; |
|
| 7003 |
} |
|
| 7004 |
} |
|
| 7005 |
|
|
| 6979 | 7006 |
/*** SPE extension ***/ |
| 6980 | 7007 |
/* Register moves */ |
| 6981 | 7008 |
|
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