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1 | b00052e4 | balrog | /*
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2 | b00052e4 | balrog | * PXA270-based Clamshell PDA platforms.
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3 | b00052e4 | balrog | *
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4 | b00052e4 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | b00052e4 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | b00052e4 | balrog | *
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7 | b00052e4 | balrog | * This code is licensed under the GNU GPL v2.
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8 | b00052e4 | balrog | */
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9 | b00052e4 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "pxa.h" |
12 | 87ecb68b | pbrook | #include "arm-misc.h" |
13 | 87ecb68b | pbrook | #include "sysemu.h" |
14 | 87ecb68b | pbrook | #include "pcmcia.h" |
15 | 87ecb68b | pbrook | #include "i2c.h" |
16 | 87ecb68b | pbrook | #include "flash.h" |
17 | 87ecb68b | pbrook | #include "qemu-timer.h" |
18 | 87ecb68b | pbrook | #include "devices.h" |
19 | e33d8cdb | balrog | #include "sharpsl.h" |
20 | 87ecb68b | pbrook | #include "console.h" |
21 | 87ecb68b | pbrook | #include "block.h" |
22 | 87ecb68b | pbrook | #include "audio/audio.h" |
23 | 87ecb68b | pbrook | #include "boards.h" |
24 | b00052e4 | balrog | |
25 | b00052e4 | balrog | #undef REG_FMT
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26 | 444ce241 | bellard | #if TARGET_PHYS_ADDR_BITS == 32 |
27 | 444ce241 | bellard | #define REG_FMT "0x%02x" |
28 | 444ce241 | bellard | #else
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29 | b00052e4 | balrog | #define REG_FMT "0x%02lx" |
30 | 444ce241 | bellard | #endif
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31 | b00052e4 | balrog | |
32 | b00052e4 | balrog | /* Spitz Flash */
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33 | b00052e4 | balrog | #define FLASH_BASE 0x0c000000 |
34 | b00052e4 | balrog | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ |
35 | b00052e4 | balrog | #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ |
36 | b00052e4 | balrog | #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ |
37 | b00052e4 | balrog | #define FLASH_ECCCNTR 0x0c /* ECC byte counter */ |
38 | b00052e4 | balrog | #define FLASH_ECCCLRR 0x10 /* Clear ECC */ |
39 | b00052e4 | balrog | #define FLASH_FLASHIO 0x14 /* Flash I/O */ |
40 | b00052e4 | balrog | #define FLASH_FLASHCTL 0x18 /* Flash Control */ |
41 | b00052e4 | balrog | |
42 | b00052e4 | balrog | #define FLASHCTL_CE0 (1 << 0) |
43 | b00052e4 | balrog | #define FLASHCTL_CLE (1 << 1) |
44 | b00052e4 | balrog | #define FLASHCTL_ALE (1 << 2) |
45 | b00052e4 | balrog | #define FLASHCTL_WP (1 << 3) |
46 | b00052e4 | balrog | #define FLASHCTL_CE1 (1 << 4) |
47 | b00052e4 | balrog | #define FLASHCTL_RYBY (1 << 5) |
48 | b00052e4 | balrog | #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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49 | b00052e4 | balrog | |
50 | b00052e4 | balrog | struct sl_nand_s {
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51 | b00052e4 | balrog | struct nand_flash_s *nand;
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52 | b00052e4 | balrog | uint8_t ctl; |
53 | b00052e4 | balrog | struct ecc_state_s ecc;
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54 | b00052e4 | balrog | }; |
55 | b00052e4 | balrog | |
56 | b00052e4 | balrog | static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
57 | b00052e4 | balrog | { |
58 | b00052e4 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
59 | b00052e4 | balrog | int ryby;
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60 | b00052e4 | balrog | |
61 | b00052e4 | balrog | switch (addr) {
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62 | b00052e4 | balrog | #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) |
63 | b00052e4 | balrog | case FLASH_ECCLPLB:
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64 | b00052e4 | balrog | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | |
65 | b00052e4 | balrog | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); |
66 | b00052e4 | balrog | |
67 | b00052e4 | balrog | #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) |
68 | b00052e4 | balrog | case FLASH_ECCLPUB:
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69 | b00052e4 | balrog | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | |
70 | b00052e4 | balrog | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); |
71 | b00052e4 | balrog | |
72 | b00052e4 | balrog | case FLASH_ECCCP:
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73 | b00052e4 | balrog | return s->ecc.cp;
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74 | b00052e4 | balrog | |
75 | b00052e4 | balrog | case FLASH_ECCCNTR:
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76 | b00052e4 | balrog | return s->ecc.count & 0xff; |
77 | b00052e4 | balrog | |
78 | b00052e4 | balrog | case FLASH_FLASHCTL:
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79 | b00052e4 | balrog | nand_getpins(s->nand, &ryby); |
80 | b00052e4 | balrog | if (ryby)
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81 | b00052e4 | balrog | return s->ctl | FLASHCTL_RYBY;
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82 | b00052e4 | balrog | else
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83 | b00052e4 | balrog | return s->ctl;
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84 | b00052e4 | balrog | |
85 | b00052e4 | balrog | case FLASH_FLASHIO:
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86 | b00052e4 | balrog | return ecc_digest(&s->ecc, nand_getio(s->nand));
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87 | b00052e4 | balrog | |
88 | b00052e4 | balrog | default:
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89 | 89cdb6af | balrog | zaurus_printf("Bad register offset " REG_FMT "\n", addr); |
90 | b00052e4 | balrog | } |
91 | b00052e4 | balrog | return 0; |
92 | b00052e4 | balrog | } |
93 | b00052e4 | balrog | |
94 | a5236105 | balrog | static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
95 | a5236105 | balrog | { |
96 | a5236105 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
97 | a5236105 | balrog | |
98 | a5236105 | balrog | if (addr == FLASH_FLASHIO)
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99 | a5236105 | balrog | return ecc_digest(&s->ecc, nand_getio(s->nand)) |
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100 | a5236105 | balrog | (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
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101 | a5236105 | balrog | |
102 | a5236105 | balrog | return sl_readb(opaque, addr);
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103 | a5236105 | balrog | } |
104 | a5236105 | balrog | |
105 | b00052e4 | balrog | static void sl_writeb(void *opaque, target_phys_addr_t addr, |
106 | b00052e4 | balrog | uint32_t value) |
107 | b00052e4 | balrog | { |
108 | b00052e4 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
109 | b00052e4 | balrog | |
110 | b00052e4 | balrog | switch (addr) {
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111 | b00052e4 | balrog | case FLASH_ECCCLRR:
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112 | b00052e4 | balrog | /* Value is ignored. */
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113 | b00052e4 | balrog | ecc_reset(&s->ecc); |
114 | b00052e4 | balrog | break;
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115 | b00052e4 | balrog | |
116 | b00052e4 | balrog | case FLASH_FLASHCTL:
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117 | b00052e4 | balrog | s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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118 | b00052e4 | balrog | nand_setpins(s->nand, |
119 | b00052e4 | balrog | s->ctl & FLASHCTL_CLE, |
120 | b00052e4 | balrog | s->ctl & FLASHCTL_ALE, |
121 | b00052e4 | balrog | s->ctl & FLASHCTL_NCE, |
122 | b00052e4 | balrog | s->ctl & FLASHCTL_WP, |
123 | b00052e4 | balrog | 0);
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124 | b00052e4 | balrog | break;
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125 | b00052e4 | balrog | |
126 | b00052e4 | balrog | case FLASH_FLASHIO:
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127 | b00052e4 | balrog | nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
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128 | b00052e4 | balrog | break;
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129 | b00052e4 | balrog | |
130 | b00052e4 | balrog | default:
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131 | 89cdb6af | balrog | zaurus_printf("Bad register offset " REG_FMT "\n", addr); |
132 | b00052e4 | balrog | } |
133 | b00052e4 | balrog | } |
134 | b00052e4 | balrog | |
135 | aa941b94 | balrog | static void sl_save(QEMUFile *f, void *opaque) |
136 | aa941b94 | balrog | { |
137 | aa941b94 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
138 | aa941b94 | balrog | |
139 | aa941b94 | balrog | qemu_put_8s(f, &s->ctl); |
140 | aa941b94 | balrog | ecc_put(f, &s->ecc); |
141 | aa941b94 | balrog | } |
142 | aa941b94 | balrog | |
143 | aa941b94 | balrog | static int sl_load(QEMUFile *f, void *opaque, int version_id) |
144 | aa941b94 | balrog | { |
145 | aa941b94 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
146 | aa941b94 | balrog | |
147 | aa941b94 | balrog | qemu_get_8s(f, &s->ctl); |
148 | aa941b94 | balrog | ecc_get(f, &s->ecc); |
149 | aa941b94 | balrog | |
150 | aa941b94 | balrog | return 0; |
151 | aa941b94 | balrog | } |
152 | aa941b94 | balrog | |
153 | b00052e4 | balrog | enum {
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154 | b00052e4 | balrog | FLASH_128M, |
155 | b00052e4 | balrog | FLASH_1024M, |
156 | b00052e4 | balrog | }; |
157 | b00052e4 | balrog | |
158 | b00052e4 | balrog | static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) |
159 | b00052e4 | balrog | { |
160 | b00052e4 | balrog | int iomemtype;
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161 | b00052e4 | balrog | struct sl_nand_s *s;
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162 | b00052e4 | balrog | CPUReadMemoryFunc *sl_readfn[] = { |
163 | b00052e4 | balrog | sl_readb, |
164 | b00052e4 | balrog | sl_readb, |
165 | a5236105 | balrog | sl_readl, |
166 | b00052e4 | balrog | }; |
167 | b00052e4 | balrog | CPUWriteMemoryFunc *sl_writefn[] = { |
168 | b00052e4 | balrog | sl_writeb, |
169 | b00052e4 | balrog | sl_writeb, |
170 | b00052e4 | balrog | sl_writeb, |
171 | b00052e4 | balrog | }; |
172 | b00052e4 | balrog | |
173 | b00052e4 | balrog | s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s)); |
174 | b00052e4 | balrog | s->ctl = 0;
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175 | b00052e4 | balrog | if (size == FLASH_128M)
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176 | b00052e4 | balrog | s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
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177 | b00052e4 | balrog | else if (size == FLASH_1024M) |
178 | b00052e4 | balrog | s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
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179 | b00052e4 | balrog | |
180 | b00052e4 | balrog | iomemtype = cpu_register_io_memory(0, sl_readfn,
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181 | b00052e4 | balrog | sl_writefn, s); |
182 | 8da3ff18 | pbrook | cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
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183 | aa941b94 | balrog | |
184 | aa941b94 | balrog | register_savevm("sl_flash", 0, 0, sl_save, sl_load, s); |
185 | b00052e4 | balrog | } |
186 | b00052e4 | balrog | |
187 | b00052e4 | balrog | /* Spitz Keyboard */
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188 | b00052e4 | balrog | |
189 | b00052e4 | balrog | #define SPITZ_KEY_STROBE_NUM 11 |
190 | b00052e4 | balrog | #define SPITZ_KEY_SENSE_NUM 7 |
191 | b00052e4 | balrog | |
192 | b00052e4 | balrog | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { |
193 | b00052e4 | balrog | 12, 17, 91, 34, 36, 38, 39 |
194 | b00052e4 | balrog | }; |
195 | b00052e4 | balrog | |
196 | b00052e4 | balrog | static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { |
197 | b00052e4 | balrog | 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 |
198 | b00052e4 | balrog | }; |
199 | b00052e4 | balrog | |
200 | b00052e4 | balrog | /* Eighth additional row maps the special keys */
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201 | b00052e4 | balrog | static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { |
202 | b00052e4 | balrog | { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, |
203 | b00052e4 | balrog | { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, |
204 | b00052e4 | balrog | { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, |
205 | b00052e4 | balrog | { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, |
206 | b00052e4 | balrog | { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, |
207 | 2b76bdc9 | balrog | { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
208 | 2b76bdc9 | balrog | { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, |
209 | b00052e4 | balrog | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
210 | b00052e4 | balrog | }; |
211 | b00052e4 | balrog | |
212 | b00052e4 | balrog | #define SPITZ_GPIO_AK_INT 13 /* Remote control */ |
213 | b00052e4 | balrog | #define SPITZ_GPIO_SYNC 16 /* Sync button */ |
214 | b00052e4 | balrog | #define SPITZ_GPIO_ON_KEY 95 /* Power button */ |
215 | b00052e4 | balrog | #define SPITZ_GPIO_SWA 97 /* Lid */ |
216 | b00052e4 | balrog | #define SPITZ_GPIO_SWB 96 /* Tablet mode */ |
217 | b00052e4 | balrog | |
218 | b00052e4 | balrog | /* The special buttons are mapped to unused keys */
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219 | b00052e4 | balrog | static const int spitz_gpiomap[5] = { |
220 | b00052e4 | balrog | SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, |
221 | b00052e4 | balrog | SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, |
222 | b00052e4 | balrog | }; |
223 | b00052e4 | balrog | static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; |
224 | b00052e4 | balrog | |
225 | b00052e4 | balrog | struct spitz_keyboard_s {
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226 | 38641a52 | balrog | qemu_irq sense[SPITZ_KEY_SENSE_NUM]; |
227 | 38641a52 | balrog | qemu_irq *strobe; |
228 | 38641a52 | balrog | qemu_irq gpiomap[5];
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229 | b00052e4 | balrog | int keymap[0x80]; |
230 | b00052e4 | balrog | uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; |
231 | b00052e4 | balrog | uint16_t strobe_state; |
232 | b00052e4 | balrog | uint16_t sense_state; |
233 | b00052e4 | balrog | |
234 | b00052e4 | balrog | uint16_t pre_map[0x100];
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235 | b00052e4 | balrog | uint16_t modifiers; |
236 | b00052e4 | balrog | uint16_t imodifiers; |
237 | b00052e4 | balrog | uint8_t fifo[16];
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238 | b00052e4 | balrog | int fifopos, fifolen;
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239 | b00052e4 | balrog | QEMUTimer *kbdtimer; |
240 | b00052e4 | balrog | }; |
241 | b00052e4 | balrog | |
242 | b00052e4 | balrog | static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) |
243 | b00052e4 | balrog | { |
244 | b00052e4 | balrog | int i;
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245 | b00052e4 | balrog | uint16_t strobe, sense = 0;
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246 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { |
247 | b00052e4 | balrog | strobe = s->keyrow[i] & s->strobe_state; |
248 | b00052e4 | balrog | if (strobe) {
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249 | b00052e4 | balrog | sense |= 1 << i;
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250 | b00052e4 | balrog | if (!(s->sense_state & (1 << i))) |
251 | 38641a52 | balrog | qemu_irq_raise(s->sense[i]); |
252 | b00052e4 | balrog | } else if (s->sense_state & (1 << i)) |
253 | 38641a52 | balrog | qemu_irq_lower(s->sense[i]); |
254 | b00052e4 | balrog | } |
255 | b00052e4 | balrog | |
256 | b00052e4 | balrog | s->sense_state = sense; |
257 | b00052e4 | balrog | } |
258 | b00052e4 | balrog | |
259 | 38641a52 | balrog | static void spitz_keyboard_strobe(void *opaque, int line, int level) |
260 | b00052e4 | balrog | { |
261 | 38641a52 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
262 | 38641a52 | balrog | |
263 | 38641a52 | balrog | if (level)
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264 | 38641a52 | balrog | s->strobe_state |= 1 << line;
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265 | 38641a52 | balrog | else
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266 | 38641a52 | balrog | s->strobe_state &= ~(1 << line);
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267 | 38641a52 | balrog | spitz_keyboard_sense_update(s); |
268 | b00052e4 | balrog | } |
269 | b00052e4 | balrog | |
270 | b00052e4 | balrog | static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) |
271 | b00052e4 | balrog | { |
272 | b00052e4 | balrog | int spitz_keycode = s->keymap[keycode & 0x7f]; |
273 | b00052e4 | balrog | if (spitz_keycode == -1) |
274 | b00052e4 | balrog | return;
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275 | b00052e4 | balrog | |
276 | b00052e4 | balrog | /* Handle the additional keys */
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277 | b00052e4 | balrog | if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { |
278 | 38641a52 | balrog | qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^ |
279 | b00052e4 | balrog | spitz_gpio_invert[spitz_keycode & 0xf]);
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280 | b00052e4 | balrog | return;
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281 | b00052e4 | balrog | } |
282 | b00052e4 | balrog | |
283 | b00052e4 | balrog | if (keycode & 0x80) |
284 | b00052e4 | balrog | s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); |
285 | b00052e4 | balrog | else
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286 | b00052e4 | balrog | s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); |
287 | b00052e4 | balrog | |
288 | b00052e4 | balrog | spitz_keyboard_sense_update(s); |
289 | b00052e4 | balrog | } |
290 | b00052e4 | balrog | |
291 | b00052e4 | balrog | #define SHIFT (1 << 7) |
292 | b00052e4 | balrog | #define CTRL (1 << 8) |
293 | b00052e4 | balrog | #define FN (1 << 9) |
294 | b00052e4 | balrog | |
295 | b00052e4 | balrog | #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c |
296 | b00052e4 | balrog | |
297 | b00052e4 | balrog | static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) |
298 | b00052e4 | balrog | { |
299 | b00052e4 | balrog | uint16_t code; |
300 | b00052e4 | balrog | int mapcode;
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301 | b00052e4 | balrog | switch (keycode) {
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302 | b00052e4 | balrog | case 0x2a: /* Left Shift */ |
303 | b00052e4 | balrog | s->modifiers |= 1;
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304 | b00052e4 | balrog | break;
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305 | b00052e4 | balrog | case 0xaa: |
306 | b00052e4 | balrog | s->modifiers &= ~1;
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307 | b00052e4 | balrog | break;
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308 | b00052e4 | balrog | case 0x36: /* Right Shift */ |
309 | b00052e4 | balrog | s->modifiers |= 2;
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310 | b00052e4 | balrog | break;
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311 | b00052e4 | balrog | case 0xb6: |
312 | b00052e4 | balrog | s->modifiers &= ~2;
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313 | b00052e4 | balrog | break;
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314 | b00052e4 | balrog | case 0x1d: /* Control */ |
315 | b00052e4 | balrog | s->modifiers |= 4;
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316 | b00052e4 | balrog | break;
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317 | b00052e4 | balrog | case 0x9d: |
318 | b00052e4 | balrog | s->modifiers &= ~4;
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319 | b00052e4 | balrog | break;
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320 | b00052e4 | balrog | case 0x38: /* Alt */ |
321 | b00052e4 | balrog | s->modifiers |= 8;
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322 | b00052e4 | balrog | break;
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323 | b00052e4 | balrog | case 0xb8: |
324 | b00052e4 | balrog | s->modifiers &= ~8;
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325 | b00052e4 | balrog | break;
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326 | b00052e4 | balrog | } |
327 | b00052e4 | balrog | |
328 | b00052e4 | balrog | code = s->pre_map[mapcode = ((s->modifiers & 3) ?
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329 | b00052e4 | balrog | (keycode | SHIFT) : |
330 | b00052e4 | balrog | (keycode & ~SHIFT))]; |
331 | b00052e4 | balrog | |
332 | b00052e4 | balrog | if (code != mapcode) {
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333 | b00052e4 | balrog | #if 0
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334 | b00052e4 | balrog | if ((code & SHIFT) && !(s->modifiers & 1))
|
335 | b00052e4 | balrog | QUEUE_KEY(0x2a | (keycode & 0x80));
|
336 | b00052e4 | balrog | if ((code & CTRL ) && !(s->modifiers & 4))
|
337 | b00052e4 | balrog | QUEUE_KEY(0x1d | (keycode & 0x80));
|
338 | b00052e4 | balrog | if ((code & FN ) && !(s->modifiers & 8))
|
339 | b00052e4 | balrog | QUEUE_KEY(0x38 | (keycode & 0x80));
|
340 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 1))
|
341 | b00052e4 | balrog | QUEUE_KEY(0x2a | (~keycode & 0x80));
|
342 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 2))
|
343 | b00052e4 | balrog | QUEUE_KEY(0x36 | (~keycode & 0x80));
|
344 | b00052e4 | balrog | #else
|
345 | b00052e4 | balrog | if (keycode & 0x80) { |
346 | b00052e4 | balrog | if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) |
347 | b00052e4 | balrog | QUEUE_KEY(0x2a | 0x80); |
348 | b00052e4 | balrog | if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) |
349 | b00052e4 | balrog | QUEUE_KEY(0x1d | 0x80); |
350 | b00052e4 | balrog | if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) |
351 | b00052e4 | balrog | QUEUE_KEY(0x38 | 0x80); |
352 | b00052e4 | balrog | if ((s->imodifiers & 0x10) && (s->modifiers & 1)) |
353 | b00052e4 | balrog | QUEUE_KEY(0x2a);
|
354 | b00052e4 | balrog | if ((s->imodifiers & 0x20) && (s->modifiers & 2)) |
355 | b00052e4 | balrog | QUEUE_KEY(0x36);
|
356 | b00052e4 | balrog | s->imodifiers = 0;
|
357 | b00052e4 | balrog | } else {
|
358 | b00052e4 | balrog | if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { |
359 | b00052e4 | balrog | QUEUE_KEY(0x2a);
|
360 | b00052e4 | balrog | s->imodifiers |= 1;
|
361 | b00052e4 | balrog | } |
362 | b00052e4 | balrog | if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { |
363 | b00052e4 | balrog | QUEUE_KEY(0x1d);
|
364 | b00052e4 | balrog | s->imodifiers |= 4;
|
365 | b00052e4 | balrog | } |
366 | b00052e4 | balrog | if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { |
367 | b00052e4 | balrog | QUEUE_KEY(0x38);
|
368 | b00052e4 | balrog | s->imodifiers |= 8;
|
369 | b00052e4 | balrog | } |
370 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 1) && |
371 | b00052e4 | balrog | !(s->imodifiers & 0x10)) {
|
372 | b00052e4 | balrog | QUEUE_KEY(0x2a | 0x80); |
373 | b00052e4 | balrog | s->imodifiers |= 0x10;
|
374 | b00052e4 | balrog | } |
375 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 2) && |
376 | b00052e4 | balrog | !(s->imodifiers & 0x20)) {
|
377 | b00052e4 | balrog | QUEUE_KEY(0x36 | 0x80); |
378 | b00052e4 | balrog | s->imodifiers |= 0x20;
|
379 | b00052e4 | balrog | } |
380 | b00052e4 | balrog | } |
381 | b00052e4 | balrog | #endif
|
382 | b00052e4 | balrog | } |
383 | b00052e4 | balrog | |
384 | b00052e4 | balrog | QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); |
385 | b00052e4 | balrog | } |
386 | b00052e4 | balrog | |
387 | b00052e4 | balrog | static void spitz_keyboard_tick(void *opaque) |
388 | b00052e4 | balrog | { |
389 | b00052e4 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
390 | b00052e4 | balrog | |
391 | b00052e4 | balrog | if (s->fifolen) {
|
392 | b00052e4 | balrog | spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); |
393 | b00052e4 | balrog | s->fifolen --; |
394 | b00052e4 | balrog | if (s->fifopos >= 16) |
395 | b00052e4 | balrog | s->fifopos = 0;
|
396 | b00052e4 | balrog | } |
397 | b00052e4 | balrog | |
398 | b00052e4 | balrog | qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
|
399 | b00052e4 | balrog | } |
400 | b00052e4 | balrog | |
401 | b00052e4 | balrog | static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) |
402 | b00052e4 | balrog | { |
403 | b00052e4 | balrog | int i;
|
404 | b00052e4 | balrog | for (i = 0; i < 0x100; i ++) |
405 | b00052e4 | balrog | s->pre_map[i] = i; |
406 | b00052e4 | balrog | s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ |
407 | b00052e4 | balrog | s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ |
408 | b00052e4 | balrog | s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ |
409 | b00052e4 | balrog | s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ |
410 | b00052e4 | balrog | s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ |
411 | b00052e4 | balrog | s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ |
412 | b00052e4 | balrog | s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ |
413 | b00052e4 | balrog | s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ |
414 | b00052e4 | balrog | s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ |
415 | b00052e4 | balrog | s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ |
416 | b00052e4 | balrog | s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ |
417 | b00052e4 | balrog | s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ |
418 | b00052e4 | balrog | s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ |
419 | b00052e4 | balrog | s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ |
420 | b00052e4 | balrog | s->pre_map[0x0d ] = 0x12 | FN; /* equal */ |
421 | b00052e4 | balrog | s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ |
422 | b00052e4 | balrog | s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ |
423 | b00052e4 | balrog | s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ |
424 | 2b76bdc9 | balrog | s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
425 | 2b76bdc9 | balrog | s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ |
426 | b00052e4 | balrog | s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
427 | b00052e4 | balrog | s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ |
428 | b00052e4 | balrog | s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ |
429 | b00052e4 | balrog | s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ |
430 | b00052e4 | balrog | s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ |
431 | b00052e4 | balrog | s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ |
432 | 2b76bdc9 | balrog | s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
433 | b00052e4 | balrog | s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
434 | 2b76bdc9 | balrog | s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
435 | b00052e4 | balrog | s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
436 | b00052e4 | balrog | s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ |
437 | b00052e4 | balrog | s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ |
438 | b00052e4 | balrog | |
439 | b00052e4 | balrog | s->modifiers = 0;
|
440 | b00052e4 | balrog | s->imodifiers = 0;
|
441 | b00052e4 | balrog | s->fifopos = 0;
|
442 | b00052e4 | balrog | s->fifolen = 0;
|
443 | b00052e4 | balrog | s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); |
444 | b00052e4 | balrog | spitz_keyboard_tick(s); |
445 | b00052e4 | balrog | } |
446 | b00052e4 | balrog | |
447 | b00052e4 | balrog | #undef SHIFT
|
448 | b00052e4 | balrog | #undef CTRL
|
449 | b00052e4 | balrog | #undef FN
|
450 | b00052e4 | balrog | |
451 | aa941b94 | balrog | static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
452 | aa941b94 | balrog | { |
453 | aa941b94 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
454 | aa941b94 | balrog | int i;
|
455 | aa941b94 | balrog | |
456 | aa941b94 | balrog | qemu_put_be16s(f, &s->sense_state); |
457 | aa941b94 | balrog | qemu_put_be16s(f, &s->strobe_state); |
458 | aa941b94 | balrog | for (i = 0; i < 5; i ++) |
459 | aa941b94 | balrog | qemu_put_byte(f, spitz_gpio_invert[i]); |
460 | aa941b94 | balrog | } |
461 | aa941b94 | balrog | |
462 | aa941b94 | balrog | static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) |
463 | aa941b94 | balrog | { |
464 | aa941b94 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
465 | aa941b94 | balrog | int i;
|
466 | aa941b94 | balrog | |
467 | aa941b94 | balrog | qemu_get_be16s(f, &s->sense_state); |
468 | aa941b94 | balrog | qemu_get_be16s(f, &s->strobe_state); |
469 | aa941b94 | balrog | for (i = 0; i < 5; i ++) |
470 | aa941b94 | balrog | spitz_gpio_invert[i] = qemu_get_byte(f); |
471 | aa941b94 | balrog | |
472 | aa941b94 | balrog | /* Release all pressed keys */
|
473 | aa941b94 | balrog | memset(s->keyrow, 0, sizeof(s->keyrow)); |
474 | aa941b94 | balrog | spitz_keyboard_sense_update(s); |
475 | aa941b94 | balrog | s->modifiers = 0;
|
476 | aa941b94 | balrog | s->imodifiers = 0;
|
477 | aa941b94 | balrog | s->fifopos = 0;
|
478 | aa941b94 | balrog | s->fifolen = 0;
|
479 | aa941b94 | balrog | |
480 | aa941b94 | balrog | return 0; |
481 | aa941b94 | balrog | } |
482 | aa941b94 | balrog | |
483 | b00052e4 | balrog | static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) |
484 | b00052e4 | balrog | { |
485 | b00052e4 | balrog | int i, j;
|
486 | b00052e4 | balrog | struct spitz_keyboard_s *s;
|
487 | b00052e4 | balrog | |
488 | b00052e4 | balrog | s = (struct spitz_keyboard_s *)
|
489 | b00052e4 | balrog | qemu_mallocz(sizeof(struct spitz_keyboard_s)); |
490 | b00052e4 | balrog | memset(s, 0, sizeof(struct spitz_keyboard_s)); |
491 | b00052e4 | balrog | |
492 | b00052e4 | balrog | for (i = 0; i < 0x80; i ++) |
493 | b00052e4 | balrog | s->keymap[i] = -1;
|
494 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) |
495 | b00052e4 | balrog | for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) |
496 | b00052e4 | balrog | if (spitz_keymap[i][j] != -1) |
497 | b00052e4 | balrog | s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
|
498 | b00052e4 | balrog | |
499 | 38641a52 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) |
500 | 38641a52 | balrog | s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]]; |
501 | 38641a52 | balrog | |
502 | 38641a52 | balrog | for (i = 0; i < 5; i ++) |
503 | 38641a52 | balrog | s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]]; |
504 | 38641a52 | balrog | |
505 | 38641a52 | balrog | s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s, |
506 | 38641a52 | balrog | SPITZ_KEY_STROBE_NUM); |
507 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
508 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]); |
509 | b00052e4 | balrog | |
510 | b00052e4 | balrog | spitz_keyboard_pre_map(s); |
511 | b00052e4 | balrog | qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); |
512 | aa941b94 | balrog | |
513 | aa941b94 | balrog | register_savevm("spitz_keyboard", 0, 0, |
514 | aa941b94 | balrog | spitz_keyboard_save, spitz_keyboard_load, s); |
515 | b00052e4 | balrog | } |
516 | b00052e4 | balrog | |
517 | b00052e4 | balrog | /* LCD backlight controller */
|
518 | b00052e4 | balrog | |
519 | b00052e4 | balrog | #define LCDTG_RESCTL 0x00 |
520 | b00052e4 | balrog | #define LCDTG_PHACTRL 0x01 |
521 | b00052e4 | balrog | #define LCDTG_DUTYCTRL 0x02 |
522 | b00052e4 | balrog | #define LCDTG_POWERREG0 0x03 |
523 | b00052e4 | balrog | #define LCDTG_POWERREG1 0x04 |
524 | b00052e4 | balrog | #define LCDTG_GPOR3 0x05 |
525 | b00052e4 | balrog | #define LCDTG_PICTRL 0x06 |
526 | b00052e4 | balrog | #define LCDTG_POLCTRL 0x07 |
527 | b00052e4 | balrog | |
528 | b00052e4 | balrog | static int bl_intensity, bl_power; |
529 | b00052e4 | balrog | |
530 | b00052e4 | balrog | static void spitz_bl_update(struct pxa2xx_state_s *s) |
531 | b00052e4 | balrog | { |
532 | b00052e4 | balrog | if (bl_power && bl_intensity)
|
533 | 89cdb6af | balrog | zaurus_printf("LCD Backlight now at %i/63\n", bl_intensity);
|
534 | b00052e4 | balrog | else
|
535 | 89cdb6af | balrog | zaurus_printf("LCD Backlight now off\n");
|
536 | b00052e4 | balrog | } |
537 | b00052e4 | balrog | |
538 | 38641a52 | balrog | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
539 | b00052e4 | balrog | { |
540 | b00052e4 | balrog | int prev = bl_intensity;
|
541 | b00052e4 | balrog | |
542 | b00052e4 | balrog | if (level)
|
543 | b00052e4 | balrog | bl_intensity &= ~0x20;
|
544 | b00052e4 | balrog | else
|
545 | b00052e4 | balrog | bl_intensity |= 0x20;
|
546 | b00052e4 | balrog | |
547 | b00052e4 | balrog | if (bl_power && prev != bl_intensity)
|
548 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
549 | b00052e4 | balrog | } |
550 | b00052e4 | balrog | |
551 | 38641a52 | balrog | static inline void spitz_bl_power(void *opaque, int line, int level) |
552 | b00052e4 | balrog | { |
553 | b00052e4 | balrog | bl_power = !!level; |
554 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
555 | b00052e4 | balrog | } |
556 | b00052e4 | balrog | |
557 | b00052e4 | balrog | static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) |
558 | b00052e4 | balrog | { |
559 | b00052e4 | balrog | int addr, value;
|
560 | b00052e4 | balrog | addr = cmd >> 5;
|
561 | b00052e4 | balrog | value = cmd & 0x1f;
|
562 | b00052e4 | balrog | |
563 | b00052e4 | balrog | switch (addr) {
|
564 | b00052e4 | balrog | case LCDTG_RESCTL:
|
565 | b00052e4 | balrog | if (value)
|
566 | 89cdb6af | balrog | zaurus_printf("LCD in QVGA mode\n");
|
567 | b00052e4 | balrog | else
|
568 | 89cdb6af | balrog | zaurus_printf("LCD in VGA mode\n");
|
569 | b00052e4 | balrog | break;
|
570 | b00052e4 | balrog | |
571 | b00052e4 | balrog | case LCDTG_DUTYCTRL:
|
572 | b00052e4 | balrog | bl_intensity &= ~0x1f;
|
573 | b00052e4 | balrog | bl_intensity |= value; |
574 | b00052e4 | balrog | if (bl_power)
|
575 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
576 | b00052e4 | balrog | break;
|
577 | b00052e4 | balrog | |
578 | b00052e4 | balrog | case LCDTG_POWERREG0:
|
579 | b00052e4 | balrog | /* Set common voltage to M62332FP */
|
580 | b00052e4 | balrog | break;
|
581 | b00052e4 | balrog | } |
582 | b00052e4 | balrog | } |
583 | b00052e4 | balrog | |
584 | b00052e4 | balrog | /* SSP devices */
|
585 | b00052e4 | balrog | |
586 | b00052e4 | balrog | #define CORGI_SSP_PORT 2 |
587 | b00052e4 | balrog | |
588 | b00052e4 | balrog | #define SPITZ_GPIO_LCDCON_CS 53 |
589 | b00052e4 | balrog | #define SPITZ_GPIO_ADS7846_CS 14 |
590 | b00052e4 | balrog | #define SPITZ_GPIO_MAX1111_CS 20 |
591 | b00052e4 | balrog | #define SPITZ_GPIO_TP_INT 11 |
592 | b00052e4 | balrog | |
593 | b00052e4 | balrog | static int lcd_en, ads_en, max_en; |
594 | b00052e4 | balrog | static struct max111x_s *max1111; |
595 | b00052e4 | balrog | static struct ads7846_state_s *ads7846; |
596 | b00052e4 | balrog | |
597 | b00052e4 | balrog | /* "Demux" the signal based on current chipselect */
|
598 | b00052e4 | balrog | static uint32_t corgi_ssp_read(void *opaque) |
599 | b00052e4 | balrog | { |
600 | b00052e4 | balrog | if (lcd_en)
|
601 | b00052e4 | balrog | return 0; |
602 | b00052e4 | balrog | if (ads_en)
|
603 | b00052e4 | balrog | return ads7846_read(ads7846);
|
604 | b00052e4 | balrog | if (max_en)
|
605 | b00052e4 | balrog | return max111x_read(max1111);
|
606 | b00052e4 | balrog | return 0; |
607 | b00052e4 | balrog | } |
608 | b00052e4 | balrog | |
609 | b00052e4 | balrog | static void corgi_ssp_write(void *opaque, uint32_t value) |
610 | b00052e4 | balrog | { |
611 | b00052e4 | balrog | if (lcd_en)
|
612 | b00052e4 | balrog | spitz_lcdtg_dac_put(opaque, value); |
613 | b00052e4 | balrog | if (ads_en)
|
614 | b00052e4 | balrog | ads7846_write(ads7846, value); |
615 | b00052e4 | balrog | if (max_en)
|
616 | b00052e4 | balrog | max111x_write(max1111, value); |
617 | b00052e4 | balrog | } |
618 | b00052e4 | balrog | |
619 | 38641a52 | balrog | static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
620 | b00052e4 | balrog | { |
621 | 38641a52 | balrog | switch (line) {
|
622 | 38641a52 | balrog | case 0: |
623 | b00052e4 | balrog | lcd_en = !level; |
624 | 38641a52 | balrog | break;
|
625 | 38641a52 | balrog | case 1: |
626 | b00052e4 | balrog | ads_en = !level; |
627 | 38641a52 | balrog | break;
|
628 | 38641a52 | balrog | case 2: |
629 | b00052e4 | balrog | max_en = !level; |
630 | 38641a52 | balrog | break;
|
631 | 38641a52 | balrog | } |
632 | b00052e4 | balrog | } |
633 | b00052e4 | balrog | |
634 | b00052e4 | balrog | #define MAX1111_BATT_VOLT 1 |
635 | b00052e4 | balrog | #define MAX1111_BATT_TEMP 2 |
636 | b00052e4 | balrog | #define MAX1111_ACIN_VOLT 3 |
637 | b00052e4 | balrog | |
638 | b00052e4 | balrog | #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ |
639 | b00052e4 | balrog | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ |
640 | b00052e4 | balrog | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ |
641 | b00052e4 | balrog | |
642 | 38641a52 | balrog | static void spitz_adc_temp_on(void *opaque, int line, int level) |
643 | b00052e4 | balrog | { |
644 | b00052e4 | balrog | if (!max1111)
|
645 | b00052e4 | balrog | return;
|
646 | b00052e4 | balrog | |
647 | b00052e4 | balrog | if (level)
|
648 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); |
649 | b00052e4 | balrog | else
|
650 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
651 | b00052e4 | balrog | } |
652 | b00052e4 | balrog | |
653 | aa941b94 | balrog | static void spitz_ssp_save(QEMUFile *f, void *opaque) |
654 | aa941b94 | balrog | { |
655 | aa941b94 | balrog | qemu_put_be32(f, lcd_en); |
656 | aa941b94 | balrog | qemu_put_be32(f, ads_en); |
657 | aa941b94 | balrog | qemu_put_be32(f, max_en); |
658 | aa941b94 | balrog | qemu_put_be32(f, bl_intensity); |
659 | aa941b94 | balrog | qemu_put_be32(f, bl_power); |
660 | aa941b94 | balrog | } |
661 | aa941b94 | balrog | |
662 | aa941b94 | balrog | static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) |
663 | aa941b94 | balrog | { |
664 | aa941b94 | balrog | lcd_en = qemu_get_be32(f); |
665 | aa941b94 | balrog | ads_en = qemu_get_be32(f); |
666 | aa941b94 | balrog | max_en = qemu_get_be32(f); |
667 | aa941b94 | balrog | bl_intensity = qemu_get_be32(f); |
668 | aa941b94 | balrog | bl_power = qemu_get_be32(f); |
669 | aa941b94 | balrog | |
670 | aa941b94 | balrog | return 0; |
671 | aa941b94 | balrog | } |
672 | aa941b94 | balrog | |
673 | b00052e4 | balrog | static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) |
674 | b00052e4 | balrog | { |
675 | 38641a52 | balrog | qemu_irq *chipselects; |
676 | 38641a52 | balrog | |
677 | b00052e4 | balrog | lcd_en = ads_en = max_en = 0;
|
678 | b00052e4 | balrog | |
679 | 38641a52 | balrog | ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]); |
680 | b00052e4 | balrog | |
681 | b00052e4 | balrog | max1111 = max1111_init(0);
|
682 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
683 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
684 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); |
685 | b00052e4 | balrog | |
686 | b00052e4 | balrog | pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
|
687 | b00052e4 | balrog | corgi_ssp_write, cpu); |
688 | b00052e4 | balrog | |
689 | 38641a52 | balrog | chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
|
690 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
|
691 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
|
692 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
|
693 | b00052e4 | balrog | |
694 | b00052e4 | balrog | bl_intensity = 0x20;
|
695 | b00052e4 | balrog | bl_power = 0;
|
696 | aa941b94 | balrog | |
697 | aa941b94 | balrog | register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu); |
698 | b00052e4 | balrog | } |
699 | b00052e4 | balrog | |
700 | b00052e4 | balrog | /* CF Microdrive */
|
701 | b00052e4 | balrog | |
702 | 15b18ec2 | balrog | static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu, int slot) |
703 | b00052e4 | balrog | { |
704 | b00052e4 | balrog | struct pcmcia_card_s *md;
|
705 | e4bcb14c | ths | int index;
|
706 | e4bcb14c | ths | BlockDriverState *bs; |
707 | b00052e4 | balrog | |
708 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 0, 0); |
709 | e4bcb14c | ths | if (index == -1) |
710 | e4bcb14c | ths | return;
|
711 | e4bcb14c | ths | bs = drives_table[index].bdrv; |
712 | e4bcb14c | ths | if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
|
713 | b00052e4 | balrog | md = dscm1xxxx_init(bs); |
714 | 15b18ec2 | balrog | pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md); |
715 | b00052e4 | balrog | } |
716 | b00052e4 | balrog | } |
717 | b00052e4 | balrog | |
718 | adb86c37 | balrog | /* Wm8750 and Max7310 on I2C */
|
719 | adb86c37 | balrog | |
720 | adb86c37 | balrog | #define AKITA_MAX_ADDR 0x18 |
721 | 611d7189 | balrog | #define SPITZ_WM_ADDRL 0x1b |
722 | 611d7189 | balrog | #define SPITZ_WM_ADDRH 0x1a |
723 | adb86c37 | balrog | |
724 | adb86c37 | balrog | #define SPITZ_GPIO_WM 5 |
725 | adb86c37 | balrog | |
726 | adb86c37 | balrog | #ifdef HAS_AUDIO
|
727 | 38641a52 | balrog | static void spitz_wm8750_addr(void *opaque, int line, int level) |
728 | adb86c37 | balrog | { |
729 | adb86c37 | balrog | i2c_slave *wm = (i2c_slave *) opaque; |
730 | adb86c37 | balrog | if (level)
|
731 | adb86c37 | balrog | i2c_set_slave_address(wm, SPITZ_WM_ADDRH); |
732 | adb86c37 | balrog | else
|
733 | adb86c37 | balrog | i2c_set_slave_address(wm, SPITZ_WM_ADDRL); |
734 | adb86c37 | balrog | } |
735 | adb86c37 | balrog | #endif
|
736 | adb86c37 | balrog | |
737 | adb86c37 | balrog | static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) |
738 | adb86c37 | balrog | { |
739 | adb86c37 | balrog | /* Attach the CPU on one end of our I2C bus. */
|
740 | adb86c37 | balrog | i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
|
741 | adb86c37 | balrog | |
742 | adb86c37 | balrog | #ifdef HAS_AUDIO
|
743 | adb86c37 | balrog | AudioState *audio; |
744 | adb86c37 | balrog | i2c_slave *wm; |
745 | adb86c37 | balrog | |
746 | adb86c37 | balrog | audio = AUD_init(); |
747 | adb86c37 | balrog | if (!audio)
|
748 | adb86c37 | balrog | return;
|
749 | adb86c37 | balrog | /* Attach a WM8750 to the bus */
|
750 | adb86c37 | balrog | wm = wm8750_init(bus, audio); |
751 | adb86c37 | balrog | |
752 | 38641a52 | balrog | spitz_wm8750_addr(wm, 0, 0); |
753 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM, |
754 | 38641a52 | balrog | qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]); |
755 | adb86c37 | balrog | /* .. and to the sound interface. */
|
756 | adb86c37 | balrog | cpu->i2s->opaque = wm; |
757 | adb86c37 | balrog | cpu->i2s->codec_out = wm8750_dac_dat; |
758 | adb86c37 | balrog | cpu->i2s->codec_in = wm8750_adc_dat; |
759 | adb86c37 | balrog | wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); |
760 | adb86c37 | balrog | #endif
|
761 | adb86c37 | balrog | } |
762 | adb86c37 | balrog | |
763 | adb86c37 | balrog | static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu) |
764 | adb86c37 | balrog | { |
765 | adb86c37 | balrog | /* Attach a Max7310 to Akita I2C bus. */
|
766 | adb86c37 | balrog | i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
|
767 | adb86c37 | balrog | AKITA_MAX_ADDR); |
768 | adb86c37 | balrog | } |
769 | adb86c37 | balrog | |
770 | b00052e4 | balrog | /* Other peripherals */
|
771 | b00052e4 | balrog | |
772 | 38641a52 | balrog | static void spitz_out_switch(void *opaque, int line, int level) |
773 | b00052e4 | balrog | { |
774 | 38641a52 | balrog | switch (line) {
|
775 | 38641a52 | balrog | case 0: |
776 | 89cdb6af | balrog | zaurus_printf("Charging %s.\n", level ? "off" : "on"); |
777 | 38641a52 | balrog | break;
|
778 | 38641a52 | balrog | case 1: |
779 | 89cdb6af | balrog | zaurus_printf("Discharging %s.\n", level ? "on" : "off"); |
780 | 38641a52 | balrog | break;
|
781 | 38641a52 | balrog | case 2: |
782 | 89cdb6af | balrog | zaurus_printf("Green LED %s.\n", level ? "on" : "off"); |
783 | 38641a52 | balrog | break;
|
784 | 38641a52 | balrog | case 3: |
785 | 89cdb6af | balrog | zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); |
786 | 38641a52 | balrog | break;
|
787 | 38641a52 | balrog | case 4: |
788 | 38641a52 | balrog | spitz_bl_bit5(opaque, line, level); |
789 | 38641a52 | balrog | break;
|
790 | 38641a52 | balrog | case 5: |
791 | 38641a52 | balrog | spitz_bl_power(opaque, line, level); |
792 | 38641a52 | balrog | break;
|
793 | 38641a52 | balrog | case 6: |
794 | 38641a52 | balrog | spitz_adc_temp_on(opaque, line, level); |
795 | 38641a52 | balrog | break;
|
796 | 38641a52 | balrog | } |
797 | b00052e4 | balrog | } |
798 | b00052e4 | balrog | |
799 | b00052e4 | balrog | #define SPITZ_SCP_LED_GREEN 1 |
800 | b00052e4 | balrog | #define SPITZ_SCP_JK_B 2 |
801 | b00052e4 | balrog | #define SPITZ_SCP_CHRG_ON 3 |
802 | b00052e4 | balrog | #define SPITZ_SCP_MUTE_L 4 |
803 | b00052e4 | balrog | #define SPITZ_SCP_MUTE_R 5 |
804 | b00052e4 | balrog | #define SPITZ_SCP_CF_POWER 6 |
805 | b00052e4 | balrog | #define SPITZ_SCP_LED_ORANGE 7 |
806 | b00052e4 | balrog | #define SPITZ_SCP_JK_A 8 |
807 | b00052e4 | balrog | #define SPITZ_SCP_ADC_TEMP_ON 9 |
808 | b00052e4 | balrog | #define SPITZ_SCP2_IR_ON 1 |
809 | b00052e4 | balrog | #define SPITZ_SCP2_AKIN_PULLUP 2 |
810 | b00052e4 | balrog | #define SPITZ_SCP2_BACKLIGHT_CONT 7 |
811 | b00052e4 | balrog | #define SPITZ_SCP2_BACKLIGHT_ON 8 |
812 | b00052e4 | balrog | #define SPITZ_SCP2_MIC_BIAS 9 |
813 | b00052e4 | balrog | |
814 | b00052e4 | balrog | static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu, |
815 | e33d8cdb | balrog | struct scoop_info_s *scp0, struct scoop_info_s *scp1) |
816 | b00052e4 | balrog | { |
817 | 38641a52 | balrog | qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
|
818 | 38641a52 | balrog | |
819 | e33d8cdb | balrog | scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
|
820 | e33d8cdb | balrog | scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
|
821 | e33d8cdb | balrog | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
|
822 | e33d8cdb | balrog | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
|
823 | b00052e4 | balrog | |
824 | e33d8cdb | balrog | if (scp1) {
|
825 | e33d8cdb | balrog | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
|
826 | e33d8cdb | balrog | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
|
827 | b00052e4 | balrog | } |
828 | b00052e4 | balrog | |
829 | e33d8cdb | balrog | scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
|
830 | b00052e4 | balrog | } |
831 | b00052e4 | balrog | |
832 | b00052e4 | balrog | #define SPITZ_GPIO_HSYNC 22 |
833 | b00052e4 | balrog | #define SPITZ_GPIO_SD_DETECT 9 |
834 | b00052e4 | balrog | #define SPITZ_GPIO_SD_WP 81 |
835 | b00052e4 | balrog | #define SPITZ_GPIO_ON_RESET 89 |
836 | b00052e4 | balrog | #define SPITZ_GPIO_BAT_COVER 90 |
837 | b00052e4 | balrog | #define SPITZ_GPIO_CF1_IRQ 105 |
838 | b00052e4 | balrog | #define SPITZ_GPIO_CF1_CD 94 |
839 | b00052e4 | balrog | #define SPITZ_GPIO_CF2_IRQ 106 |
840 | b00052e4 | balrog | #define SPITZ_GPIO_CF2_CD 93 |
841 | b00052e4 | balrog | |
842 | 38641a52 | balrog | static int spitz_hsync; |
843 | b00052e4 | balrog | |
844 | 38641a52 | balrog | static void spitz_lcd_hsync_handler(void *opaque, int line, int level) |
845 | b00052e4 | balrog | { |
846 | b00052e4 | balrog | struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
847 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); |
848 | b00052e4 | balrog | spitz_hsync ^= 1;
|
849 | b00052e4 | balrog | } |
850 | b00052e4 | balrog | |
851 | b00052e4 | balrog | static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots) |
852 | b00052e4 | balrog | { |
853 | 38641a52 | balrog | qemu_irq lcd_hsync; |
854 | b00052e4 | balrog | /*
|
855 | b00052e4 | balrog | * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
|
856 | b00052e4 | balrog | * read to satisfy broken guests that poll-wait for hsync.
|
857 | b00052e4 | balrog | * Simulating a real hsync event would be less practical and
|
858 | b00052e4 | balrog | * wouldn't guarantee that a guest ever exits the loop.
|
859 | b00052e4 | balrog | */
|
860 | b00052e4 | balrog | spitz_hsync = 0;
|
861 | 38641a52 | balrog | lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0]; |
862 | 38641a52 | balrog | pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync); |
863 | 38641a52 | balrog | pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync); |
864 | b00052e4 | balrog | |
865 | b00052e4 | balrog | /* MMC/SD host */
|
866 | 02ce600c | balrog | pxa2xx_mmci_handlers(cpu->mmc, |
867 | 02ce600c | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], |
868 | 02ce600c | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]); |
869 | b00052e4 | balrog | |
870 | b00052e4 | balrog | /* Battery lock always closed */
|
871 | 38641a52 | balrog | qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]); |
872 | b00052e4 | balrog | |
873 | b00052e4 | balrog | /* Handle reset */
|
874 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); |
875 | b00052e4 | balrog | |
876 | b00052e4 | balrog | /* PCMCIA signals: card's IRQ and Card-Detect */
|
877 | b00052e4 | balrog | if (slots >= 1) |
878 | 38641a52 | balrog | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
|
879 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ], |
880 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]); |
881 | b00052e4 | balrog | if (slots >= 2) |
882 | 38641a52 | balrog | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
|
883 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ], |
884 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]); |
885 | b00052e4 | balrog | |
886 | b00052e4 | balrog | /* Initialise the screen rotation related signals */
|
887 | b00052e4 | balrog | spitz_gpio_invert[3] = 0; /* Always open */ |
888 | b00052e4 | balrog | if (graphic_rotate) { /* Tablet mode */ |
889 | b00052e4 | balrog | spitz_gpio_invert[4] = 0; |
890 | b00052e4 | balrog | } else { /* Portrait mode */ |
891 | b00052e4 | balrog | spitz_gpio_invert[4] = 1; |
892 | b00052e4 | balrog | } |
893 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA], |
894 | 38641a52 | balrog | spitz_gpio_invert[3]);
|
895 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB], |
896 | 38641a52 | balrog | spitz_gpio_invert[4]);
|
897 | b00052e4 | balrog | } |
898 | b00052e4 | balrog | |
899 | b00052e4 | balrog | /* Board init. */
|
900 | b00052e4 | balrog | enum spitz_model_e { spitz, akita, borzoi, terrier };
|
901 | b00052e4 | balrog | |
902 | 7fb4fdcf | balrog | #define SPITZ_RAM 0x04000000 |
903 | 7fb4fdcf | balrog | #define SPITZ_ROM 0x00800000 |
904 | 7fb4fdcf | balrog | |
905 | f93eb9ff | balrog | static struct arm_boot_info spitz_binfo = { |
906 | f93eb9ff | balrog | .loader_start = PXA2XX_SDRAM_BASE, |
907 | f93eb9ff | balrog | .ram_size = 0x04000000,
|
908 | f93eb9ff | balrog | }; |
909 | f93eb9ff | balrog | |
910 | 00f82b8a | aurel32 | static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size, |
911 | b00052e4 | balrog | DisplayState *ds, const char *kernel_filename, |
912 | b00052e4 | balrog | const char *kernel_cmdline, const char *initrd_filename, |
913 | 4207117c | balrog | const char *cpu_model, enum spitz_model_e model, int arm_id) |
914 | b00052e4 | balrog | { |
915 | b00052e4 | balrog | struct pxa2xx_state_s *cpu;
|
916 | e33d8cdb | balrog | struct scoop_info_s *scp0, *scp1 = NULL; |
917 | b00052e4 | balrog | |
918 | 4207117c | balrog | if (!cpu_model)
|
919 | 4207117c | balrog | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; |
920 | b00052e4 | balrog | |
921 | d95b2f8d | balrog | /* Setup CPU & memory */
|
922 | 7fb4fdcf | balrog | if (ram_size < SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE) {
|
923 | b00052e4 | balrog | fprintf(stderr, "This platform requires %i bytes of memory\n",
|
924 | 7fb4fdcf | balrog | SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE); |
925 | b00052e4 | balrog | exit(1);
|
926 | b00052e4 | balrog | } |
927 | 7fb4fdcf | balrog | cpu = pxa270_init(spitz_binfo.ram_size, ds, cpu_model); |
928 | b00052e4 | balrog | |
929 | b00052e4 | balrog | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); |
930 | b00052e4 | balrog | |
931 | 7fb4fdcf | balrog | cpu_register_physical_memory(0, SPITZ_ROM,
|
932 | 7fb4fdcf | balrog | qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM); |
933 | b00052e4 | balrog | |
934 | b00052e4 | balrog | /* Setup peripherals */
|
935 | b00052e4 | balrog | spitz_keyboard_register(cpu); |
936 | b00052e4 | balrog | |
937 | b00052e4 | balrog | spitz_ssp_attach(cpu); |
938 | b00052e4 | balrog | |
939 | e33d8cdb | balrog | scp0 = scoop_init(cpu, 0, 0x10800000); |
940 | e33d8cdb | balrog | if (model != akita) {
|
941 | e33d8cdb | balrog | scp1 = scoop_init(cpu, 1, 0x08800040); |
942 | e33d8cdb | balrog | } |
943 | b00052e4 | balrog | |
944 | e33d8cdb | balrog | spitz_scoop_gpio_setup(cpu, scp0, scp1); |
945 | b00052e4 | balrog | |
946 | b00052e4 | balrog | spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); |
947 | b00052e4 | balrog | |
948 | adb86c37 | balrog | spitz_i2c_setup(cpu); |
949 | adb86c37 | balrog | |
950 | adb86c37 | balrog | if (model == akita)
|
951 | adb86c37 | balrog | spitz_akita_i2c_setup(cpu); |
952 | adb86c37 | balrog | |
953 | b00052e4 | balrog | if (model == terrier)
|
954 | bf5ee248 | balrog | /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
|
955 | 15b18ec2 | balrog | spitz_microdrive_attach(cpu, 1);
|
956 | b00052e4 | balrog | else if (model != akita) |
957 | 15b18ec2 | balrog | /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
|
958 | 15b18ec2 | balrog | spitz_microdrive_attach(cpu, 0);
|
959 | b00052e4 | balrog | |
960 | b00052e4 | balrog | /* Setup initial (reset) machine state */
|
961 | f93eb9ff | balrog | cpu->env->regs[15] = spitz_binfo.loader_start;
|
962 | b00052e4 | balrog | |
963 | f93eb9ff | balrog | spitz_binfo.kernel_filename = kernel_filename; |
964 | f93eb9ff | balrog | spitz_binfo.kernel_cmdline = kernel_cmdline; |
965 | f93eb9ff | balrog | spitz_binfo.initrd_filename = initrd_filename; |
966 | f93eb9ff | balrog | spitz_binfo.board_id = arm_id; |
967 | f93eb9ff | balrog | arm_load_kernel(cpu->env, &spitz_binfo); |
968 | d95b2f8d | balrog | sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE); |
969 | b00052e4 | balrog | } |
970 | b00052e4 | balrog | |
971 | 00f82b8a | aurel32 | static void spitz_init(ram_addr_t ram_size, int vga_ram_size, |
972 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
973 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
974 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
975 | b00052e4 | balrog | { |
976 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
977 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
|
978 | b00052e4 | balrog | } |
979 | b00052e4 | balrog | |
980 | 00f82b8a | aurel32 | static void borzoi_init(ram_addr_t ram_size, int vga_ram_size, |
981 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
982 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
983 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
984 | b00052e4 | balrog | { |
985 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
986 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
|
987 | b00052e4 | balrog | } |
988 | b00052e4 | balrog | |
989 | 00f82b8a | aurel32 | static void akita_init(ram_addr_t ram_size, int vga_ram_size, |
990 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
991 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
992 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
993 | b00052e4 | balrog | { |
994 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
995 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
|
996 | b00052e4 | balrog | } |
997 | b00052e4 | balrog | |
998 | 00f82b8a | aurel32 | static void terrier_init(ram_addr_t ram_size, int vga_ram_size, |
999 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
1000 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1001 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
1002 | b00052e4 | balrog | { |
1003 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1004 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
|
1005 | b00052e4 | balrog | } |
1006 | b00052e4 | balrog | |
1007 | b00052e4 | balrog | QEMUMachine akitapda_machine = { |
1008 | 4b32e168 | aliguori | .name = "akita",
|
1009 | 4b32e168 | aliguori | .desc = "Akita PDA (PXA270)",
|
1010 | 4b32e168 | aliguori | .init = akita_init, |
1011 | 4b32e168 | aliguori | .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED, |
1012 | b00052e4 | balrog | }; |
1013 | b00052e4 | balrog | |
1014 | b00052e4 | balrog | QEMUMachine spitzpda_machine = { |
1015 | 4b32e168 | aliguori | .name = "spitz",
|
1016 | 4b32e168 | aliguori | .desc = "Spitz PDA (PXA270)",
|
1017 | 4b32e168 | aliguori | .init = spitz_init, |
1018 | 4b32e168 | aliguori | .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED, |
1019 | b00052e4 | balrog | }; |
1020 | b00052e4 | balrog | |
1021 | b00052e4 | balrog | QEMUMachine borzoipda_machine = { |
1022 | 4b32e168 | aliguori | .name = "borzoi",
|
1023 | 4b32e168 | aliguori | .desc = "Borzoi PDA (PXA270)",
|
1024 | 4b32e168 | aliguori | .init = borzoi_init, |
1025 | 4b32e168 | aliguori | .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED, |
1026 | b00052e4 | balrog | }; |
1027 | b00052e4 | balrog | |
1028 | b00052e4 | balrog | QEMUMachine terrierpda_machine = { |
1029 | 4b32e168 | aliguori | .name = "terrier",
|
1030 | 4b32e168 | aliguori | .desc = "Terrier PDA (PXA270)",
|
1031 | 4b32e168 | aliguori | .init = terrier_init, |
1032 | 4b32e168 | aliguori | .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED, |
1033 | b00052e4 | balrog | }; |