root / hw / ppc405_uc.c @ 475dc65f
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/*
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* QEMU PowerPC 405 embedded processors emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc405.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "qemu-log.h" |
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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#define DEBUG_GPIO
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#define DEBUG_SERIAL
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#define DEBUG_OCM
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//#define DEBUG_I2C
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#define DEBUG_GPT
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#define DEBUG_MAL
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#define DEBUG_CLOCKS
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//#define DEBUG_CLOCKS_LL
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
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uint32_t flags) |
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{ |
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ram_addr_t bdloc; |
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int i, n;
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/* We put the bd structure at the top of memory */
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if (bd->bi_memsize >= 0x01000000UL) |
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bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
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else
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bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
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stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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for (i = 0; i < 4; i++) |
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stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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for (i = 0; i < 32; i++) |
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stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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n = 0x6A;
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if (flags & 0x00000001) { |
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for (i = 0; i < 6; i++) |
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stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); |
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} |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); |
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n += 4;
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for (i = 0; i < 2; i++) { |
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stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); |
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n += 4;
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} |
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return bdloc;
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} |
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/*****************************************************************************/
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/* Shared peripherals */
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/*****************************************************************************/
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/* Peripheral local bus arbitrer */
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enum {
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PLB0_BESR = 0x084,
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PLB0_BEAR = 0x086,
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PLB0_ACR = 0x087,
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}; |
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typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
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struct ppc4xx_plb_t {
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uint32_t acr; |
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uint32_t bear; |
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uint32_t besr; |
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}; |
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static target_ulong dcr_read_plb (void *opaque, int dcrn) |
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{ |
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ppc4xx_plb_t *plb; |
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target_ulong ret; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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ret = plb->acr; |
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break;
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case PLB0_BEAR:
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ret = plb->bear; |
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break;
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case PLB0_BESR:
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ret = plb->besr; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
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{ |
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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/* We don't care about the actual parameters written as
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* we don't manage any priorities on the bus
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*/
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plb->acr = val & 0xF8000000;
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break;
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case PLB0_BEAR:
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/* Read only */
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break;
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case PLB0_BESR:
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/* Write-clear */
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plb->besr &= ~val; |
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break;
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} |
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} |
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static void ppc4xx_plb_reset (void *opaque) |
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{ |
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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plb->acr = 0x00000000;
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plb->bear = 0x00000000;
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plb->besr = 0x00000000;
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} |
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void ppc4xx_plb_init (CPUState *env)
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{ |
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ppc4xx_plb_t *plb; |
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plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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if (plb != NULL) { |
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc4xx_plb_reset(plb); |
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qemu_register_reset(ppc4xx_plb_reset, plb); |
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} |
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} |
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/*****************************************************************************/
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/* PLB to OPB bridge */
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enum {
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POB0_BESR0 = 0x0A0,
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POB0_BESR1 = 0x0A2,
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POB0_BEAR = 0x0A4,
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}; |
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typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
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struct ppc4xx_pob_t {
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uint32_t bear; |
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uint32_t besr[2];
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}; |
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static target_ulong dcr_read_pob (void *opaque, int dcrn) |
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{ |
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ppc4xx_pob_t *pob; |
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target_ulong ret; |
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pob = opaque; |
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switch (dcrn) {
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case POB0_BEAR:
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ret = pob->bear; |
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break;
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case POB0_BESR0:
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case POB0_BESR1:
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ret = pob->besr[dcrn - POB0_BESR0]; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
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{ |
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ppc4xx_pob_t *pob; |
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pob = opaque; |
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switch (dcrn) {
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case POB0_BEAR:
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/* Read only */
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break;
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case POB0_BESR0:
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case POB0_BESR1:
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/* Write-clear */
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pob->besr[dcrn - POB0_BESR0] &= ~val; |
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break;
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} |
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} |
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static void ppc4xx_pob_reset (void *opaque) |
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{ |
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ppc4xx_pob_t *pob; |
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pob = opaque; |
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/* No error */
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pob->bear = 0x00000000;
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pob->besr[0] = 0x0000000; |
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pob->besr[1] = 0x0000000; |
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} |
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void ppc4xx_pob_init (CPUState *env)
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{ |
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ppc4xx_pob_t *pob; |
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pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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if (pob != NULL) { |
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ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
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qemu_register_reset(ppc4xx_pob_reset, pob); |
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ppc4xx_pob_reset(env); |
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} |
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} |
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/*****************************************************************************/
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/* OPB arbitrer */
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typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
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struct ppc4xx_opba_t {
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target_phys_addr_t base; |
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uint8_t cr; |
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uint8_t pr; |
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}; |
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static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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ppc4xx_opba_t *opba; |
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uint32_t ret; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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opba = opaque; |
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switch (addr - opba->base) {
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case 0x00: |
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ret = opba->cr; |
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break;
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case 0x01: |
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ret = opba->pr; |
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break;
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default:
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ret = 0x00;
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break;
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} |
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return ret;
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} |
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static void opba_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ppc4xx_opba_t *opba; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
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#endif
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opba = opaque; |
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switch (addr - opba->base) {
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case 0x00: |
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opba->cr = value & 0xF8;
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break;
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case 0x01: |
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opba->pr = value & 0xFF;
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break;
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default:
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break;
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} |
312 |
} |
313 |
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static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr); |
320 |
#endif
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ret = opba_readb(opaque, addr) << 8;
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ret |= opba_readb(opaque, addr + 1);
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return ret;
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} |
326 |
|
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static void opba_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
329 |
{ |
330 |
#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
332 |
#endif
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opba_writeb(opaque, addr, value >> 8);
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opba_writeb(opaque, addr + 1, value);
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} |
336 |
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static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
338 |
{ |
339 |
uint32_t ret; |
340 |
|
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr); |
343 |
#endif
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344 |
ret = opba_readb(opaque, addr) << 24;
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ret |= opba_readb(opaque, addr + 1) << 16; |
346 |
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347 |
return ret;
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} |
349 |
|
350 |
static void opba_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
352 |
{ |
353 |
#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
355 |
#endif
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opba_writeb(opaque, addr, value >> 24);
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opba_writeb(opaque, addr + 1, value >> 16); |
358 |
} |
359 |
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360 |
static CPUReadMemoryFunc *opba_read[] = {
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361 |
&opba_readb, |
362 |
&opba_readw, |
363 |
&opba_readl, |
364 |
}; |
365 |
|
366 |
static CPUWriteMemoryFunc *opba_write[] = {
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&opba_writeb, |
368 |
&opba_writew, |
369 |
&opba_writel, |
370 |
}; |
371 |
|
372 |
static void ppc4xx_opba_reset (void *opaque) |
373 |
{ |
374 |
ppc4xx_opba_t *opba; |
375 |
|
376 |
opba = opaque; |
377 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
378 |
opba->pr = 0x11;
|
379 |
} |
380 |
|
381 |
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
382 |
target_phys_addr_t offset) |
383 |
{ |
384 |
ppc4xx_opba_t *opba; |
385 |
|
386 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
387 |
if (opba != NULL) { |
388 |
opba->base = offset; |
389 |
#ifdef DEBUG_OPBA
|
390 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
391 |
#endif
|
392 |
ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
393 |
opba_read, opba_write, opba); |
394 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
395 |
ppc4xx_opba_reset(opba); |
396 |
} |
397 |
} |
398 |
|
399 |
/*****************************************************************************/
|
400 |
/* Code decompression controller */
|
401 |
/* XXX: TODO */
|
402 |
|
403 |
/*****************************************************************************/
|
404 |
/* Peripheral controller */
|
405 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
406 |
struct ppc4xx_ebc_t {
|
407 |
uint32_t addr; |
408 |
uint32_t bcr[8];
|
409 |
uint32_t bap[8];
|
410 |
uint32_t bear; |
411 |
uint32_t besr0; |
412 |
uint32_t besr1; |
413 |
uint32_t cfg; |
414 |
}; |
415 |
|
416 |
enum {
|
417 |
EBC0_CFGADDR = 0x012,
|
418 |
EBC0_CFGDATA = 0x013,
|
419 |
}; |
420 |
|
421 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
422 |
{ |
423 |
ppc4xx_ebc_t *ebc; |
424 |
target_ulong ret; |
425 |
|
426 |
ebc = opaque; |
427 |
switch (dcrn) {
|
428 |
case EBC0_CFGADDR:
|
429 |
ret = ebc->addr; |
430 |
break;
|
431 |
case EBC0_CFGDATA:
|
432 |
switch (ebc->addr) {
|
433 |
case 0x00: /* B0CR */ |
434 |
ret = ebc->bcr[0];
|
435 |
break;
|
436 |
case 0x01: /* B1CR */ |
437 |
ret = ebc->bcr[1];
|
438 |
break;
|
439 |
case 0x02: /* B2CR */ |
440 |
ret = ebc->bcr[2];
|
441 |
break;
|
442 |
case 0x03: /* B3CR */ |
443 |
ret = ebc->bcr[3];
|
444 |
break;
|
445 |
case 0x04: /* B4CR */ |
446 |
ret = ebc->bcr[4];
|
447 |
break;
|
448 |
case 0x05: /* B5CR */ |
449 |
ret = ebc->bcr[5];
|
450 |
break;
|
451 |
case 0x06: /* B6CR */ |
452 |
ret = ebc->bcr[6];
|
453 |
break;
|
454 |
case 0x07: /* B7CR */ |
455 |
ret = ebc->bcr[7];
|
456 |
break;
|
457 |
case 0x10: /* B0AP */ |
458 |
ret = ebc->bap[0];
|
459 |
break;
|
460 |
case 0x11: /* B1AP */ |
461 |
ret = ebc->bap[1];
|
462 |
break;
|
463 |
case 0x12: /* B2AP */ |
464 |
ret = ebc->bap[2];
|
465 |
break;
|
466 |
case 0x13: /* B3AP */ |
467 |
ret = ebc->bap[3];
|
468 |
break;
|
469 |
case 0x14: /* B4AP */ |
470 |
ret = ebc->bap[4];
|
471 |
break;
|
472 |
case 0x15: /* B5AP */ |
473 |
ret = ebc->bap[5];
|
474 |
break;
|
475 |
case 0x16: /* B6AP */ |
476 |
ret = ebc->bap[6];
|
477 |
break;
|
478 |
case 0x17: /* B7AP */ |
479 |
ret = ebc->bap[7];
|
480 |
break;
|
481 |
case 0x20: /* BEAR */ |
482 |
ret = ebc->bear; |
483 |
break;
|
484 |
case 0x21: /* BESR0 */ |
485 |
ret = ebc->besr0; |
486 |
break;
|
487 |
case 0x22: /* BESR1 */ |
488 |
ret = ebc->besr1; |
489 |
break;
|
490 |
case 0x23: /* CFG */ |
491 |
ret = ebc->cfg; |
492 |
break;
|
493 |
default:
|
494 |
ret = 0x00000000;
|
495 |
break;
|
496 |
} |
497 |
default:
|
498 |
ret = 0x00000000;
|
499 |
break;
|
500 |
} |
501 |
|
502 |
return ret;
|
503 |
} |
504 |
|
505 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
506 |
{ |
507 |
ppc4xx_ebc_t *ebc; |
508 |
|
509 |
ebc = opaque; |
510 |
switch (dcrn) {
|
511 |
case EBC0_CFGADDR:
|
512 |
ebc->addr = val; |
513 |
break;
|
514 |
case EBC0_CFGDATA:
|
515 |
switch (ebc->addr) {
|
516 |
case 0x00: /* B0CR */ |
517 |
break;
|
518 |
case 0x01: /* B1CR */ |
519 |
break;
|
520 |
case 0x02: /* B2CR */ |
521 |
break;
|
522 |
case 0x03: /* B3CR */ |
523 |
break;
|
524 |
case 0x04: /* B4CR */ |
525 |
break;
|
526 |
case 0x05: /* B5CR */ |
527 |
break;
|
528 |
case 0x06: /* B6CR */ |
529 |
break;
|
530 |
case 0x07: /* B7CR */ |
531 |
break;
|
532 |
case 0x10: /* B0AP */ |
533 |
break;
|
534 |
case 0x11: /* B1AP */ |
535 |
break;
|
536 |
case 0x12: /* B2AP */ |
537 |
break;
|
538 |
case 0x13: /* B3AP */ |
539 |
break;
|
540 |
case 0x14: /* B4AP */ |
541 |
break;
|
542 |
case 0x15: /* B5AP */ |
543 |
break;
|
544 |
case 0x16: /* B6AP */ |
545 |
break;
|
546 |
case 0x17: /* B7AP */ |
547 |
break;
|
548 |
case 0x20: /* BEAR */ |
549 |
break;
|
550 |
case 0x21: /* BESR0 */ |
551 |
break;
|
552 |
case 0x22: /* BESR1 */ |
553 |
break;
|
554 |
case 0x23: /* CFG */ |
555 |
break;
|
556 |
default:
|
557 |
break;
|
558 |
} |
559 |
break;
|
560 |
default:
|
561 |
break;
|
562 |
} |
563 |
} |
564 |
|
565 |
static void ebc_reset (void *opaque) |
566 |
{ |
567 |
ppc4xx_ebc_t *ebc; |
568 |
int i;
|
569 |
|
570 |
ebc = opaque; |
571 |
ebc->addr = 0x00000000;
|
572 |
ebc->bap[0] = 0x7F8FFE80; |
573 |
ebc->bcr[0] = 0xFFE28000; |
574 |
for (i = 0; i < 8; i++) { |
575 |
ebc->bap[i] = 0x00000000;
|
576 |
ebc->bcr[i] = 0x00000000;
|
577 |
} |
578 |
ebc->besr0 = 0x00000000;
|
579 |
ebc->besr1 = 0x00000000;
|
580 |
ebc->cfg = 0x80400000;
|
581 |
} |
582 |
|
583 |
void ppc405_ebc_init (CPUState *env)
|
584 |
{ |
585 |
ppc4xx_ebc_t *ebc; |
586 |
|
587 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
588 |
if (ebc != NULL) { |
589 |
ebc_reset(ebc); |
590 |
qemu_register_reset(&ebc_reset, ebc); |
591 |
ppc_dcr_register(env, EBC0_CFGADDR, |
592 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
593 |
ppc_dcr_register(env, EBC0_CFGDATA, |
594 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
595 |
} |
596 |
} |
597 |
|
598 |
/*****************************************************************************/
|
599 |
/* DMA controller */
|
600 |
enum {
|
601 |
DMA0_CR0 = 0x100,
|
602 |
DMA0_CT0 = 0x101,
|
603 |
DMA0_DA0 = 0x102,
|
604 |
DMA0_SA0 = 0x103,
|
605 |
DMA0_SG0 = 0x104,
|
606 |
DMA0_CR1 = 0x108,
|
607 |
DMA0_CT1 = 0x109,
|
608 |
DMA0_DA1 = 0x10A,
|
609 |
DMA0_SA1 = 0x10B,
|
610 |
DMA0_SG1 = 0x10C,
|
611 |
DMA0_CR2 = 0x110,
|
612 |
DMA0_CT2 = 0x111,
|
613 |
DMA0_DA2 = 0x112,
|
614 |
DMA0_SA2 = 0x113,
|
615 |
DMA0_SG2 = 0x114,
|
616 |
DMA0_CR3 = 0x118,
|
617 |
DMA0_CT3 = 0x119,
|
618 |
DMA0_DA3 = 0x11A,
|
619 |
DMA0_SA3 = 0x11B,
|
620 |
DMA0_SG3 = 0x11C,
|
621 |
DMA0_SR = 0x120,
|
622 |
DMA0_SGC = 0x123,
|
623 |
DMA0_SLP = 0x125,
|
624 |
DMA0_POL = 0x126,
|
625 |
}; |
626 |
|
627 |
typedef struct ppc405_dma_t ppc405_dma_t; |
628 |
struct ppc405_dma_t {
|
629 |
qemu_irq irqs[4];
|
630 |
uint32_t cr[4];
|
631 |
uint32_t ct[4];
|
632 |
uint32_t da[4];
|
633 |
uint32_t sa[4];
|
634 |
uint32_t sg[4];
|
635 |
uint32_t sr; |
636 |
uint32_t sgc; |
637 |
uint32_t slp; |
638 |
uint32_t pol; |
639 |
}; |
640 |
|
641 |
static target_ulong dcr_read_dma (void *opaque, int dcrn) |
642 |
{ |
643 |
ppc405_dma_t *dma; |
644 |
|
645 |
dma = opaque; |
646 |
|
647 |
return 0; |
648 |
} |
649 |
|
650 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
651 |
{ |
652 |
ppc405_dma_t *dma; |
653 |
|
654 |
dma = opaque; |
655 |
} |
656 |
|
657 |
static void ppc405_dma_reset (void *opaque) |
658 |
{ |
659 |
ppc405_dma_t *dma; |
660 |
int i;
|
661 |
|
662 |
dma = opaque; |
663 |
for (i = 0; i < 4; i++) { |
664 |
dma->cr[i] = 0x00000000;
|
665 |
dma->ct[i] = 0x00000000;
|
666 |
dma->da[i] = 0x00000000;
|
667 |
dma->sa[i] = 0x00000000;
|
668 |
dma->sg[i] = 0x00000000;
|
669 |
} |
670 |
dma->sr = 0x00000000;
|
671 |
dma->sgc = 0x00000000;
|
672 |
dma->slp = 0x7C000000;
|
673 |
dma->pol = 0x00000000;
|
674 |
} |
675 |
|
676 |
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) |
677 |
{ |
678 |
ppc405_dma_t *dma; |
679 |
|
680 |
dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
681 |
if (dma != NULL) { |
682 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
683 |
ppc405_dma_reset(dma); |
684 |
qemu_register_reset(&ppc405_dma_reset, dma); |
685 |
ppc_dcr_register(env, DMA0_CR0, |
686 |
dma, &dcr_read_dma, &dcr_write_dma); |
687 |
ppc_dcr_register(env, DMA0_CT0, |
688 |
dma, &dcr_read_dma, &dcr_write_dma); |
689 |
ppc_dcr_register(env, DMA0_DA0, |
690 |
dma, &dcr_read_dma, &dcr_write_dma); |
691 |
ppc_dcr_register(env, DMA0_SA0, |
692 |
dma, &dcr_read_dma, &dcr_write_dma); |
693 |
ppc_dcr_register(env, DMA0_SG0, |
694 |
dma, &dcr_read_dma, &dcr_write_dma); |
695 |
ppc_dcr_register(env, DMA0_CR1, |
696 |
dma, &dcr_read_dma, &dcr_write_dma); |
697 |
ppc_dcr_register(env, DMA0_CT1, |
698 |
dma, &dcr_read_dma, &dcr_write_dma); |
699 |
ppc_dcr_register(env, DMA0_DA1, |
700 |
dma, &dcr_read_dma, &dcr_write_dma); |
701 |
ppc_dcr_register(env, DMA0_SA1, |
702 |
dma, &dcr_read_dma, &dcr_write_dma); |
703 |
ppc_dcr_register(env, DMA0_SG1, |
704 |
dma, &dcr_read_dma, &dcr_write_dma); |
705 |
ppc_dcr_register(env, DMA0_CR2, |
706 |
dma, &dcr_read_dma, &dcr_write_dma); |
707 |
ppc_dcr_register(env, DMA0_CT2, |
708 |
dma, &dcr_read_dma, &dcr_write_dma); |
709 |
ppc_dcr_register(env, DMA0_DA2, |
710 |
dma, &dcr_read_dma, &dcr_write_dma); |
711 |
ppc_dcr_register(env, DMA0_SA2, |
712 |
dma, &dcr_read_dma, &dcr_write_dma); |
713 |
ppc_dcr_register(env, DMA0_SG2, |
714 |
dma, &dcr_read_dma, &dcr_write_dma); |
715 |
ppc_dcr_register(env, DMA0_CR3, |
716 |
dma, &dcr_read_dma, &dcr_write_dma); |
717 |
ppc_dcr_register(env, DMA0_CT3, |
718 |
dma, &dcr_read_dma, &dcr_write_dma); |
719 |
ppc_dcr_register(env, DMA0_DA3, |
720 |
dma, &dcr_read_dma, &dcr_write_dma); |
721 |
ppc_dcr_register(env, DMA0_SA3, |
722 |
dma, &dcr_read_dma, &dcr_write_dma); |
723 |
ppc_dcr_register(env, DMA0_SG3, |
724 |
dma, &dcr_read_dma, &dcr_write_dma); |
725 |
ppc_dcr_register(env, DMA0_SR, |
726 |
dma, &dcr_read_dma, &dcr_write_dma); |
727 |
ppc_dcr_register(env, DMA0_SGC, |
728 |
dma, &dcr_read_dma, &dcr_write_dma); |
729 |
ppc_dcr_register(env, DMA0_SLP, |
730 |
dma, &dcr_read_dma, &dcr_write_dma); |
731 |
ppc_dcr_register(env, DMA0_POL, |
732 |
dma, &dcr_read_dma, &dcr_write_dma); |
733 |
} |
734 |
} |
735 |
|
736 |
/*****************************************************************************/
|
737 |
/* GPIO */
|
738 |
typedef struct ppc405_gpio_t ppc405_gpio_t; |
739 |
struct ppc405_gpio_t {
|
740 |
target_phys_addr_t base; |
741 |
uint32_t or; |
742 |
uint32_t tcr; |
743 |
uint32_t osrh; |
744 |
uint32_t osrl; |
745 |
uint32_t tsrh; |
746 |
uint32_t tsrl; |
747 |
uint32_t odr; |
748 |
uint32_t ir; |
749 |
uint32_t rr1; |
750 |
uint32_t isr1h; |
751 |
uint32_t isr1l; |
752 |
}; |
753 |
|
754 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
755 |
{ |
756 |
ppc405_gpio_t *gpio; |
757 |
|
758 |
gpio = opaque; |
759 |
#ifdef DEBUG_GPIO
|
760 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
761 |
#endif
|
762 |
|
763 |
return 0; |
764 |
} |
765 |
|
766 |
static void ppc405_gpio_writeb (void *opaque, |
767 |
target_phys_addr_t addr, uint32_t value) |
768 |
{ |
769 |
ppc405_gpio_t *gpio; |
770 |
|
771 |
gpio = opaque; |
772 |
#ifdef DEBUG_GPIO
|
773 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
774 |
#endif
|
775 |
} |
776 |
|
777 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
778 |
{ |
779 |
ppc405_gpio_t *gpio; |
780 |
|
781 |
gpio = opaque; |
782 |
#ifdef DEBUG_GPIO
|
783 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
784 |
#endif
|
785 |
|
786 |
return 0; |
787 |
} |
788 |
|
789 |
static void ppc405_gpio_writew (void *opaque, |
790 |
target_phys_addr_t addr, uint32_t value) |
791 |
{ |
792 |
ppc405_gpio_t *gpio; |
793 |
|
794 |
gpio = opaque; |
795 |
#ifdef DEBUG_GPIO
|
796 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
797 |
#endif
|
798 |
} |
799 |
|
800 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
801 |
{ |
802 |
ppc405_gpio_t *gpio; |
803 |
|
804 |
gpio = opaque; |
805 |
#ifdef DEBUG_GPIO
|
806 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
807 |
#endif
|
808 |
|
809 |
return 0; |
810 |
} |
811 |
|
812 |
static void ppc405_gpio_writel (void *opaque, |
813 |
target_phys_addr_t addr, uint32_t value) |
814 |
{ |
815 |
ppc405_gpio_t *gpio; |
816 |
|
817 |
gpio = opaque; |
818 |
#ifdef DEBUG_GPIO
|
819 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
820 |
#endif
|
821 |
} |
822 |
|
823 |
static CPUReadMemoryFunc *ppc405_gpio_read[] = {
|
824 |
&ppc405_gpio_readb, |
825 |
&ppc405_gpio_readw, |
826 |
&ppc405_gpio_readl, |
827 |
}; |
828 |
|
829 |
static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
|
830 |
&ppc405_gpio_writeb, |
831 |
&ppc405_gpio_writew, |
832 |
&ppc405_gpio_writel, |
833 |
}; |
834 |
|
835 |
static void ppc405_gpio_reset (void *opaque) |
836 |
{ |
837 |
ppc405_gpio_t *gpio; |
838 |
|
839 |
gpio = opaque; |
840 |
} |
841 |
|
842 |
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
843 |
target_phys_addr_t offset) |
844 |
{ |
845 |
ppc405_gpio_t *gpio; |
846 |
|
847 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
848 |
if (gpio != NULL) { |
849 |
gpio->base = offset; |
850 |
ppc405_gpio_reset(gpio); |
851 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
852 |
#ifdef DEBUG_GPIO
|
853 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
854 |
#endif
|
855 |
ppc4xx_mmio_register(env, mmio, offset, 0x038,
|
856 |
ppc405_gpio_read, ppc405_gpio_write, gpio); |
857 |
} |
858 |
} |
859 |
|
860 |
/*****************************************************************************/
|
861 |
/* Serial ports */
|
862 |
static CPUReadMemoryFunc *serial_mm_read[] = {
|
863 |
&serial_mm_readb, |
864 |
&serial_mm_readw, |
865 |
&serial_mm_readl, |
866 |
}; |
867 |
|
868 |
static CPUWriteMemoryFunc *serial_mm_write[] = {
|
869 |
&serial_mm_writeb, |
870 |
&serial_mm_writew, |
871 |
&serial_mm_writel, |
872 |
}; |
873 |
|
874 |
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
875 |
target_phys_addr_t offset, qemu_irq irq, |
876 |
CharDriverState *chr) |
877 |
{ |
878 |
void *serial;
|
879 |
|
880 |
#ifdef DEBUG_SERIAL
|
881 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
882 |
#endif
|
883 |
serial = serial_mm_init(offset, 0, irq, 399193, chr, 0); |
884 |
ppc4xx_mmio_register(env, mmio, offset, 0x008,
|
885 |
serial_mm_read, serial_mm_write, serial); |
886 |
} |
887 |
|
888 |
/*****************************************************************************/
|
889 |
/* On Chip Memory */
|
890 |
enum {
|
891 |
OCM0_ISARC = 0x018,
|
892 |
OCM0_ISACNTL = 0x019,
|
893 |
OCM0_DSARC = 0x01A,
|
894 |
OCM0_DSACNTL = 0x01B,
|
895 |
}; |
896 |
|
897 |
typedef struct ppc405_ocm_t ppc405_ocm_t; |
898 |
struct ppc405_ocm_t {
|
899 |
target_ulong offset; |
900 |
uint32_t isarc; |
901 |
uint32_t isacntl; |
902 |
uint32_t dsarc; |
903 |
uint32_t dsacntl; |
904 |
}; |
905 |
|
906 |
static void ocm_update_mappings (ppc405_ocm_t *ocm, |
907 |
uint32_t isarc, uint32_t isacntl, |
908 |
uint32_t dsarc, uint32_t dsacntl) |
909 |
{ |
910 |
#ifdef DEBUG_OCM
|
911 |
printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
912 |
" %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 |
913 |
" (%08" PRIx32 " %08" PRIx32 ")\n", |
914 |
isarc, isacntl, dsarc, dsacntl, |
915 |
ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
916 |
#endif
|
917 |
if (ocm->isarc != isarc ||
|
918 |
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
919 |
if (ocm->isacntl & 0x80000000) { |
920 |
/* Unmap previously assigned memory region */
|
921 |
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
922 |
cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
923 |
IO_MEM_UNASSIGNED); |
924 |
} |
925 |
if (isacntl & 0x80000000) { |
926 |
/* Map new instruction memory region */
|
927 |
#ifdef DEBUG_OCM
|
928 |
printf("OCM map ISA %08" PRIx32 "\n", isarc); |
929 |
#endif
|
930 |
cpu_register_physical_memory(isarc, 0x04000000,
|
931 |
ocm->offset | IO_MEM_RAM); |
932 |
} |
933 |
} |
934 |
if (ocm->dsarc != dsarc ||
|
935 |
(ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
936 |
if (ocm->dsacntl & 0x80000000) { |
937 |
/* Beware not to unmap the region we just mapped */
|
938 |
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
939 |
/* Unmap previously assigned memory region */
|
940 |
#ifdef DEBUG_OCM
|
941 |
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
942 |
#endif
|
943 |
cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
944 |
IO_MEM_UNASSIGNED); |
945 |
} |
946 |
} |
947 |
if (dsacntl & 0x80000000) { |
948 |
/* Beware not to remap the region we just mapped */
|
949 |
if (!(isacntl & 0x80000000) || dsarc != isarc) { |
950 |
/* Map new data memory region */
|
951 |
#ifdef DEBUG_OCM
|
952 |
printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
953 |
#endif
|
954 |
cpu_register_physical_memory(dsarc, 0x04000000,
|
955 |
ocm->offset | IO_MEM_RAM); |
956 |
} |
957 |
} |
958 |
} |
959 |
} |
960 |
|
961 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
962 |
{ |
963 |
ppc405_ocm_t *ocm; |
964 |
target_ulong ret; |
965 |
|
966 |
ocm = opaque; |
967 |
switch (dcrn) {
|
968 |
case OCM0_ISARC:
|
969 |
ret = ocm->isarc; |
970 |
break;
|
971 |
case OCM0_ISACNTL:
|
972 |
ret = ocm->isacntl; |
973 |
break;
|
974 |
case OCM0_DSARC:
|
975 |
ret = ocm->dsarc; |
976 |
break;
|
977 |
case OCM0_DSACNTL:
|
978 |
ret = ocm->dsacntl; |
979 |
break;
|
980 |
default:
|
981 |
ret = 0;
|
982 |
break;
|
983 |
} |
984 |
|
985 |
return ret;
|
986 |
} |
987 |
|
988 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
989 |
{ |
990 |
ppc405_ocm_t *ocm; |
991 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
992 |
|
993 |
ocm = opaque; |
994 |
isarc = ocm->isarc; |
995 |
dsarc = ocm->dsarc; |
996 |
isacntl = ocm->isacntl; |
997 |
dsacntl = ocm->dsacntl; |
998 |
switch (dcrn) {
|
999 |
case OCM0_ISARC:
|
1000 |
isarc = val & 0xFC000000;
|
1001 |
break;
|
1002 |
case OCM0_ISACNTL:
|
1003 |
isacntl = val & 0xC0000000;
|
1004 |
break;
|
1005 |
case OCM0_DSARC:
|
1006 |
isarc = val & 0xFC000000;
|
1007 |
break;
|
1008 |
case OCM0_DSACNTL:
|
1009 |
isacntl = val & 0xC0000000;
|
1010 |
break;
|
1011 |
} |
1012 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1013 |
ocm->isarc = isarc; |
1014 |
ocm->dsarc = dsarc; |
1015 |
ocm->isacntl = isacntl; |
1016 |
ocm->dsacntl = dsacntl; |
1017 |
} |
1018 |
|
1019 |
static void ocm_reset (void *opaque) |
1020 |
{ |
1021 |
ppc405_ocm_t *ocm; |
1022 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
1023 |
|
1024 |
ocm = opaque; |
1025 |
isarc = 0x00000000;
|
1026 |
isacntl = 0x00000000;
|
1027 |
dsarc = 0x00000000;
|
1028 |
dsacntl = 0x00000000;
|
1029 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1030 |
ocm->isarc = isarc; |
1031 |
ocm->dsarc = dsarc; |
1032 |
ocm->isacntl = isacntl; |
1033 |
ocm->dsacntl = dsacntl; |
1034 |
} |
1035 |
|
1036 |
void ppc405_ocm_init (CPUState *env, unsigned long offset) |
1037 |
{ |
1038 |
ppc405_ocm_t *ocm; |
1039 |
|
1040 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
1041 |
if (ocm != NULL) { |
1042 |
ocm->offset = offset; |
1043 |
ocm_reset(ocm); |
1044 |
qemu_register_reset(&ocm_reset, ocm); |
1045 |
ppc_dcr_register(env, OCM0_ISARC, |
1046 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1047 |
ppc_dcr_register(env, OCM0_ISACNTL, |
1048 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1049 |
ppc_dcr_register(env, OCM0_DSARC, |
1050 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1051 |
ppc_dcr_register(env, OCM0_DSACNTL, |
1052 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1053 |
} |
1054 |
} |
1055 |
|
1056 |
/*****************************************************************************/
|
1057 |
/* I2C controller */
|
1058 |
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
1059 |
struct ppc4xx_i2c_t {
|
1060 |
target_phys_addr_t base; |
1061 |
qemu_irq irq; |
1062 |
uint8_t mdata; |
1063 |
uint8_t lmadr; |
1064 |
uint8_t hmadr; |
1065 |
uint8_t cntl; |
1066 |
uint8_t mdcntl; |
1067 |
uint8_t sts; |
1068 |
uint8_t extsts; |
1069 |
uint8_t sdata; |
1070 |
uint8_t lsadr; |
1071 |
uint8_t hsadr; |
1072 |
uint8_t clkdiv; |
1073 |
uint8_t intrmsk; |
1074 |
uint8_t xfrcnt; |
1075 |
uint8_t xtcntlss; |
1076 |
uint8_t directcntl; |
1077 |
}; |
1078 |
|
1079 |
static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
1080 |
{ |
1081 |
ppc4xx_i2c_t *i2c; |
1082 |
uint32_t ret; |
1083 |
|
1084 |
#ifdef DEBUG_I2C
|
1085 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1086 |
#endif
|
1087 |
i2c = opaque; |
1088 |
switch (addr - i2c->base) {
|
1089 |
case 0x00: |
1090 |
// i2c_readbyte(&i2c->mdata);
|
1091 |
ret = i2c->mdata; |
1092 |
break;
|
1093 |
case 0x02: |
1094 |
ret = i2c->sdata; |
1095 |
break;
|
1096 |
case 0x04: |
1097 |
ret = i2c->lmadr; |
1098 |
break;
|
1099 |
case 0x05: |
1100 |
ret = i2c->hmadr; |
1101 |
break;
|
1102 |
case 0x06: |
1103 |
ret = i2c->cntl; |
1104 |
break;
|
1105 |
case 0x07: |
1106 |
ret = i2c->mdcntl; |
1107 |
break;
|
1108 |
case 0x08: |
1109 |
ret = i2c->sts; |
1110 |
break;
|
1111 |
case 0x09: |
1112 |
ret = i2c->extsts; |
1113 |
break;
|
1114 |
case 0x0A: |
1115 |
ret = i2c->lsadr; |
1116 |
break;
|
1117 |
case 0x0B: |
1118 |
ret = i2c->hsadr; |
1119 |
break;
|
1120 |
case 0x0C: |
1121 |
ret = i2c->clkdiv; |
1122 |
break;
|
1123 |
case 0x0D: |
1124 |
ret = i2c->intrmsk; |
1125 |
break;
|
1126 |
case 0x0E: |
1127 |
ret = i2c->xfrcnt; |
1128 |
break;
|
1129 |
case 0x0F: |
1130 |
ret = i2c->xtcntlss; |
1131 |
break;
|
1132 |
case 0x10: |
1133 |
ret = i2c->directcntl; |
1134 |
break;
|
1135 |
default:
|
1136 |
ret = 0x00;
|
1137 |
break;
|
1138 |
} |
1139 |
#ifdef DEBUG_I2C
|
1140 |
printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret); |
1141 |
#endif
|
1142 |
|
1143 |
return ret;
|
1144 |
} |
1145 |
|
1146 |
static void ppc4xx_i2c_writeb (void *opaque, |
1147 |
target_phys_addr_t addr, uint32_t value) |
1148 |
{ |
1149 |
ppc4xx_i2c_t *i2c; |
1150 |
|
1151 |
#ifdef DEBUG_I2C
|
1152 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1153 |
#endif
|
1154 |
i2c = opaque; |
1155 |
switch (addr - i2c->base) {
|
1156 |
case 0x00: |
1157 |
i2c->mdata = value; |
1158 |
// i2c_sendbyte(&i2c->mdata);
|
1159 |
break;
|
1160 |
case 0x02: |
1161 |
i2c->sdata = value; |
1162 |
break;
|
1163 |
case 0x04: |
1164 |
i2c->lmadr = value; |
1165 |
break;
|
1166 |
case 0x05: |
1167 |
i2c->hmadr = value; |
1168 |
break;
|
1169 |
case 0x06: |
1170 |
i2c->cntl = value; |
1171 |
break;
|
1172 |
case 0x07: |
1173 |
i2c->mdcntl = value & 0xDF;
|
1174 |
break;
|
1175 |
case 0x08: |
1176 |
i2c->sts &= ~(value & 0x0A);
|
1177 |
break;
|
1178 |
case 0x09: |
1179 |
i2c->extsts &= ~(value & 0x8F);
|
1180 |
break;
|
1181 |
case 0x0A: |
1182 |
i2c->lsadr = value; |
1183 |
break;
|
1184 |
case 0x0B: |
1185 |
i2c->hsadr = value; |
1186 |
break;
|
1187 |
case 0x0C: |
1188 |
i2c->clkdiv = value; |
1189 |
break;
|
1190 |
case 0x0D: |
1191 |
i2c->intrmsk = value; |
1192 |
break;
|
1193 |
case 0x0E: |
1194 |
i2c->xfrcnt = value & 0x77;
|
1195 |
break;
|
1196 |
case 0x0F: |
1197 |
i2c->xtcntlss = value; |
1198 |
break;
|
1199 |
case 0x10: |
1200 |
i2c->directcntl = value & 0x7;
|
1201 |
break;
|
1202 |
} |
1203 |
} |
1204 |
|
1205 |
static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
1206 |
{ |
1207 |
uint32_t ret; |
1208 |
|
1209 |
#ifdef DEBUG_I2C
|
1210 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1211 |
#endif
|
1212 |
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
1213 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
1214 |
|
1215 |
return ret;
|
1216 |
} |
1217 |
|
1218 |
static void ppc4xx_i2c_writew (void *opaque, |
1219 |
target_phys_addr_t addr, uint32_t value) |
1220 |
{ |
1221 |
#ifdef DEBUG_I2C
|
1222 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1223 |
#endif
|
1224 |
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
1225 |
ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
1226 |
} |
1227 |
|
1228 |
static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
1229 |
{ |
1230 |
uint32_t ret; |
1231 |
|
1232 |
#ifdef DEBUG_I2C
|
1233 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1234 |
#endif
|
1235 |
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
1236 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
1237 |
ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
1238 |
ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
1239 |
|
1240 |
return ret;
|
1241 |
} |
1242 |
|
1243 |
static void ppc4xx_i2c_writel (void *opaque, |
1244 |
target_phys_addr_t addr, uint32_t value) |
1245 |
{ |
1246 |
#ifdef DEBUG_I2C
|
1247 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1248 |
#endif
|
1249 |
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
1250 |
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
1251 |
ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
1252 |
ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
1253 |
} |
1254 |
|
1255 |
static CPUReadMemoryFunc *i2c_read[] = {
|
1256 |
&ppc4xx_i2c_readb, |
1257 |
&ppc4xx_i2c_readw, |
1258 |
&ppc4xx_i2c_readl, |
1259 |
}; |
1260 |
|
1261 |
static CPUWriteMemoryFunc *i2c_write[] = {
|
1262 |
&ppc4xx_i2c_writeb, |
1263 |
&ppc4xx_i2c_writew, |
1264 |
&ppc4xx_i2c_writel, |
1265 |
}; |
1266 |
|
1267 |
static void ppc4xx_i2c_reset (void *opaque) |
1268 |
{ |
1269 |
ppc4xx_i2c_t *i2c; |
1270 |
|
1271 |
i2c = opaque; |
1272 |
i2c->mdata = 0x00;
|
1273 |
i2c->sdata = 0x00;
|
1274 |
i2c->cntl = 0x00;
|
1275 |
i2c->mdcntl = 0x00;
|
1276 |
i2c->sts = 0x00;
|
1277 |
i2c->extsts = 0x00;
|
1278 |
i2c->clkdiv = 0x00;
|
1279 |
i2c->xfrcnt = 0x00;
|
1280 |
i2c->directcntl = 0x0F;
|
1281 |
} |
1282 |
|
1283 |
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1284 |
target_phys_addr_t offset, qemu_irq irq) |
1285 |
{ |
1286 |
ppc4xx_i2c_t *i2c; |
1287 |
|
1288 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
1289 |
if (i2c != NULL) { |
1290 |
i2c->base = offset; |
1291 |
i2c->irq = irq; |
1292 |
ppc4xx_i2c_reset(i2c); |
1293 |
#ifdef DEBUG_I2C
|
1294 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
1295 |
#endif
|
1296 |
ppc4xx_mmio_register(env, mmio, offset, 0x011,
|
1297 |
i2c_read, i2c_write, i2c); |
1298 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
1299 |
} |
1300 |
} |
1301 |
|
1302 |
/*****************************************************************************/
|
1303 |
/* General purpose timers */
|
1304 |
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
1305 |
struct ppc4xx_gpt_t {
|
1306 |
target_phys_addr_t base; |
1307 |
int64_t tb_offset; |
1308 |
uint32_t tb_freq; |
1309 |
struct QEMUTimer *timer;
|
1310 |
qemu_irq irqs[5];
|
1311 |
uint32_t oe; |
1312 |
uint32_t ol; |
1313 |
uint32_t im; |
1314 |
uint32_t is; |
1315 |
uint32_t ie; |
1316 |
uint32_t comp[5];
|
1317 |
uint32_t mask[5];
|
1318 |
}; |
1319 |
|
1320 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
1321 |
{ |
1322 |
#ifdef DEBUG_GPT
|
1323 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1324 |
#endif
|
1325 |
/* XXX: generate a bus fault */
|
1326 |
return -1; |
1327 |
} |
1328 |
|
1329 |
static void ppc4xx_gpt_writeb (void *opaque, |
1330 |
target_phys_addr_t addr, uint32_t value) |
1331 |
{ |
1332 |
#ifdef DEBUG_I2C
|
1333 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1334 |
#endif
|
1335 |
/* XXX: generate a bus fault */
|
1336 |
} |
1337 |
|
1338 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
1339 |
{ |
1340 |
#ifdef DEBUG_GPT
|
1341 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1342 |
#endif
|
1343 |
/* XXX: generate a bus fault */
|
1344 |
return -1; |
1345 |
} |
1346 |
|
1347 |
static void ppc4xx_gpt_writew (void *opaque, |
1348 |
target_phys_addr_t addr, uint32_t value) |
1349 |
{ |
1350 |
#ifdef DEBUG_I2C
|
1351 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1352 |
#endif
|
1353 |
/* XXX: generate a bus fault */
|
1354 |
} |
1355 |
|
1356 |
static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
1357 |
{ |
1358 |
/* XXX: TODO */
|
1359 |
return 0; |
1360 |
} |
1361 |
|
1362 |
static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
1363 |
{ |
1364 |
/* XXX: TODO */
|
1365 |
} |
1366 |
|
1367 |
static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
1368 |
{ |
1369 |
uint32_t mask; |
1370 |
int i;
|
1371 |
|
1372 |
mask = 0x80000000;
|
1373 |
for (i = 0; i < 5; i++) { |
1374 |
if (gpt->oe & mask) {
|
1375 |
/* Output is enabled */
|
1376 |
if (ppc4xx_gpt_compare(gpt, i)) {
|
1377 |
/* Comparison is OK */
|
1378 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
1379 |
} else {
|
1380 |
/* Comparison is KO */
|
1381 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
1382 |
} |
1383 |
} |
1384 |
mask = mask >> 1;
|
1385 |
} |
1386 |
} |
1387 |
|
1388 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
1389 |
{ |
1390 |
uint32_t mask; |
1391 |
int i;
|
1392 |
|
1393 |
mask = 0x00008000;
|
1394 |
for (i = 0; i < 5; i++) { |
1395 |
if (gpt->is & gpt->im & mask)
|
1396 |
qemu_irq_raise(gpt->irqs[i]); |
1397 |
else
|
1398 |
qemu_irq_lower(gpt->irqs[i]); |
1399 |
mask = mask >> 1;
|
1400 |
} |
1401 |
} |
1402 |
|
1403 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
1404 |
{ |
1405 |
/* XXX: TODO */
|
1406 |
} |
1407 |
|
1408 |
static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
1409 |
{ |
1410 |
ppc4xx_gpt_t *gpt; |
1411 |
uint32_t ret; |
1412 |
int idx;
|
1413 |
|
1414 |
#ifdef DEBUG_GPT
|
1415 |
printf("%s: addr " PADDRX "\n", __func__, addr); |
1416 |
#endif
|
1417 |
gpt = opaque; |
1418 |
switch (addr - gpt->base) {
|
1419 |
case 0x00: |
1420 |
/* Time base counter */
|
1421 |
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
1422 |
gpt->tb_freq, ticks_per_sec); |
1423 |
break;
|
1424 |
case 0x10: |
1425 |
/* Output enable */
|
1426 |
ret = gpt->oe; |
1427 |
break;
|
1428 |
case 0x14: |
1429 |
/* Output level */
|
1430 |
ret = gpt->ol; |
1431 |
break;
|
1432 |
case 0x18: |
1433 |
/* Interrupt mask */
|
1434 |
ret = gpt->im; |
1435 |
break;
|
1436 |
case 0x1C: |
1437 |
case 0x20: |
1438 |
/* Interrupt status */
|
1439 |
ret = gpt->is; |
1440 |
break;
|
1441 |
case 0x24: |
1442 |
/* Interrupt enable */
|
1443 |
ret = gpt->ie; |
1444 |
break;
|
1445 |
case 0x80 ... 0x90: |
1446 |
/* Compare timer */
|
1447 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
1448 |
ret = gpt->comp[idx]; |
1449 |
break;
|
1450 |
case 0xC0 ... 0xD0: |
1451 |
/* Compare mask */
|
1452 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
1453 |
ret = gpt->mask[idx]; |
1454 |
break;
|
1455 |
default:
|
1456 |
ret = -1;
|
1457 |
break;
|
1458 |
} |
1459 |
|
1460 |
return ret;
|
1461 |
} |
1462 |
|
1463 |
static void ppc4xx_gpt_writel (void *opaque, |
1464 |
target_phys_addr_t addr, uint32_t value) |
1465 |
{ |
1466 |
ppc4xx_gpt_t *gpt; |
1467 |
int idx;
|
1468 |
|
1469 |
#ifdef DEBUG_I2C
|
1470 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
1471 |
#endif
|
1472 |
gpt = opaque; |
1473 |
switch (addr - gpt->base) {
|
1474 |
case 0x00: |
1475 |
/* Time base counter */
|
1476 |
gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
1477 |
- qemu_get_clock(vm_clock); |
1478 |
ppc4xx_gpt_compute_timer(gpt); |
1479 |
break;
|
1480 |
case 0x10: |
1481 |
/* Output enable */
|
1482 |
gpt->oe = value & 0xF8000000;
|
1483 |
ppc4xx_gpt_set_outputs(gpt); |
1484 |
break;
|
1485 |
case 0x14: |
1486 |
/* Output level */
|
1487 |
gpt->ol = value & 0xF8000000;
|
1488 |
ppc4xx_gpt_set_outputs(gpt); |
1489 |
break;
|
1490 |
case 0x18: |
1491 |
/* Interrupt mask */
|
1492 |
gpt->im = value & 0x0000F800;
|
1493 |
break;
|
1494 |
case 0x1C: |
1495 |
/* Interrupt status set */
|
1496 |
gpt->is |= value & 0x0000F800;
|
1497 |
ppc4xx_gpt_set_irqs(gpt); |
1498 |
break;
|
1499 |
case 0x20: |
1500 |
/* Interrupt status clear */
|
1501 |
gpt->is &= ~(value & 0x0000F800);
|
1502 |
ppc4xx_gpt_set_irqs(gpt); |
1503 |
break;
|
1504 |
case 0x24: |
1505 |
/* Interrupt enable */
|
1506 |
gpt->ie = value & 0x0000F800;
|
1507 |
ppc4xx_gpt_set_irqs(gpt); |
1508 |
break;
|
1509 |
case 0x80 ... 0x90: |
1510 |
/* Compare timer */
|
1511 |
idx = ((addr - gpt->base) - 0x80) >> 2; |
1512 |
gpt->comp[idx] = value & 0xF8000000;
|
1513 |
ppc4xx_gpt_compute_timer(gpt); |
1514 |
break;
|
1515 |
case 0xC0 ... 0xD0: |
1516 |
/* Compare mask */
|
1517 |
idx = ((addr - gpt->base) - 0xC0) >> 2; |
1518 |
gpt->mask[idx] = value & 0xF8000000;
|
1519 |
ppc4xx_gpt_compute_timer(gpt); |
1520 |
break;
|
1521 |
} |
1522 |
} |
1523 |
|
1524 |
static CPUReadMemoryFunc *gpt_read[] = {
|
1525 |
&ppc4xx_gpt_readb, |
1526 |
&ppc4xx_gpt_readw, |
1527 |
&ppc4xx_gpt_readl, |
1528 |
}; |
1529 |
|
1530 |
static CPUWriteMemoryFunc *gpt_write[] = {
|
1531 |
&ppc4xx_gpt_writeb, |
1532 |
&ppc4xx_gpt_writew, |
1533 |
&ppc4xx_gpt_writel, |
1534 |
}; |
1535 |
|
1536 |
static void ppc4xx_gpt_cb (void *opaque) |
1537 |
{ |
1538 |
ppc4xx_gpt_t *gpt; |
1539 |
|
1540 |
gpt = opaque; |
1541 |
ppc4xx_gpt_set_irqs(gpt); |
1542 |
ppc4xx_gpt_set_outputs(gpt); |
1543 |
ppc4xx_gpt_compute_timer(gpt); |
1544 |
} |
1545 |
|
1546 |
static void ppc4xx_gpt_reset (void *opaque) |
1547 |
{ |
1548 |
ppc4xx_gpt_t *gpt; |
1549 |
int i;
|
1550 |
|
1551 |
gpt = opaque; |
1552 |
qemu_del_timer(gpt->timer); |
1553 |
gpt->oe = 0x00000000;
|
1554 |
gpt->ol = 0x00000000;
|
1555 |
gpt->im = 0x00000000;
|
1556 |
gpt->is = 0x00000000;
|
1557 |
gpt->ie = 0x00000000;
|
1558 |
for (i = 0; i < 5; i++) { |
1559 |
gpt->comp[i] = 0x00000000;
|
1560 |
gpt->mask[i] = 0x00000000;
|
1561 |
} |
1562 |
} |
1563 |
|
1564 |
void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1565 |
target_phys_addr_t offset, qemu_irq irqs[5])
|
1566 |
{ |
1567 |
ppc4xx_gpt_t *gpt; |
1568 |
int i;
|
1569 |
|
1570 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
1571 |
if (gpt != NULL) { |
1572 |
gpt->base = offset; |
1573 |
for (i = 0; i < 5; i++) |
1574 |
gpt->irqs[i] = irqs[i]; |
1575 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
1576 |
ppc4xx_gpt_reset(gpt); |
1577 |
#ifdef DEBUG_GPT
|
1578 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
1579 |
#endif
|
1580 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
|
1581 |
gpt_read, gpt_write, gpt); |
1582 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
1583 |
} |
1584 |
} |
1585 |
|
1586 |
/*****************************************************************************/
|
1587 |
/* MAL */
|
1588 |
enum {
|
1589 |
MAL0_CFG = 0x180,
|
1590 |
MAL0_ESR = 0x181,
|
1591 |
MAL0_IER = 0x182,
|
1592 |
MAL0_TXCASR = 0x184,
|
1593 |
MAL0_TXCARR = 0x185,
|
1594 |
MAL0_TXEOBISR = 0x186,
|
1595 |
MAL0_TXDEIR = 0x187,
|
1596 |
MAL0_RXCASR = 0x190,
|
1597 |
MAL0_RXCARR = 0x191,
|
1598 |
MAL0_RXEOBISR = 0x192,
|
1599 |
MAL0_RXDEIR = 0x193,
|
1600 |
MAL0_TXCTP0R = 0x1A0,
|
1601 |
MAL0_TXCTP1R = 0x1A1,
|
1602 |
MAL0_TXCTP2R = 0x1A2,
|
1603 |
MAL0_TXCTP3R = 0x1A3,
|
1604 |
MAL0_RXCTP0R = 0x1C0,
|
1605 |
MAL0_RXCTP1R = 0x1C1,
|
1606 |
MAL0_RCBS0 = 0x1E0,
|
1607 |
MAL0_RCBS1 = 0x1E1,
|
1608 |
}; |
1609 |
|
1610 |
typedef struct ppc40x_mal_t ppc40x_mal_t; |
1611 |
struct ppc40x_mal_t {
|
1612 |
qemu_irq irqs[4];
|
1613 |
uint32_t cfg; |
1614 |
uint32_t esr; |
1615 |
uint32_t ier; |
1616 |
uint32_t txcasr; |
1617 |
uint32_t txcarr; |
1618 |
uint32_t txeobisr; |
1619 |
uint32_t txdeir; |
1620 |
uint32_t rxcasr; |
1621 |
uint32_t rxcarr; |
1622 |
uint32_t rxeobisr; |
1623 |
uint32_t rxdeir; |
1624 |
uint32_t txctpr[4];
|
1625 |
uint32_t rxctpr[2];
|
1626 |
uint32_t rcbs[2];
|
1627 |
}; |
1628 |
|
1629 |
static void ppc40x_mal_reset (void *opaque); |
1630 |
|
1631 |
static target_ulong dcr_read_mal (void *opaque, int dcrn) |
1632 |
{ |
1633 |
ppc40x_mal_t *mal; |
1634 |
target_ulong ret; |
1635 |
|
1636 |
mal = opaque; |
1637 |
switch (dcrn) {
|
1638 |
case MAL0_CFG:
|
1639 |
ret = mal->cfg; |
1640 |
break;
|
1641 |
case MAL0_ESR:
|
1642 |
ret = mal->esr; |
1643 |
break;
|
1644 |
case MAL0_IER:
|
1645 |
ret = mal->ier; |
1646 |
break;
|
1647 |
case MAL0_TXCASR:
|
1648 |
ret = mal->txcasr; |
1649 |
break;
|
1650 |
case MAL0_TXCARR:
|
1651 |
ret = mal->txcarr; |
1652 |
break;
|
1653 |
case MAL0_TXEOBISR:
|
1654 |
ret = mal->txeobisr; |
1655 |
break;
|
1656 |
case MAL0_TXDEIR:
|
1657 |
ret = mal->txdeir; |
1658 |
break;
|
1659 |
case MAL0_RXCASR:
|
1660 |
ret = mal->rxcasr; |
1661 |
break;
|
1662 |
case MAL0_RXCARR:
|
1663 |
ret = mal->rxcarr; |
1664 |
break;
|
1665 |
case MAL0_RXEOBISR:
|
1666 |
ret = mal->rxeobisr; |
1667 |
break;
|
1668 |
case MAL0_RXDEIR:
|
1669 |
ret = mal->rxdeir; |
1670 |
break;
|
1671 |
case MAL0_TXCTP0R:
|
1672 |
ret = mal->txctpr[0];
|
1673 |
break;
|
1674 |
case MAL0_TXCTP1R:
|
1675 |
ret = mal->txctpr[1];
|
1676 |
break;
|
1677 |
case MAL0_TXCTP2R:
|
1678 |
ret = mal->txctpr[2];
|
1679 |
break;
|
1680 |
case MAL0_TXCTP3R:
|
1681 |
ret = mal->txctpr[3];
|
1682 |
break;
|
1683 |
case MAL0_RXCTP0R:
|
1684 |
ret = mal->rxctpr[0];
|
1685 |
break;
|
1686 |
case MAL0_RXCTP1R:
|
1687 |
ret = mal->rxctpr[1];
|
1688 |
break;
|
1689 |
case MAL0_RCBS0:
|
1690 |
ret = mal->rcbs[0];
|
1691 |
break;
|
1692 |
case MAL0_RCBS1:
|
1693 |
ret = mal->rcbs[1];
|
1694 |
break;
|
1695 |
default:
|
1696 |
ret = 0;
|
1697 |
break;
|
1698 |
} |
1699 |
|
1700 |
return ret;
|
1701 |
} |
1702 |
|
1703 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
1704 |
{ |
1705 |
ppc40x_mal_t *mal; |
1706 |
int idx;
|
1707 |
|
1708 |
mal = opaque; |
1709 |
switch (dcrn) {
|
1710 |
case MAL0_CFG:
|
1711 |
if (val & 0x80000000) |
1712 |
ppc40x_mal_reset(mal); |
1713 |
mal->cfg = val & 0x00FFC087;
|
1714 |
break;
|
1715 |
case MAL0_ESR:
|
1716 |
/* Read/clear */
|
1717 |
mal->esr &= ~val; |
1718 |
break;
|
1719 |
case MAL0_IER:
|
1720 |
mal->ier = val & 0x0000001F;
|
1721 |
break;
|
1722 |
case MAL0_TXCASR:
|
1723 |
mal->txcasr = val & 0xF0000000;
|
1724 |
break;
|
1725 |
case MAL0_TXCARR:
|
1726 |
mal->txcarr = val & 0xF0000000;
|
1727 |
break;
|
1728 |
case MAL0_TXEOBISR:
|
1729 |
/* Read/clear */
|
1730 |
mal->txeobisr &= ~val; |
1731 |
break;
|
1732 |
case MAL0_TXDEIR:
|
1733 |
/* Read/clear */
|
1734 |
mal->txdeir &= ~val; |
1735 |
break;
|
1736 |
case MAL0_RXCASR:
|
1737 |
mal->rxcasr = val & 0xC0000000;
|
1738 |
break;
|
1739 |
case MAL0_RXCARR:
|
1740 |
mal->rxcarr = val & 0xC0000000;
|
1741 |
break;
|
1742 |
case MAL0_RXEOBISR:
|
1743 |
/* Read/clear */
|
1744 |
mal->rxeobisr &= ~val; |
1745 |
break;
|
1746 |
case MAL0_RXDEIR:
|
1747 |
/* Read/clear */
|
1748 |
mal->rxdeir &= ~val; |
1749 |
break;
|
1750 |
case MAL0_TXCTP0R:
|
1751 |
idx = 0;
|
1752 |
goto update_tx_ptr;
|
1753 |
case MAL0_TXCTP1R:
|
1754 |
idx = 1;
|
1755 |
goto update_tx_ptr;
|
1756 |
case MAL0_TXCTP2R:
|
1757 |
idx = 2;
|
1758 |
goto update_tx_ptr;
|
1759 |
case MAL0_TXCTP3R:
|
1760 |
idx = 3;
|
1761 |
update_tx_ptr:
|
1762 |
mal->txctpr[idx] = val; |
1763 |
break;
|
1764 |
case MAL0_RXCTP0R:
|
1765 |
idx = 0;
|
1766 |
goto update_rx_ptr;
|
1767 |
case MAL0_RXCTP1R:
|
1768 |
idx = 1;
|
1769 |
update_rx_ptr:
|
1770 |
mal->rxctpr[idx] = val; |
1771 |
break;
|
1772 |
case MAL0_RCBS0:
|
1773 |
idx = 0;
|
1774 |
goto update_rx_size;
|
1775 |
case MAL0_RCBS1:
|
1776 |
idx = 1;
|
1777 |
update_rx_size:
|
1778 |
mal->rcbs[idx] = val & 0x000000FF;
|
1779 |
break;
|
1780 |
} |
1781 |
} |
1782 |
|
1783 |
static void ppc40x_mal_reset (void *opaque) |
1784 |
{ |
1785 |
ppc40x_mal_t *mal; |
1786 |
|
1787 |
mal = opaque; |
1788 |
mal->cfg = 0x0007C000;
|
1789 |
mal->esr = 0x00000000;
|
1790 |
mal->ier = 0x00000000;
|
1791 |
mal->rxcasr = 0x00000000;
|
1792 |
mal->rxdeir = 0x00000000;
|
1793 |
mal->rxeobisr = 0x00000000;
|
1794 |
mal->txcasr = 0x00000000;
|
1795 |
mal->txdeir = 0x00000000;
|
1796 |
mal->txeobisr = 0x00000000;
|
1797 |
} |
1798 |
|
1799 |
void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) |
1800 |
{ |
1801 |
ppc40x_mal_t *mal; |
1802 |
int i;
|
1803 |
|
1804 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
1805 |
if (mal != NULL) { |
1806 |
for (i = 0; i < 4; i++) |
1807 |
mal->irqs[i] = irqs[i]; |
1808 |
ppc40x_mal_reset(mal); |
1809 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
1810 |
ppc_dcr_register(env, MAL0_CFG, |
1811 |
mal, &dcr_read_mal, &dcr_write_mal); |
1812 |
ppc_dcr_register(env, MAL0_ESR, |
1813 |
mal, &dcr_read_mal, &dcr_write_mal); |
1814 |
ppc_dcr_register(env, MAL0_IER, |
1815 |
mal, &dcr_read_mal, &dcr_write_mal); |
1816 |
ppc_dcr_register(env, MAL0_TXCASR, |
1817 |
mal, &dcr_read_mal, &dcr_write_mal); |
1818 |
ppc_dcr_register(env, MAL0_TXCARR, |
1819 |
mal, &dcr_read_mal, &dcr_write_mal); |
1820 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
1821 |
mal, &dcr_read_mal, &dcr_write_mal); |
1822 |
ppc_dcr_register(env, MAL0_TXDEIR, |
1823 |
mal, &dcr_read_mal, &dcr_write_mal); |
1824 |
ppc_dcr_register(env, MAL0_RXCASR, |
1825 |
mal, &dcr_read_mal, &dcr_write_mal); |
1826 |
ppc_dcr_register(env, MAL0_RXCARR, |
1827 |
mal, &dcr_read_mal, &dcr_write_mal); |
1828 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
1829 |
mal, &dcr_read_mal, &dcr_write_mal); |
1830 |
ppc_dcr_register(env, MAL0_RXDEIR, |
1831 |
mal, &dcr_read_mal, &dcr_write_mal); |
1832 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
1833 |
mal, &dcr_read_mal, &dcr_write_mal); |
1834 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
1835 |
mal, &dcr_read_mal, &dcr_write_mal); |
1836 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
1837 |
mal, &dcr_read_mal, &dcr_write_mal); |
1838 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
1839 |
mal, &dcr_read_mal, &dcr_write_mal); |
1840 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
1841 |
mal, &dcr_read_mal, &dcr_write_mal); |
1842 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
1843 |
mal, &dcr_read_mal, &dcr_write_mal); |
1844 |
ppc_dcr_register(env, MAL0_RCBS0, |
1845 |
mal, &dcr_read_mal, &dcr_write_mal); |
1846 |
ppc_dcr_register(env, MAL0_RCBS1, |
1847 |
mal, &dcr_read_mal, &dcr_write_mal); |
1848 |
} |
1849 |
} |
1850 |
|
1851 |
/*****************************************************************************/
|
1852 |
/* SPR */
|
1853 |
void ppc40x_core_reset (CPUState *env)
|
1854 |
{ |
1855 |
target_ulong dbsr; |
1856 |
|
1857 |
printf("Reset PowerPC core\n");
|
1858 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1859 |
/* XXX: TOFIX */
|
1860 |
#if 0
|
1861 |
cpu_ppc_reset(env);
|
1862 |
#else
|
1863 |
qemu_system_reset_request(); |
1864 |
#endif
|
1865 |
dbsr = env->spr[SPR_40x_DBSR]; |
1866 |
dbsr &= ~0x00000300;
|
1867 |
dbsr |= 0x00000100;
|
1868 |
env->spr[SPR_40x_DBSR] = dbsr; |
1869 |
} |
1870 |
|
1871 |
void ppc40x_chip_reset (CPUState *env)
|
1872 |
{ |
1873 |
target_ulong dbsr; |
1874 |
|
1875 |
printf("Reset PowerPC chip\n");
|
1876 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1877 |
/* XXX: TOFIX */
|
1878 |
#if 0
|
1879 |
cpu_ppc_reset(env);
|
1880 |
#else
|
1881 |
qemu_system_reset_request(); |
1882 |
#endif
|
1883 |
/* XXX: TODO reset all internal peripherals */
|
1884 |
dbsr = env->spr[SPR_40x_DBSR]; |
1885 |
dbsr &= ~0x00000300;
|
1886 |
dbsr |= 0x00000200;
|
1887 |
env->spr[SPR_40x_DBSR] = dbsr; |
1888 |
} |
1889 |
|
1890 |
void ppc40x_system_reset (CPUState *env)
|
1891 |
{ |
1892 |
printf("Reset PowerPC system\n");
|
1893 |
qemu_system_reset_request(); |
1894 |
} |
1895 |
|
1896 |
void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
1897 |
{ |
1898 |
switch ((val >> 28) & 0x3) { |
1899 |
case 0x0: |
1900 |
/* No action */
|
1901 |
break;
|
1902 |
case 0x1: |
1903 |
/* Core reset */
|
1904 |
ppc40x_core_reset(env); |
1905 |
break;
|
1906 |
case 0x2: |
1907 |
/* Chip reset */
|
1908 |
ppc40x_chip_reset(env); |
1909 |
break;
|
1910 |
case 0x3: |
1911 |
/* System reset */
|
1912 |
ppc40x_system_reset(env); |
1913 |
break;
|
1914 |
} |
1915 |
} |
1916 |
|
1917 |
/*****************************************************************************/
|
1918 |
/* PowerPC 405CR */
|
1919 |
enum {
|
1920 |
PPC405CR_CPC0_PLLMR = 0x0B0,
|
1921 |
PPC405CR_CPC0_CR0 = 0x0B1,
|
1922 |
PPC405CR_CPC0_CR1 = 0x0B2,
|
1923 |
PPC405CR_CPC0_PSR = 0x0B4,
|
1924 |
PPC405CR_CPC0_JTAGID = 0x0B5,
|
1925 |
PPC405CR_CPC0_ER = 0x0B9,
|
1926 |
PPC405CR_CPC0_FR = 0x0BA,
|
1927 |
PPC405CR_CPC0_SR = 0x0BB,
|
1928 |
}; |
1929 |
|
1930 |
enum {
|
1931 |
PPC405CR_CPU_CLK = 0,
|
1932 |
PPC405CR_TMR_CLK = 1,
|
1933 |
PPC405CR_PLB_CLK = 2,
|
1934 |
PPC405CR_SDRAM_CLK = 3,
|
1935 |
PPC405CR_OPB_CLK = 4,
|
1936 |
PPC405CR_EXT_CLK = 5,
|
1937 |
PPC405CR_UART_CLK = 6,
|
1938 |
PPC405CR_CLK_NB = 7,
|
1939 |
}; |
1940 |
|
1941 |
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
1942 |
struct ppc405cr_cpc_t {
|
1943 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
1944 |
uint32_t sysclk; |
1945 |
uint32_t psr; |
1946 |
uint32_t cr0; |
1947 |
uint32_t cr1; |
1948 |
uint32_t jtagid; |
1949 |
uint32_t pllmr; |
1950 |
uint32_t er; |
1951 |
uint32_t fr; |
1952 |
}; |
1953 |
|
1954 |
static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
1955 |
{ |
1956 |
uint64_t VCO_out, PLL_out; |
1957 |
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
1958 |
int M, D0, D1, D2;
|
1959 |
|
1960 |
D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
1961 |
if (cpc->pllmr & 0x80000000) { |
1962 |
D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
1963 |
D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
1964 |
M = D0 * D1 * D2; |
1965 |
VCO_out = cpc->sysclk * M; |
1966 |
if (VCO_out < 400000000 || VCO_out > 800000000) { |
1967 |
/* PLL cannot lock */
|
1968 |
cpc->pllmr &= ~0x80000000;
|
1969 |
goto bypass_pll;
|
1970 |
} |
1971 |
PLL_out = VCO_out / D2; |
1972 |
} else {
|
1973 |
/* Bypass PLL */
|
1974 |
bypass_pll:
|
1975 |
M = D0; |
1976 |
PLL_out = cpc->sysclk * M; |
1977 |
} |
1978 |
CPU_clk = PLL_out; |
1979 |
if (cpc->cr1 & 0x00800000) |
1980 |
TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
1981 |
else
|
1982 |
TMR_clk = CPU_clk; |
1983 |
PLB_clk = CPU_clk / D0; |
1984 |
SDRAM_clk = PLB_clk; |
1985 |
D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
1986 |
OPB_clk = PLB_clk / D0; |
1987 |
D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
1988 |
EXT_clk = PLB_clk / D0; |
1989 |
D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
1990 |
UART_clk = CPU_clk / D0; |
1991 |
/* Setup CPU clocks */
|
1992 |
clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
1993 |
/* Setup time-base clock */
|
1994 |
clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
1995 |
/* Setup PLB clock */
|
1996 |
clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
1997 |
/* Setup SDRAM clock */
|
1998 |
clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
1999 |
/* Setup OPB clock */
|
2000 |
clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
2001 |
/* Setup external clock */
|
2002 |
clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
2003 |
/* Setup UART clock */
|
2004 |
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
2005 |
} |
2006 |
|
2007 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
2008 |
{ |
2009 |
ppc405cr_cpc_t *cpc; |
2010 |
target_ulong ret; |
2011 |
|
2012 |
cpc = opaque; |
2013 |
switch (dcrn) {
|
2014 |
case PPC405CR_CPC0_PLLMR:
|
2015 |
ret = cpc->pllmr; |
2016 |
break;
|
2017 |
case PPC405CR_CPC0_CR0:
|
2018 |
ret = cpc->cr0; |
2019 |
break;
|
2020 |
case PPC405CR_CPC0_CR1:
|
2021 |
ret = cpc->cr1; |
2022 |
break;
|
2023 |
case PPC405CR_CPC0_PSR:
|
2024 |
ret = cpc->psr; |
2025 |
break;
|
2026 |
case PPC405CR_CPC0_JTAGID:
|
2027 |
ret = cpc->jtagid; |
2028 |
break;
|
2029 |
case PPC405CR_CPC0_ER:
|
2030 |
ret = cpc->er; |
2031 |
break;
|
2032 |
case PPC405CR_CPC0_FR:
|
2033 |
ret = cpc->fr; |
2034 |
break;
|
2035 |
case PPC405CR_CPC0_SR:
|
2036 |
ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
2037 |
break;
|
2038 |
default:
|
2039 |
/* Avoid gcc warning */
|
2040 |
ret = 0;
|
2041 |
break;
|
2042 |
} |
2043 |
|
2044 |
return ret;
|
2045 |
} |
2046 |
|
2047 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2048 |
{ |
2049 |
ppc405cr_cpc_t *cpc; |
2050 |
|
2051 |
cpc = opaque; |
2052 |
switch (dcrn) {
|
2053 |
case PPC405CR_CPC0_PLLMR:
|
2054 |
cpc->pllmr = val & 0xFFF77C3F;
|
2055 |
break;
|
2056 |
case PPC405CR_CPC0_CR0:
|
2057 |
cpc->cr0 = val & 0x0FFFFFFE;
|
2058 |
break;
|
2059 |
case PPC405CR_CPC0_CR1:
|
2060 |
cpc->cr1 = val & 0x00800000;
|
2061 |
break;
|
2062 |
case PPC405CR_CPC0_PSR:
|
2063 |
/* Read-only */
|
2064 |
break;
|
2065 |
case PPC405CR_CPC0_JTAGID:
|
2066 |
/* Read-only */
|
2067 |
break;
|
2068 |
case PPC405CR_CPC0_ER:
|
2069 |
cpc->er = val & 0xBFFC0000;
|
2070 |
break;
|
2071 |
case PPC405CR_CPC0_FR:
|
2072 |
cpc->fr = val & 0xBFFC0000;
|
2073 |
break;
|
2074 |
case PPC405CR_CPC0_SR:
|
2075 |
/* Read-only */
|
2076 |
break;
|
2077 |
} |
2078 |
} |
2079 |
|
2080 |
static void ppc405cr_cpc_reset (void *opaque) |
2081 |
{ |
2082 |
ppc405cr_cpc_t *cpc; |
2083 |
int D;
|
2084 |
|
2085 |
cpc = opaque; |
2086 |
/* Compute PLLMR value from PSR settings */
|
2087 |
cpc->pllmr = 0x80000000;
|
2088 |
/* PFWD */
|
2089 |
switch ((cpc->psr >> 30) & 3) { |
2090 |
case 0: |
2091 |
/* Bypass */
|
2092 |
cpc->pllmr &= ~0x80000000;
|
2093 |
break;
|
2094 |
case 1: |
2095 |
/* Divide by 3 */
|
2096 |
cpc->pllmr |= 5 << 16; |
2097 |
break;
|
2098 |
case 2: |
2099 |
/* Divide by 4 */
|
2100 |
cpc->pllmr |= 4 << 16; |
2101 |
break;
|
2102 |
case 3: |
2103 |
/* Divide by 6 */
|
2104 |
cpc->pllmr |= 2 << 16; |
2105 |
break;
|
2106 |
} |
2107 |
/* PFBD */
|
2108 |
D = (cpc->psr >> 28) & 3; |
2109 |
cpc->pllmr |= (D + 1) << 20; |
2110 |
/* PT */
|
2111 |
D = (cpc->psr >> 25) & 7; |
2112 |
switch (D) {
|
2113 |
case 0x2: |
2114 |
cpc->pllmr |= 0x13;
|
2115 |
break;
|
2116 |
case 0x4: |
2117 |
cpc->pllmr |= 0x15;
|
2118 |
break;
|
2119 |
case 0x5: |
2120 |
cpc->pllmr |= 0x16;
|
2121 |
break;
|
2122 |
default:
|
2123 |
break;
|
2124 |
} |
2125 |
/* PDC */
|
2126 |
D = (cpc->psr >> 23) & 3; |
2127 |
cpc->pllmr |= D << 26;
|
2128 |
/* ODP */
|
2129 |
D = (cpc->psr >> 21) & 3; |
2130 |
cpc->pllmr |= D << 10;
|
2131 |
/* EBPD */
|
2132 |
D = (cpc->psr >> 17) & 3; |
2133 |
cpc->pllmr |= D << 24;
|
2134 |
cpc->cr0 = 0x0000003C;
|
2135 |
cpc->cr1 = 0x2B0D8800;
|
2136 |
cpc->er = 0x00000000;
|
2137 |
cpc->fr = 0x00000000;
|
2138 |
ppc405cr_clk_setup(cpc); |
2139 |
} |
2140 |
|
2141 |
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
2142 |
{ |
2143 |
int D;
|
2144 |
|
2145 |
/* XXX: this should be read from IO pins */
|
2146 |
cpc->psr = 0x00000000; /* 8 bits ROM */ |
2147 |
/* PFWD */
|
2148 |
D = 0x2; /* Divide by 4 */ |
2149 |
cpc->psr |= D << 30;
|
2150 |
/* PFBD */
|
2151 |
D = 0x1; /* Divide by 2 */ |
2152 |
cpc->psr |= D << 28;
|
2153 |
/* PDC */
|
2154 |
D = 0x1; /* Divide by 2 */ |
2155 |
cpc->psr |= D << 23;
|
2156 |
/* PT */
|
2157 |
D = 0x5; /* M = 16 */ |
2158 |
cpc->psr |= D << 25;
|
2159 |
/* ODP */
|
2160 |
D = 0x1; /* Divide by 2 */ |
2161 |
cpc->psr |= D << 21;
|
2162 |
/* EBDP */
|
2163 |
D = 0x2; /* Divide by 4 */ |
2164 |
cpc->psr |= D << 17;
|
2165 |
} |
2166 |
|
2167 |
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2168 |
uint32_t sysclk) |
2169 |
{ |
2170 |
ppc405cr_cpc_t *cpc; |
2171 |
|
2172 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
2173 |
if (cpc != NULL) { |
2174 |
memcpy(cpc->clk_setup, clk_setup, |
2175 |
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
2176 |
cpc->sysclk = sysclk; |
2177 |
cpc->jtagid = 0x42051049;
|
2178 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
2179 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2180 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
2181 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2182 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
2183 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2184 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
2185 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2186 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
2187 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2188 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
2189 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2190 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
2191 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2192 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
2193 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2194 |
ppc405cr_clk_init(cpc); |
2195 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
2196 |
ppc405cr_cpc_reset(cpc); |
2197 |
} |
2198 |
} |
2199 |
|
2200 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
2201 |
target_phys_addr_t ram_sizes[4],
|
2202 |
uint32_t sysclk, qemu_irq **picp, |
2203 |
ram_addr_t *offsetp, int do_init)
|
2204 |
{ |
2205 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2206 |
qemu_irq dma_irqs[4];
|
2207 |
CPUState *env; |
2208 |
ppc4xx_mmio_t *mmio; |
2209 |
qemu_irq *pic, *irqs; |
2210 |
ram_addr_t offset; |
2211 |
int i;
|
2212 |
|
2213 |
memset(clk_setup, 0, sizeof(clk_setup)); |
2214 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
2215 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
2216 |
/* Memory mapped devices registers */
|
2217 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
2218 |
/* PLB arbitrer */
|
2219 |
ppc4xx_plb_init(env); |
2220 |
/* PLB to OPB bridge */
|
2221 |
ppc4xx_pob_init(env); |
2222 |
/* OBP arbitrer */
|
2223 |
ppc4xx_opba_init(env, mmio, 0x600);
|
2224 |
/* Universal interrupt controller */
|
2225 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2226 |
irqs[PPCUIC_OUTPUT_INT] = |
2227 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2228 |
irqs[PPCUIC_OUTPUT_CINT] = |
2229 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2230 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2231 |
*picp = pic; |
2232 |
/* SDRAM controller */
|
2233 |
ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
2234 |
offset = 0;
|
2235 |
for (i = 0; i < 4; i++) |
2236 |
offset += ram_sizes[i]; |
2237 |
/* External bus controller */
|
2238 |
ppc405_ebc_init(env); |
2239 |
/* DMA controller */
|
2240 |
dma_irqs[0] = pic[26]; |
2241 |
dma_irqs[1] = pic[25]; |
2242 |
dma_irqs[2] = pic[24]; |
2243 |
dma_irqs[3] = pic[23]; |
2244 |
ppc405_dma_init(env, dma_irqs); |
2245 |
/* Serial ports */
|
2246 |
if (serial_hds[0] != NULL) { |
2247 |
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
2248 |
} |
2249 |
if (serial_hds[1] != NULL) { |
2250 |
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
2251 |
} |
2252 |
/* IIC controller */
|
2253 |
ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
2254 |
/* GPIO */
|
2255 |
ppc405_gpio_init(env, mmio, 0x700);
|
2256 |
/* CPU control */
|
2257 |
ppc405cr_cpc_init(env, clk_setup, sysclk); |
2258 |
*offsetp = offset; |
2259 |
|
2260 |
return env;
|
2261 |
} |
2262 |
|
2263 |
/*****************************************************************************/
|
2264 |
/* PowerPC 405EP */
|
2265 |
/* CPU control */
|
2266 |
enum {
|
2267 |
PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
2268 |
PPC405EP_CPC0_BOOT = 0x0F1,
|
2269 |
PPC405EP_CPC0_EPCTL = 0x0F3,
|
2270 |
PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
2271 |
PPC405EP_CPC0_UCR = 0x0F5,
|
2272 |
PPC405EP_CPC0_SRR = 0x0F6,
|
2273 |
PPC405EP_CPC0_JTAGID = 0x0F7,
|
2274 |
PPC405EP_CPC0_PCI = 0x0F9,
|
2275 |
#if 0
|
2276 |
PPC405EP_CPC0_ER = xxx,
|
2277 |
PPC405EP_CPC0_FR = xxx,
|
2278 |
PPC405EP_CPC0_SR = xxx,
|
2279 |
#endif
|
2280 |
}; |
2281 |
|
2282 |
enum {
|
2283 |
PPC405EP_CPU_CLK = 0,
|
2284 |
PPC405EP_PLB_CLK = 1,
|
2285 |
PPC405EP_OPB_CLK = 2,
|
2286 |
PPC405EP_EBC_CLK = 3,
|
2287 |
PPC405EP_MAL_CLK = 4,
|
2288 |
PPC405EP_PCI_CLK = 5,
|
2289 |
PPC405EP_UART0_CLK = 6,
|
2290 |
PPC405EP_UART1_CLK = 7,
|
2291 |
PPC405EP_CLK_NB = 8,
|
2292 |
}; |
2293 |
|
2294 |
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
2295 |
struct ppc405ep_cpc_t {
|
2296 |
uint32_t sysclk; |
2297 |
clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
2298 |
uint32_t boot; |
2299 |
uint32_t epctl; |
2300 |
uint32_t pllmr[2];
|
2301 |
uint32_t ucr; |
2302 |
uint32_t srr; |
2303 |
uint32_t jtagid; |
2304 |
uint32_t pci; |
2305 |
/* Clock and power management */
|
2306 |
uint32_t er; |
2307 |
uint32_t fr; |
2308 |
uint32_t sr; |
2309 |
}; |
2310 |
|
2311 |
static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
2312 |
{ |
2313 |
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
2314 |
uint32_t UART0_clk, UART1_clk; |
2315 |
uint64_t VCO_out, PLL_out; |
2316 |
int M, D;
|
2317 |
|
2318 |
VCO_out = 0;
|
2319 |
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
2320 |
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
2321 |
#ifdef DEBUG_CLOCKS_LL
|
2322 |
printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); |
2323 |
#endif
|
2324 |
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
2325 |
#ifdef DEBUG_CLOCKS_LL
|
2326 |
printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); |
2327 |
#endif
|
2328 |
VCO_out = cpc->sysclk * M * D; |
2329 |
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
2330 |
/* Error - unlock the PLL */
|
2331 |
printf("VCO out of range %" PRIu64 "\n", VCO_out); |
2332 |
#if 0
|
2333 |
cpc->pllmr[1] &= ~0x80000000;
|
2334 |
goto pll_bypass;
|
2335 |
#endif
|
2336 |
} |
2337 |
PLL_out = VCO_out / D; |
2338 |
/* Pretend the PLL is locked */
|
2339 |
cpc->boot |= 0x00000001;
|
2340 |
} else {
|
2341 |
#if 0
|
2342 |
pll_bypass:
|
2343 |
#endif
|
2344 |
PLL_out = cpc->sysclk; |
2345 |
if (cpc->pllmr[1] & 0x40000000) { |
2346 |
/* Pretend the PLL is not locked */
|
2347 |
cpc->boot &= ~0x00000001;
|
2348 |
} |
2349 |
} |
2350 |
/* Now, compute all other clocks */
|
2351 |
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
2352 |
#ifdef DEBUG_CLOCKS_LL
|
2353 |
printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); |
2354 |
#endif
|
2355 |
CPU_clk = PLL_out / D; |
2356 |
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
2357 |
#ifdef DEBUG_CLOCKS_LL
|
2358 |
printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); |
2359 |
#endif
|
2360 |
PLB_clk = CPU_clk / D; |
2361 |
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
2362 |
#ifdef DEBUG_CLOCKS_LL
|
2363 |
printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); |
2364 |
#endif
|
2365 |
OPB_clk = PLB_clk / D; |
2366 |
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
2367 |
#ifdef DEBUG_CLOCKS_LL
|
2368 |
printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); |
2369 |
#endif
|
2370 |
EBC_clk = PLB_clk / D; |
2371 |
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
2372 |
#ifdef DEBUG_CLOCKS_LL
|
2373 |
printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); |
2374 |
#endif
|
2375 |
MAL_clk = PLB_clk / D; |
2376 |
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
2377 |
#ifdef DEBUG_CLOCKS_LL
|
2378 |
printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); |
2379 |
#endif
|
2380 |
PCI_clk = PLB_clk / D; |
2381 |
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
2382 |
#ifdef DEBUG_CLOCKS_LL
|
2383 |
printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); |
2384 |
#endif
|
2385 |
UART0_clk = PLL_out / D; |
2386 |
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
2387 |
#ifdef DEBUG_CLOCKS_LL
|
2388 |
printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); |
2389 |
#endif
|
2390 |
UART1_clk = PLL_out / D; |
2391 |
#ifdef DEBUG_CLOCKS
|
2392 |
printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
2393 |
" PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
2394 |
printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
2395 |
" MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 |
2396 |
" UART1 %" PRIu32 "\n", |
2397 |
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
2398 |
UART0_clk, UART1_clk); |
2399 |
#endif
|
2400 |
/* Setup CPU clocks */
|
2401 |
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
2402 |
/* Setup PLB clock */
|
2403 |
clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
2404 |
/* Setup OPB clock */
|
2405 |
clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
2406 |
/* Setup external clock */
|
2407 |
clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
2408 |
/* Setup MAL clock */
|
2409 |
clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
2410 |
/* Setup PCI clock */
|
2411 |
clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
2412 |
/* Setup UART0 clock */
|
2413 |
clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
2414 |
/* Setup UART1 clock */
|
2415 |
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
2416 |
} |
2417 |
|
2418 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
2419 |
{ |
2420 |
ppc405ep_cpc_t *cpc; |
2421 |
target_ulong ret; |
2422 |
|
2423 |
cpc = opaque; |
2424 |
switch (dcrn) {
|
2425 |
case PPC405EP_CPC0_BOOT:
|
2426 |
ret = cpc->boot; |
2427 |
break;
|
2428 |
case PPC405EP_CPC0_EPCTL:
|
2429 |
ret = cpc->epctl; |
2430 |
break;
|
2431 |
case PPC405EP_CPC0_PLLMR0:
|
2432 |
ret = cpc->pllmr[0];
|
2433 |
break;
|
2434 |
case PPC405EP_CPC0_PLLMR1:
|
2435 |
ret = cpc->pllmr[1];
|
2436 |
break;
|
2437 |
case PPC405EP_CPC0_UCR:
|
2438 |
ret = cpc->ucr; |
2439 |
break;
|
2440 |
case PPC405EP_CPC0_SRR:
|
2441 |
ret = cpc->srr; |
2442 |
break;
|
2443 |
case PPC405EP_CPC0_JTAGID:
|
2444 |
ret = cpc->jtagid; |
2445 |
break;
|
2446 |
case PPC405EP_CPC0_PCI:
|
2447 |
ret = cpc->pci; |
2448 |
break;
|
2449 |
default:
|
2450 |
/* Avoid gcc warning */
|
2451 |
ret = 0;
|
2452 |
break;
|
2453 |
} |
2454 |
|
2455 |
return ret;
|
2456 |
} |
2457 |
|
2458 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
2459 |
{ |
2460 |
ppc405ep_cpc_t *cpc; |
2461 |
|
2462 |
cpc = opaque; |
2463 |
switch (dcrn) {
|
2464 |
case PPC405EP_CPC0_BOOT:
|
2465 |
/* Read-only register */
|
2466 |
break;
|
2467 |
case PPC405EP_CPC0_EPCTL:
|
2468 |
/* Don't care for now */
|
2469 |
cpc->epctl = val & 0xC00000F3;
|
2470 |
break;
|
2471 |
case PPC405EP_CPC0_PLLMR0:
|
2472 |
cpc->pllmr[0] = val & 0x00633333; |
2473 |
ppc405ep_compute_clocks(cpc); |
2474 |
break;
|
2475 |
case PPC405EP_CPC0_PLLMR1:
|
2476 |
cpc->pllmr[1] = val & 0xC0F73FFF; |
2477 |
ppc405ep_compute_clocks(cpc); |
2478 |
break;
|
2479 |
case PPC405EP_CPC0_UCR:
|
2480 |
/* UART control - don't care for now */
|
2481 |
cpc->ucr = val & 0x003F7F7F;
|
2482 |
break;
|
2483 |
case PPC405EP_CPC0_SRR:
|
2484 |
cpc->srr = val; |
2485 |
break;
|
2486 |
case PPC405EP_CPC0_JTAGID:
|
2487 |
/* Read-only */
|
2488 |
break;
|
2489 |
case PPC405EP_CPC0_PCI:
|
2490 |
cpc->pci = val; |
2491 |
break;
|
2492 |
} |
2493 |
} |
2494 |
|
2495 |
static void ppc405ep_cpc_reset (void *opaque) |
2496 |
{ |
2497 |
ppc405ep_cpc_t *cpc = opaque; |
2498 |
|
2499 |
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
2500 |
cpc->epctl = 0x00000000;
|
2501 |
cpc->pllmr[0] = 0x00011010; |
2502 |
cpc->pllmr[1] = 0x40000000; |
2503 |
cpc->ucr = 0x00000000;
|
2504 |
cpc->srr = 0x00040000;
|
2505 |
cpc->pci = 0x00000000;
|
2506 |
cpc->er = 0x00000000;
|
2507 |
cpc->fr = 0x00000000;
|
2508 |
cpc->sr = 0x00000000;
|
2509 |
ppc405ep_compute_clocks(cpc); |
2510 |
} |
2511 |
|
2512 |
/* XXX: sysclk should be between 25 and 100 MHz */
|
2513 |
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
2514 |
uint32_t sysclk) |
2515 |
{ |
2516 |
ppc405ep_cpc_t *cpc; |
2517 |
|
2518 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
2519 |
if (cpc != NULL) { |
2520 |
memcpy(cpc->clk_setup, clk_setup, |
2521 |
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
2522 |
cpc->jtagid = 0x20267049;
|
2523 |
cpc->sysclk = sysclk; |
2524 |
ppc405ep_cpc_reset(cpc); |
2525 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
2526 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
2527 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2528 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
2529 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2530 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
2531 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2532 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
2533 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2534 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
2535 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2536 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
2537 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2538 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
2539 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2540 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
2541 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2542 |
#if 0
|
2543 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
2544 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2545 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
2546 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2547 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
2548 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2549 |
#endif
|
2550 |
} |
2551 |
} |
2552 |
|
2553 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
2554 |
target_phys_addr_t ram_sizes[2],
|
2555 |
uint32_t sysclk, qemu_irq **picp, |
2556 |
ram_addr_t *offsetp, int do_init)
|
2557 |
{ |
2558 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2559 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2560 |
CPUState *env; |
2561 |
ppc4xx_mmio_t *mmio; |
2562 |
qemu_irq *pic, *irqs; |
2563 |
ram_addr_t offset; |
2564 |
int i;
|
2565 |
|
2566 |
memset(clk_setup, 0, sizeof(clk_setup)); |
2567 |
/* init CPUs */
|
2568 |
env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
2569 |
&tlb_clk_setup, sysclk); |
2570 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
2571 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
2572 |
/* Internal devices init */
|
2573 |
/* Memory mapped devices registers */
|
2574 |
mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
2575 |
/* PLB arbitrer */
|
2576 |
ppc4xx_plb_init(env); |
2577 |
/* PLB to OPB bridge */
|
2578 |
ppc4xx_pob_init(env); |
2579 |
/* OBP arbitrer */
|
2580 |
ppc4xx_opba_init(env, mmio, 0x600);
|
2581 |
/* Universal interrupt controller */
|
2582 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2583 |
irqs[PPCUIC_OUTPUT_INT] = |
2584 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2585 |
irqs[PPCUIC_OUTPUT_CINT] = |
2586 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2587 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2588 |
*picp = pic; |
2589 |
/* SDRAM controller */
|
2590 |
/* XXX 405EP has no ECC interrupt */
|
2591 |
ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
2592 |
offset = 0;
|
2593 |
for (i = 0; i < 2; i++) |
2594 |
offset += ram_sizes[i]; |
2595 |
/* External bus controller */
|
2596 |
ppc405_ebc_init(env); |
2597 |
/* DMA controller */
|
2598 |
dma_irqs[0] = pic[5]; |
2599 |
dma_irqs[1] = pic[6]; |
2600 |
dma_irqs[2] = pic[7]; |
2601 |
dma_irqs[3] = pic[8]; |
2602 |
ppc405_dma_init(env, dma_irqs); |
2603 |
/* IIC controller */
|
2604 |
ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
2605 |
/* GPIO */
|
2606 |
ppc405_gpio_init(env, mmio, 0x700);
|
2607 |
/* Serial ports */
|
2608 |
if (serial_hds[0] != NULL) { |
2609 |
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
2610 |
} |
2611 |
if (serial_hds[1] != NULL) { |
2612 |
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
2613 |
} |
2614 |
/* OCM */
|
2615 |
ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
2616 |
offset += 4096;
|
2617 |
/* GPT */
|
2618 |
gpt_irqs[0] = pic[19]; |
2619 |
gpt_irqs[1] = pic[20]; |
2620 |
gpt_irqs[2] = pic[21]; |
2621 |
gpt_irqs[3] = pic[22]; |
2622 |
gpt_irqs[4] = pic[23]; |
2623 |
ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
|
2624 |
/* PCI */
|
2625 |
/* Uses pic[3], pic[16], pic[18] */
|
2626 |
/* MAL */
|
2627 |
mal_irqs[0] = pic[11]; |
2628 |
mal_irqs[1] = pic[12]; |
2629 |
mal_irqs[2] = pic[13]; |
2630 |
mal_irqs[3] = pic[14]; |
2631 |
ppc405_mal_init(env, mal_irqs); |
2632 |
/* Ethernet */
|
2633 |
/* Uses pic[9], pic[15], pic[17] */
|
2634 |
/* CPU control */
|
2635 |
ppc405ep_cpc_init(env, clk_setup, sysclk); |
2636 |
*offsetp = offset; |
2637 |
|
2638 |
return env;
|
2639 |
} |