root / hw / arm_gic.c @ 477afee3
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 9ee6e8bb | pbrook | controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 9ee6e8bb | pbrook | Nested Vectored Interrupt Controller. */
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13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | //#define DEBUG_GIC
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15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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17 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) \
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18 | df628ff1 | pbrook | do { printf("arm_gic: " fmt , ##args); } while (0) |
19 | e69954b9 | pbrook | #else
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20 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
21 | e69954b9 | pbrook | #endif
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22 | e69954b9 | pbrook | |
23 | 9ee6e8bb | pbrook | #ifdef NVIC
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24 | 9ee6e8bb | pbrook | static const uint8_t gic_id[] = |
25 | 9ee6e8bb | pbrook | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
26 | 9ee6e8bb | pbrook | #define GIC_DIST_OFFSET 0 |
27 | 9ee6e8bb | pbrook | /* The NVIC has 16 internal vectors. However these are not exposed
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28 | 9ee6e8bb | pbrook | through the normal GIC interface. */
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29 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 32 |
30 | 9ee6e8bb | pbrook | #else
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31 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
32 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
33 | 9ee6e8bb | pbrook | #define GIC_DIST_OFFSET 0x1000 |
34 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 0 |
35 | 9ee6e8bb | pbrook | #endif
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36 | e69954b9 | pbrook | |
37 | e69954b9 | pbrook | typedef struct gic_irq_state |
38 | e69954b9 | pbrook | { |
39 | 9ee6e8bb | pbrook | /* ??? The documentation seems to imply the enable bits are global, even
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40 | 9ee6e8bb | pbrook | for per-cpu interrupts. This seems strange. */
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41 | e69954b9 | pbrook | unsigned enabled:1; |
42 | 9ee6e8bb | pbrook | unsigned pending:NCPU;
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43 | 9ee6e8bb | pbrook | unsigned active:NCPU;
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44 | e69954b9 | pbrook | unsigned level:1; |
45 | 9ee6e8bb | pbrook | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
46 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
47 | e69954b9 | pbrook | } gic_irq_state; |
48 | e69954b9 | pbrook | |
49 | 9ee6e8bb | pbrook | #define ALL_CPU_MASK ((1 << NCPU) - 1) |
50 | 9ee6e8bb | pbrook | |
51 | e69954b9 | pbrook | #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
52 | e69954b9 | pbrook | #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
53 | e69954b9 | pbrook | #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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54 | 9ee6e8bb | pbrook | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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55 | 9ee6e8bb | pbrook | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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56 | 9ee6e8bb | pbrook | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
57 | 9ee6e8bb | pbrook | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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58 | 9ee6e8bb | pbrook | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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59 | 9ee6e8bb | pbrook | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
60 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
61 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
62 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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63 | 9ee6e8bb | pbrook | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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64 | 9ee6e8bb | pbrook | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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65 | 9ee6e8bb | pbrook | #define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0 |
66 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
67 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
68 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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69 | 9ee6e8bb | pbrook | #define GIC_GET_PRIORITY(irq, cpu) \
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70 | 9ee6e8bb | pbrook | (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32]) |
71 | 9ee6e8bb | pbrook | #ifdef NVIC
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72 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) 1 |
73 | 9ee6e8bb | pbrook | #else
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74 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) s->irq_target[irq]
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75 | 9ee6e8bb | pbrook | #endif
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76 | e69954b9 | pbrook | |
77 | e69954b9 | pbrook | typedef struct gic_state |
78 | e69954b9 | pbrook | { |
79 | e69954b9 | pbrook | uint32_t base; |
80 | 9ee6e8bb | pbrook | qemu_irq parent_irq[NCPU]; |
81 | e69954b9 | pbrook | int enabled;
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82 | 9ee6e8bb | pbrook | int cpu_enabled[NCPU];
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83 | e69954b9 | pbrook | |
84 | e69954b9 | pbrook | gic_irq_state irq_state[GIC_NIRQ]; |
85 | 9ee6e8bb | pbrook | #ifndef NVIC
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86 | e69954b9 | pbrook | int irq_target[GIC_NIRQ];
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87 | 9ee6e8bb | pbrook | #endif
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88 | 9ee6e8bb | pbrook | int priority1[32][NCPU]; |
89 | 9ee6e8bb | pbrook | int priority2[GIC_NIRQ - 32]; |
90 | 9ee6e8bb | pbrook | int last_active[GIC_NIRQ][NCPU];
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91 | 9ee6e8bb | pbrook | |
92 | 9ee6e8bb | pbrook | int priority_mask[NCPU];
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93 | 9ee6e8bb | pbrook | int running_irq[NCPU];
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94 | 9ee6e8bb | pbrook | int running_priority[NCPU];
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95 | 9ee6e8bb | pbrook | int current_pending[NCPU];
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96 | 9ee6e8bb | pbrook | |
97 | 9ee6e8bb | pbrook | qemu_irq *in; |
98 | 9ee6e8bb | pbrook | #ifdef NVIC
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99 | 9ee6e8bb | pbrook | void *nvic;
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100 | 9ee6e8bb | pbrook | #endif
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101 | e69954b9 | pbrook | } gic_state; |
102 | e69954b9 | pbrook | |
103 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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104 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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105 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
106 | e69954b9 | pbrook | { |
107 | e69954b9 | pbrook | int best_irq;
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108 | e69954b9 | pbrook | int best_prio;
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109 | e69954b9 | pbrook | int irq;
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110 | 9ee6e8bb | pbrook | int level;
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111 | 9ee6e8bb | pbrook | int cpu;
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112 | 9ee6e8bb | pbrook | int cm;
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113 | 9ee6e8bb | pbrook | |
114 | 9ee6e8bb | pbrook | for (cpu = 0; cpu < NCPU; cpu++) { |
115 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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116 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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117 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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118 | 9ee6e8bb | pbrook | qemu_irq_lower(s->parent_irq[cpu]); |
119 | 9ee6e8bb | pbrook | return;
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120 | 9ee6e8bb | pbrook | } |
121 | 9ee6e8bb | pbrook | best_prio = 0x100;
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122 | 9ee6e8bb | pbrook | best_irq = 1023;
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123 | 9ee6e8bb | pbrook | for (irq = 0; irq < GIC_NIRQ; irq++) { |
124 | 9ee6e8bb | pbrook | if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
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125 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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126 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
127 | 9ee6e8bb | pbrook | best_irq = irq; |
128 | 9ee6e8bb | pbrook | } |
129 | e69954b9 | pbrook | } |
130 | e69954b9 | pbrook | } |
131 | 9ee6e8bb | pbrook | level = 0;
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132 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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133 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
134 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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135 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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136 | 9ee6e8bb | pbrook | level = 1;
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137 | 9ee6e8bb | pbrook | } |
138 | e69954b9 | pbrook | } |
139 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
140 | e69954b9 | pbrook | } |
141 | e69954b9 | pbrook | } |
142 | e69954b9 | pbrook | |
143 | 9ee6e8bb | pbrook | static void __attribute__((unused)) |
144 | 9ee6e8bb | pbrook | gic_set_pending_private(gic_state *s, int cpu, int irq) |
145 | 9ee6e8bb | pbrook | { |
146 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
147 | 9ee6e8bb | pbrook | |
148 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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149 | 9ee6e8bb | pbrook | return;
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150 | 9ee6e8bb | pbrook | |
151 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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152 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
153 | 9ee6e8bb | pbrook | gic_update(s); |
154 | 9ee6e8bb | pbrook | } |
155 | 9ee6e8bb | pbrook | |
156 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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157 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
158 | e69954b9 | pbrook | { |
159 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
160 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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161 | e69954b9 | pbrook | irq += 32;
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162 | 9ee6e8bb | pbrook | if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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163 | e69954b9 | pbrook | return;
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164 | e69954b9 | pbrook | |
165 | e69954b9 | pbrook | if (level) {
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166 | 9ee6e8bb | pbrook | GIC_SET_LEVEL(irq, ALL_CPU_MASK); |
167 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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168 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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169 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, GIC_TARGET(irq)); |
170 | e69954b9 | pbrook | } |
171 | e69954b9 | pbrook | } else {
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172 | 9ee6e8bb | pbrook | GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); |
173 | e69954b9 | pbrook | } |
174 | e69954b9 | pbrook | gic_update(s); |
175 | e69954b9 | pbrook | } |
176 | e69954b9 | pbrook | |
177 | 9ee6e8bb | pbrook | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
178 | e69954b9 | pbrook | { |
179 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
180 | 9ee6e8bb | pbrook | if (irq == 1023) { |
181 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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182 | 9ee6e8bb | pbrook | } else {
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183 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
184 | 9ee6e8bb | pbrook | } |
185 | e69954b9 | pbrook | gic_update(s); |
186 | e69954b9 | pbrook | } |
187 | e69954b9 | pbrook | |
188 | 9ee6e8bb | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
189 | e69954b9 | pbrook | { |
190 | e69954b9 | pbrook | int new_irq;
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191 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
192 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
193 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
194 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
195 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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196 | e69954b9 | pbrook | return 1023; |
197 | e69954b9 | pbrook | } |
198 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
199 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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200 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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201 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
202 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
203 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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204 | e69954b9 | pbrook | return new_irq;
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205 | e69954b9 | pbrook | } |
206 | e69954b9 | pbrook | |
207 | 9ee6e8bb | pbrook | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
208 | e69954b9 | pbrook | { |
209 | e69954b9 | pbrook | int update = 0; |
210 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
211 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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212 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
213 | e69954b9 | pbrook | return; /* No active IRQ. */ |
214 | e69954b9 | pbrook | if (irq != 1023) { |
215 | e69954b9 | pbrook | /* Mark level triggered interrupts as pending if they are still
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216 | e69954b9 | pbrook | raised. */
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217 | e69954b9 | pbrook | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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218 | 9ee6e8bb | pbrook | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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219 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, cm);
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220 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
221 | e69954b9 | pbrook | update = 1;
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222 | e69954b9 | pbrook | } |
223 | e69954b9 | pbrook | } |
224 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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225 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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226 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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227 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
228 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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229 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
230 | e69954b9 | pbrook | break;
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231 | e69954b9 | pbrook | } |
232 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
233 | e69954b9 | pbrook | } |
234 | e69954b9 | pbrook | if (update) {
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235 | e69954b9 | pbrook | gic_update(s); |
236 | e69954b9 | pbrook | } |
237 | e69954b9 | pbrook | } else {
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238 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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239 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
240 | e69954b9 | pbrook | } |
241 | e69954b9 | pbrook | } |
242 | e69954b9 | pbrook | |
243 | e69954b9 | pbrook | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
244 | e69954b9 | pbrook | { |
245 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
246 | e69954b9 | pbrook | uint32_t res; |
247 | e69954b9 | pbrook | int irq;
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248 | e69954b9 | pbrook | int i;
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249 | 9ee6e8bb | pbrook | int cpu;
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250 | 9ee6e8bb | pbrook | int cm;
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251 | 9ee6e8bb | pbrook | int mask;
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252 | e69954b9 | pbrook | |
253 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
254 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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255 | 9ee6e8bb | pbrook | offset -= s->base + GIC_DIST_OFFSET; |
256 | e69954b9 | pbrook | if (offset < 0x100) { |
257 | 9ee6e8bb | pbrook | #ifndef NVIC
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258 | e69954b9 | pbrook | if (offset == 0) |
259 | e69954b9 | pbrook | return s->enabled;
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260 | e69954b9 | pbrook | if (offset == 4) |
261 | 9ee6e8bb | pbrook | return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5); |
262 | e69954b9 | pbrook | if (offset < 0x08) |
263 | e69954b9 | pbrook | return 0; |
264 | 9ee6e8bb | pbrook | #endif
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265 | e69954b9 | pbrook | goto bad_reg;
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266 | e69954b9 | pbrook | } else if (offset < 0x200) { |
267 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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268 | e69954b9 | pbrook | if (offset < 0x180) |
269 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
270 | e69954b9 | pbrook | else
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271 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
272 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
273 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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274 | e69954b9 | pbrook | goto bad_reg;
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275 | e69954b9 | pbrook | res = 0;
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276 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
277 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i)) {
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278 | e69954b9 | pbrook | res |= (1 << i);
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279 | e69954b9 | pbrook | } |
280 | e69954b9 | pbrook | } |
281 | e69954b9 | pbrook | } else if (offset < 0x300) { |
282 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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283 | e69954b9 | pbrook | if (offset < 0x280) |
284 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
285 | e69954b9 | pbrook | else
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286 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
287 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
288 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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289 | e69954b9 | pbrook | goto bad_reg;
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290 | e69954b9 | pbrook | res = 0;
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291 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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292 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
293 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
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294 | e69954b9 | pbrook | res |= (1 << i);
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295 | e69954b9 | pbrook | } |
296 | e69954b9 | pbrook | } |
297 | e69954b9 | pbrook | } else if (offset < 0x400) { |
298 | e69954b9 | pbrook | /* Interrupt Active. */
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299 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
300 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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301 | e69954b9 | pbrook | goto bad_reg;
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302 | e69954b9 | pbrook | res = 0;
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303 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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304 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
305 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
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306 | e69954b9 | pbrook | res |= (1 << i);
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307 | e69954b9 | pbrook | } |
308 | e69954b9 | pbrook | } |
309 | e69954b9 | pbrook | } else if (offset < 0x800) { |
310 | e69954b9 | pbrook | /* Interrupt Priority. */
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311 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
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312 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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313 | e69954b9 | pbrook | goto bad_reg;
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314 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
315 | 9ee6e8bb | pbrook | #ifndef NVIC
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316 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
317 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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318 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
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319 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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320 | e69954b9 | pbrook | goto bad_reg;
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321 | 9ee6e8bb | pbrook | if (irq >= 29 && irq <= 31) { |
322 | 9ee6e8bb | pbrook | res = cm; |
323 | 9ee6e8bb | pbrook | } else {
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324 | 9ee6e8bb | pbrook | res = GIC_TARGET(irq); |
325 | 9ee6e8bb | pbrook | } |
326 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
327 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
328 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
329 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
330 | e69954b9 | pbrook | goto bad_reg;
|
331 | e69954b9 | pbrook | res = 0;
|
332 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
333 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
|
334 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
335 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
|
336 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
337 | e69954b9 | pbrook | } |
338 | 9ee6e8bb | pbrook | #endif
|
339 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
340 | e69954b9 | pbrook | goto bad_reg;
|
341 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
342 | e69954b9 | pbrook | if (offset & 3) { |
343 | e69954b9 | pbrook | res = 0;
|
344 | e69954b9 | pbrook | } else {
|
345 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
346 | e69954b9 | pbrook | } |
347 | e69954b9 | pbrook | } |
348 | e69954b9 | pbrook | return res;
|
349 | e69954b9 | pbrook | bad_reg:
|
350 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset); |
351 | e69954b9 | pbrook | return 0; |
352 | e69954b9 | pbrook | } |
353 | e69954b9 | pbrook | |
354 | e69954b9 | pbrook | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
355 | e69954b9 | pbrook | { |
356 | e69954b9 | pbrook | uint32_t val; |
357 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
358 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
359 | e69954b9 | pbrook | return val;
|
360 | e69954b9 | pbrook | } |
361 | e69954b9 | pbrook | |
362 | e69954b9 | pbrook | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
363 | e69954b9 | pbrook | { |
364 | e69954b9 | pbrook | uint32_t val; |
365 | 9ee6e8bb | pbrook | #ifdef NVIC
|
366 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
367 | 9ee6e8bb | pbrook | uint32_t addr; |
368 | 9ee6e8bb | pbrook | addr = offset - s->base; |
369 | 9ee6e8bb | pbrook | if (addr < 0x100 || addr > 0xd00) |
370 | 9ee6e8bb | pbrook | return nvic_readl(s->nvic, addr);
|
371 | 9ee6e8bb | pbrook | #endif
|
372 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
373 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
374 | e69954b9 | pbrook | return val;
|
375 | e69954b9 | pbrook | } |
376 | e69954b9 | pbrook | |
377 | e69954b9 | pbrook | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
378 | e69954b9 | pbrook | uint32_t value) |
379 | e69954b9 | pbrook | { |
380 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
381 | e69954b9 | pbrook | int irq;
|
382 | e69954b9 | pbrook | int i;
|
383 | 9ee6e8bb | pbrook | int cpu;
|
384 | e69954b9 | pbrook | |
385 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
386 | 9ee6e8bb | pbrook | offset -= s->base + GIC_DIST_OFFSET; |
387 | e69954b9 | pbrook | if (offset < 0x100) { |
388 | 9ee6e8bb | pbrook | #ifdef NVIC
|
389 | 9ee6e8bb | pbrook | goto bad_reg;
|
390 | 9ee6e8bb | pbrook | #else
|
391 | e69954b9 | pbrook | if (offset == 0) { |
392 | e69954b9 | pbrook | s->enabled = (value & 1);
|
393 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
394 | e69954b9 | pbrook | } else if (offset < 4) { |
395 | e69954b9 | pbrook | /* ignored. */
|
396 | e69954b9 | pbrook | } else {
|
397 | e69954b9 | pbrook | goto bad_reg;
|
398 | e69954b9 | pbrook | } |
399 | 9ee6e8bb | pbrook | #endif
|
400 | e69954b9 | pbrook | } else if (offset < 0x180) { |
401 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
402 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
403 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
404 | e69954b9 | pbrook | goto bad_reg;
|
405 | 9ee6e8bb | pbrook | if (irq < 16) |
406 | 9ee6e8bb | pbrook | value = 0xff;
|
407 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
408 | e69954b9 | pbrook | if (value & (1 << i)) { |
409 | 9ee6e8bb | pbrook | int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq); |
410 | e69954b9 | pbrook | if (!GIC_TEST_ENABLED(irq + i))
|
411 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
412 | e69954b9 | pbrook | GIC_SET_ENABLED(irq + i); |
413 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
414 | e69954b9 | pbrook | is as pending. */
|
415 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
416 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
417 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
418 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
419 | 9ee6e8bb | pbrook | } |
420 | e69954b9 | pbrook | } |
421 | e69954b9 | pbrook | } |
422 | e69954b9 | pbrook | } else if (offset < 0x200) { |
423 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
424 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
425 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
426 | e69954b9 | pbrook | goto bad_reg;
|
427 | 9ee6e8bb | pbrook | if (irq < 16) |
428 | 9ee6e8bb | pbrook | value = 0;
|
429 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
430 | e69954b9 | pbrook | if (value & (1 << i)) { |
431 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i))
|
432 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
433 | e69954b9 | pbrook | GIC_CLEAR_ENABLED(irq + i); |
434 | e69954b9 | pbrook | } |
435 | e69954b9 | pbrook | } |
436 | e69954b9 | pbrook | } else if (offset < 0x280) { |
437 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
438 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
439 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
440 | e69954b9 | pbrook | goto bad_reg;
|
441 | 9ee6e8bb | pbrook | if (irq < 16) |
442 | 9ee6e8bb | pbrook | irq = 0;
|
443 | 9ee6e8bb | pbrook | |
444 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
445 | e69954b9 | pbrook | if (value & (1 << i)) { |
446 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
447 | e69954b9 | pbrook | } |
448 | e69954b9 | pbrook | } |
449 | e69954b9 | pbrook | } else if (offset < 0x300) { |
450 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
451 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
452 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
453 | e69954b9 | pbrook | goto bad_reg;
|
454 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
455 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
456 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
457 | 9ee6e8bb | pbrook | corect behavior. */
|
458 | e69954b9 | pbrook | if (value & (1 << i)) { |
459 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
460 | e69954b9 | pbrook | } |
461 | e69954b9 | pbrook | } |
462 | e69954b9 | pbrook | } else if (offset < 0x400) { |
463 | e69954b9 | pbrook | /* Interrupt Active. */
|
464 | e69954b9 | pbrook | goto bad_reg;
|
465 | e69954b9 | pbrook | } else if (offset < 0x800) { |
466 | e69954b9 | pbrook | /* Interrupt Priority. */
|
467 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
468 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
469 | e69954b9 | pbrook | goto bad_reg;
|
470 | 9ee6e8bb | pbrook | if (irq < 32) { |
471 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
472 | 9ee6e8bb | pbrook | } else {
|
473 | 9ee6e8bb | pbrook | s->priority2[irq - 32] = value;
|
474 | 9ee6e8bb | pbrook | } |
475 | 9ee6e8bb | pbrook | #ifndef NVIC
|
476 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
477 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
478 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
479 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
480 | e69954b9 | pbrook | goto bad_reg;
|
481 | 9ee6e8bb | pbrook | if (irq < 29) |
482 | 9ee6e8bb | pbrook | value = 0;
|
483 | 9ee6e8bb | pbrook | else if (irq < 32) |
484 | 9ee6e8bb | pbrook | value = ALL_CPU_MASK; |
485 | 9ee6e8bb | pbrook | s->irq_target[irq] = value & ALL_CPU_MASK; |
486 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
487 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
488 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
489 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
490 | e69954b9 | pbrook | goto bad_reg;
|
491 | 9ee6e8bb | pbrook | if (irq < 32) |
492 | 9ee6e8bb | pbrook | value |= 0xaa;
|
493 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
494 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
495 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
496 | e69954b9 | pbrook | } else {
|
497 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
498 | e69954b9 | pbrook | } |
499 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
500 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
501 | e69954b9 | pbrook | } else {
|
502 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
503 | e69954b9 | pbrook | } |
504 | e69954b9 | pbrook | } |
505 | 9ee6e8bb | pbrook | #endif
|
506 | e69954b9 | pbrook | } else {
|
507 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
508 | e69954b9 | pbrook | goto bad_reg;
|
509 | e69954b9 | pbrook | } |
510 | e69954b9 | pbrook | gic_update(s); |
511 | e69954b9 | pbrook | return;
|
512 | e69954b9 | pbrook | bad_reg:
|
513 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset); |
514 | e69954b9 | pbrook | } |
515 | e69954b9 | pbrook | |
516 | e69954b9 | pbrook | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
517 | e69954b9 | pbrook | uint32_t value) |
518 | e69954b9 | pbrook | { |
519 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
520 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
521 | e69954b9 | pbrook | } |
522 | e69954b9 | pbrook | |
523 | e69954b9 | pbrook | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
524 | e69954b9 | pbrook | uint32_t value) |
525 | e69954b9 | pbrook | { |
526 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
527 | 9ee6e8bb | pbrook | #ifdef NVIC
|
528 | 9ee6e8bb | pbrook | uint32_t addr; |
529 | 9ee6e8bb | pbrook | addr = offset - s->base; |
530 | 9ee6e8bb | pbrook | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
531 | 9ee6e8bb | pbrook | nvic_writel(s->nvic, addr, value); |
532 | 9ee6e8bb | pbrook | return;
|
533 | 9ee6e8bb | pbrook | } |
534 | 9ee6e8bb | pbrook | #endif
|
535 | 9ee6e8bb | pbrook | if (offset - s->base == GIC_DIST_OFFSET + 0xf00) { |
536 | 9ee6e8bb | pbrook | int cpu;
|
537 | 9ee6e8bb | pbrook | int irq;
|
538 | 9ee6e8bb | pbrook | int mask;
|
539 | 9ee6e8bb | pbrook | |
540 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
541 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
542 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
543 | 9ee6e8bb | pbrook | case 0: |
544 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
545 | 9ee6e8bb | pbrook | break;
|
546 | 9ee6e8bb | pbrook | case 1: |
547 | 9ee6e8bb | pbrook | mask = 1 << cpu;
|
548 | 9ee6e8bb | pbrook | break;
|
549 | 9ee6e8bb | pbrook | case 2: |
550 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK ^ (1 << cpu);
|
551 | 9ee6e8bb | pbrook | break;
|
552 | 9ee6e8bb | pbrook | default:
|
553 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
554 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
555 | 9ee6e8bb | pbrook | break;
|
556 | 9ee6e8bb | pbrook | } |
557 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
558 | 9ee6e8bb | pbrook | gic_update(s); |
559 | 9ee6e8bb | pbrook | return;
|
560 | 9ee6e8bb | pbrook | } |
561 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
562 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
563 | e69954b9 | pbrook | } |
564 | e69954b9 | pbrook | |
565 | e69954b9 | pbrook | static CPUReadMemoryFunc *gic_dist_readfn[] = {
|
566 | e69954b9 | pbrook | gic_dist_readb, |
567 | e69954b9 | pbrook | gic_dist_readw, |
568 | e69954b9 | pbrook | gic_dist_readl |
569 | e69954b9 | pbrook | }; |
570 | e69954b9 | pbrook | |
571 | e69954b9 | pbrook | static CPUWriteMemoryFunc *gic_dist_writefn[] = {
|
572 | e69954b9 | pbrook | gic_dist_writeb, |
573 | e69954b9 | pbrook | gic_dist_writew, |
574 | e69954b9 | pbrook | gic_dist_writel |
575 | e69954b9 | pbrook | }; |
576 | e69954b9 | pbrook | |
577 | 9ee6e8bb | pbrook | #ifndef NVIC
|
578 | 9ee6e8bb | pbrook | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
579 | e69954b9 | pbrook | { |
580 | e69954b9 | pbrook | switch (offset) {
|
581 | e69954b9 | pbrook | case 0x00: /* Control */ |
582 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
583 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
584 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
585 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
586 | e69954b9 | pbrook | /* ??? Not implemented. */
|
587 | e69954b9 | pbrook | return 0; |
588 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
589 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
590 | e69954b9 | pbrook | case 0x14: /* Runing Priority */ |
591 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
592 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
593 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
594 | e69954b9 | pbrook | default:
|
595 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
|
596 | 9ee6e8bb | pbrook | (int)offset);
|
597 | e69954b9 | pbrook | return 0; |
598 | e69954b9 | pbrook | } |
599 | e69954b9 | pbrook | } |
600 | e69954b9 | pbrook | |
601 | 9ee6e8bb | pbrook | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
602 | e69954b9 | pbrook | { |
603 | e69954b9 | pbrook | switch (offset) {
|
604 | e69954b9 | pbrook | case 0x00: /* Control */ |
605 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
606 | e69954b9 | pbrook | DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); |
607 | e69954b9 | pbrook | break;
|
608 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
609 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
610 | e69954b9 | pbrook | break;
|
611 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
612 | e69954b9 | pbrook | /* ??? Not implemented. */
|
613 | e69954b9 | pbrook | break;
|
614 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
615 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
616 | e69954b9 | pbrook | default:
|
617 | 9ee6e8bb | pbrook | cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
|
618 | 9ee6e8bb | pbrook | (int)offset);
|
619 | e69954b9 | pbrook | return;
|
620 | e69954b9 | pbrook | } |
621 | e69954b9 | pbrook | gic_update(s); |
622 | e69954b9 | pbrook | } |
623 | 9ee6e8bb | pbrook | #endif
|
624 | e69954b9 | pbrook | |
625 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
626 | e69954b9 | pbrook | { |
627 | e69954b9 | pbrook | int i;
|
628 | e69954b9 | pbrook | memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
629 | 9ee6e8bb | pbrook | for (i = 0 ; i < NCPU; i++) { |
630 | 9ee6e8bb | pbrook | s->priority_mask[i] = 0xf0;
|
631 | 9ee6e8bb | pbrook | s->current_pending[i] = 1023;
|
632 | 9ee6e8bb | pbrook | s->running_irq[i] = 1023;
|
633 | 9ee6e8bb | pbrook | s->running_priority[i] = 0x100;
|
634 | 9ee6e8bb | pbrook | #ifdef NVIC
|
635 | 9ee6e8bb | pbrook | /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
636 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 1;
|
637 | 9ee6e8bb | pbrook | #else
|
638 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 0;
|
639 | 9ee6e8bb | pbrook | #endif
|
640 | 9ee6e8bb | pbrook | } |
641 | e57ec016 | pbrook | for (i = 0; i < 16; i++) { |
642 | e69954b9 | pbrook | GIC_SET_ENABLED(i); |
643 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
644 | e69954b9 | pbrook | } |
645 | 9ee6e8bb | pbrook | #ifdef NVIC
|
646 | 9ee6e8bb | pbrook | /* The NVIC is always enabled. */
|
647 | 9ee6e8bb | pbrook | s->enabled = 1;
|
648 | 9ee6e8bb | pbrook | #else
|
649 | e69954b9 | pbrook | s->enabled = 0;
|
650 | 9ee6e8bb | pbrook | #endif
|
651 | e69954b9 | pbrook | } |
652 | e69954b9 | pbrook | |
653 | 9ee6e8bb | pbrook | static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
|
654 | e69954b9 | pbrook | { |
655 | e69954b9 | pbrook | gic_state *s; |
656 | e69954b9 | pbrook | int iomemtype;
|
657 | 9ee6e8bb | pbrook | int i;
|
658 | e69954b9 | pbrook | |
659 | e69954b9 | pbrook | s = (gic_state *)qemu_mallocz(sizeof(gic_state));
|
660 | e69954b9 | pbrook | if (!s)
|
661 | e69954b9 | pbrook | return NULL; |
662 | 9ee6e8bb | pbrook | s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ); |
663 | 9ee6e8bb | pbrook | for (i = 0; i < NCPU; i++) { |
664 | 9ee6e8bb | pbrook | s->parent_irq[i] = parent_irq[i]; |
665 | e69954b9 | pbrook | } |
666 | 9ee6e8bb | pbrook | iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
|
667 | 9ee6e8bb | pbrook | gic_dist_writefn, s); |
668 | 9ee6e8bb | pbrook | cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
|
669 | 9ee6e8bb | pbrook | iomemtype); |
670 | 9ee6e8bb | pbrook | s->base = base; |
671 | e69954b9 | pbrook | gic_reset(s); |
672 | 9ee6e8bb | pbrook | return s;
|
673 | e69954b9 | pbrook | } |