root / hw / sdhci.h @ 47934d0a
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1 | d7dfca08 | Igor Mitsyanko | /*
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2 | d7dfca08 | Igor Mitsyanko | * SD Association Host Standard Specification v2.0 controller emulation
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3 | d7dfca08 | Igor Mitsyanko | *
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4 | d7dfca08 | Igor Mitsyanko | * Copyright (c) 2011 Samsung Electronics Co., Ltd.
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5 | d7dfca08 | Igor Mitsyanko | * Mitsyanko Igor <i.mitsyanko@samsung.com>
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6 | d7dfca08 | Igor Mitsyanko | * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
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7 | d7dfca08 | Igor Mitsyanko | *
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8 | d7dfca08 | Igor Mitsyanko | * Based on MMC controller for Samsung S5PC1xx-based board emulation
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9 | d7dfca08 | Igor Mitsyanko | * by Alexey Merkulov and Vladimir Monakhov.
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10 | d7dfca08 | Igor Mitsyanko | *
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11 | d7dfca08 | Igor Mitsyanko | * This program is free software; you can redistribute it and/or modify it
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12 | d7dfca08 | Igor Mitsyanko | * under the terms of the GNU General Public License as published by the
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13 | d7dfca08 | Igor Mitsyanko | * Free Software Foundation; either version 2 of the License, or (at your
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14 | d7dfca08 | Igor Mitsyanko | * option) any later version.
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15 | d7dfca08 | Igor Mitsyanko | *
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16 | d7dfca08 | Igor Mitsyanko | * This program is distributed in the hope that it will be useful,
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17 | d7dfca08 | Igor Mitsyanko | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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18 | d7dfca08 | Igor Mitsyanko | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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19 | d7dfca08 | Igor Mitsyanko | * See the GNU General Public License for more details.
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20 | d7dfca08 | Igor Mitsyanko | *
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21 | d7dfca08 | Igor Mitsyanko | * You should have received a copy of the GNU General Public License along
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22 | d7dfca08 | Igor Mitsyanko | * with this program; if not, see <http://www.gnu.org/licenses/>.
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23 | d7dfca08 | Igor Mitsyanko | */
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24 | d7dfca08 | Igor Mitsyanko | |
25 | d7dfca08 | Igor Mitsyanko | #ifndef SDHCI_H
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26 | d7dfca08 | Igor Mitsyanko | #define SDHCI_H
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27 | d7dfca08 | Igor Mitsyanko | |
28 | d7dfca08 | Igor Mitsyanko | #include "qemu-common.h" |
29 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/sd.h" |
31 | d7dfca08 | Igor Mitsyanko | |
32 | d7dfca08 | Igor Mitsyanko | /* R/W SDMA System Address register 0x0 */
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33 | d7dfca08 | Igor Mitsyanko | #define SDHC_SYSAD 0x00 |
34 | d7dfca08 | Igor Mitsyanko | |
35 | d7dfca08 | Igor Mitsyanko | /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
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36 | d7dfca08 | Igor Mitsyanko | #define SDHC_BLKSIZE 0x04 |
37 | d7dfca08 | Igor Mitsyanko | |
38 | d7dfca08 | Igor Mitsyanko | /* R/W Blocks count for current transfer 0x0 */
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39 | d7dfca08 | Igor Mitsyanko | #define SDHC_BLKCNT 0x06 |
40 | d7dfca08 | Igor Mitsyanko | |
41 | d7dfca08 | Igor Mitsyanko | /* R/W Command Argument Register 0x0 */
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42 | d7dfca08 | Igor Mitsyanko | #define SDHC_ARGUMENT 0x08 |
43 | d7dfca08 | Igor Mitsyanko | |
44 | d7dfca08 | Igor Mitsyanko | /* R/W Transfer Mode Setting Register 0x0 */
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45 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNMOD 0x0C |
46 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNS_DMA 0x0001 |
47 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNS_BLK_CNT_EN 0x0002 |
48 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNS_ACMD12 0x0004 |
49 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNS_READ 0x0010 |
50 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRNS_MULTI 0x0020 |
51 | d7dfca08 | Igor Mitsyanko | |
52 | d7dfca08 | Igor Mitsyanko | /* R/W Command Register 0x0 */
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53 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMDREG 0x0E |
54 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_RSP_WITH_BUSY (3 << 0) |
55 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_DATA_PRESENT (1 << 5) |
56 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_SUSPEND (1 << 6) |
57 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_RESUME (1 << 7) |
58 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_ABORT ((1 << 6)|(1 << 7)) |
59 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7)) |
60 | d7dfca08 | Igor Mitsyanko | #define SDHC_COMMAND_TYPE(x) ((x) & SDHC_CMD_TYPE_MASK)
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61 | d7dfca08 | Igor Mitsyanko | |
62 | d7dfca08 | Igor Mitsyanko | /* ROC Response Register 0 0x0 */
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63 | d7dfca08 | Igor Mitsyanko | #define SDHC_RSPREG0 0x10 |
64 | d7dfca08 | Igor Mitsyanko | /* ROC Response Register 1 0x0 */
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65 | d7dfca08 | Igor Mitsyanko | #define SDHC_RSPREG1 0x14 |
66 | d7dfca08 | Igor Mitsyanko | /* ROC Response Register 2 0x0 */
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67 | d7dfca08 | Igor Mitsyanko | #define SDHC_RSPREG2 0x18 |
68 | d7dfca08 | Igor Mitsyanko | /* ROC Response Register 3 0x0 */
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69 | d7dfca08 | Igor Mitsyanko | #define SDHC_RSPREG3 0x1C |
70 | d7dfca08 | Igor Mitsyanko | |
71 | d7dfca08 | Igor Mitsyanko | /* R/W Buffer Data Register 0x0 */
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72 | d7dfca08 | Igor Mitsyanko | #define SDHC_BDATA 0x20 |
73 | d7dfca08 | Igor Mitsyanko | |
74 | d7dfca08 | Igor Mitsyanko | /* R/ROC Present State Register 0x000A0000 */
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75 | d7dfca08 | Igor Mitsyanko | #define SDHC_PRNSTS 0x24 |
76 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_INHIBIT 0x00000001 |
77 | d7dfca08 | Igor Mitsyanko | #define SDHC_DATA_INHIBIT 0x00000002 |
78 | d7dfca08 | Igor Mitsyanko | #define SDHC_DAT_LINE_ACTIVE 0x00000004 |
79 | d7dfca08 | Igor Mitsyanko | #define SDHC_DOING_WRITE 0x00000100 |
80 | d7dfca08 | Igor Mitsyanko | #define SDHC_DOING_READ 0x00000200 |
81 | d7dfca08 | Igor Mitsyanko | #define SDHC_SPACE_AVAILABLE 0x00000400 |
82 | d7dfca08 | Igor Mitsyanko | #define SDHC_DATA_AVAILABLE 0x00000800 |
83 | d7dfca08 | Igor Mitsyanko | #define SDHC_CARD_PRESENT 0x00010000 |
84 | d7dfca08 | Igor Mitsyanko | #define SDHC_CARD_DETECT 0x00040000 |
85 | d7dfca08 | Igor Mitsyanko | #define SDHC_WRITE_PROTECT 0x00080000 |
86 | d7dfca08 | Igor Mitsyanko | #define TRANSFERRING_DATA(x) \
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87 | d7dfca08 | Igor Mitsyanko | ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) |
88 | d7dfca08 | Igor Mitsyanko | |
89 | d7dfca08 | Igor Mitsyanko | /* R/W Host control Register 0x0 */
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90 | d7dfca08 | Igor Mitsyanko | #define SDHC_HOSTCTL 0x28 |
91 | d7dfca08 | Igor Mitsyanko | #define SDHC_CTRL_DMA_CHECK_MASK 0x18 |
92 | d7dfca08 | Igor Mitsyanko | #define SDHC_CTRL_SDMA 0x00 |
93 | d7dfca08 | Igor Mitsyanko | #define SDHC_CTRL_ADMA1_32 0x08 |
94 | d7dfca08 | Igor Mitsyanko | #define SDHC_CTRL_ADMA2_32 0x10 |
95 | d7dfca08 | Igor Mitsyanko | #define SDHC_CTRL_ADMA2_64 0x18 |
96 | d7dfca08 | Igor Mitsyanko | #define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
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97 | d7dfca08 | Igor Mitsyanko | |
98 | d7dfca08 | Igor Mitsyanko | /* R/W Power Control Register 0x0 */
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99 | d7dfca08 | Igor Mitsyanko | #define SDHC_PWRCON 0x29 |
100 | d7dfca08 | Igor Mitsyanko | #define SDHC_POWER_ON (1 << 0) |
101 | d7dfca08 | Igor Mitsyanko | |
102 | d7dfca08 | Igor Mitsyanko | /* R/W Block Gap Control Register 0x0 */
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103 | d7dfca08 | Igor Mitsyanko | #define SDHC_BLKGAP 0x2A |
104 | d7dfca08 | Igor Mitsyanko | #define SDHC_STOP_AT_GAP_REQ 0x01 |
105 | d7dfca08 | Igor Mitsyanko | #define SDHC_CONTINUE_REQ 0x02 |
106 | d7dfca08 | Igor Mitsyanko | |
107 | d7dfca08 | Igor Mitsyanko | /* R/W WakeUp Control Register 0x0 */
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108 | d7dfca08 | Igor Mitsyanko | #define SDHC_WAKCON 0x2B |
109 | d7dfca08 | Igor Mitsyanko | #define SDHC_WKUP_ON_INS (1 << 1) |
110 | d7dfca08 | Igor Mitsyanko | #define SDHC_WKUP_ON_RMV (1 << 2) |
111 | d7dfca08 | Igor Mitsyanko | |
112 | d7dfca08 | Igor Mitsyanko | /* CLKCON */
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113 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLKCON 0x2C |
114 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLOCK_INT_STABLE 0x0002 |
115 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLOCK_INT_EN 0x0001 |
116 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLOCK_SDCLK_EN (1 << 2) |
117 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLOCK_CHK_MASK 0x0007 |
118 | d7dfca08 | Igor Mitsyanko | #define SDHC_CLOCK_IS_ON(x) \
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119 | d7dfca08 | Igor Mitsyanko | (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK) |
120 | d7dfca08 | Igor Mitsyanko | |
121 | d7dfca08 | Igor Mitsyanko | /* R/W Timeout Control Register 0x0 */
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122 | d7dfca08 | Igor Mitsyanko | #define SDHC_TIMEOUTCON 0x2E |
123 | d7dfca08 | Igor Mitsyanko | |
124 | d7dfca08 | Igor Mitsyanko | /* R/W Software Reset Register 0x0 */
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125 | d7dfca08 | Igor Mitsyanko | #define SDHC_SWRST 0x2F |
126 | d7dfca08 | Igor Mitsyanko | #define SDHC_RESET_ALL 0x01 |
127 | d7dfca08 | Igor Mitsyanko | #define SDHC_RESET_CMD 0x02 |
128 | d7dfca08 | Igor Mitsyanko | #define SDHC_RESET_DATA 0x04 |
129 | d7dfca08 | Igor Mitsyanko | |
130 | d7dfca08 | Igor Mitsyanko | /* ROC/RW1C Normal Interrupt Status Register 0x0 */
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131 | d7dfca08 | Igor Mitsyanko | #define SDHC_NORINTSTS 0x30 |
132 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_ERR 0x8000 |
133 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_CMDCMP 0x0001 |
134 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_TRSCMP 0x0002 |
135 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_BLKGAP 0x0004 |
136 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_DMA 0x0008 |
137 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_WBUFRDY 0x0010 |
138 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_RBUFRDY 0x0020 |
139 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_INSERT 0x0040 |
140 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_REMOVE 0x0080 |
141 | d7dfca08 | Igor Mitsyanko | #define SDHC_NIS_CARDINT 0x0100 |
142 | d7dfca08 | Igor Mitsyanko | |
143 | d7dfca08 | Igor Mitsyanko | /* ROC/RW1C Error Interrupt Status Register 0x0 */
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144 | d7dfca08 | Igor Mitsyanko | #define SDHC_ERRINTSTS 0x32 |
145 | d7dfca08 | Igor Mitsyanko | #define SDHC_EIS_CMDTIMEOUT 0x0001 |
146 | d7dfca08 | Igor Mitsyanko | #define SDHC_EIS_BLKGAP 0x0004 |
147 | d7dfca08 | Igor Mitsyanko | #define SDHC_EIS_CMDIDX 0x0008 |
148 | d7dfca08 | Igor Mitsyanko | #define SDHC_EIS_CMD12ERR 0x0100 |
149 | d7dfca08 | Igor Mitsyanko | #define SDHC_EIS_ADMAERR 0x0200 |
150 | d7dfca08 | Igor Mitsyanko | |
151 | d7dfca08 | Igor Mitsyanko | /* R/W Normal Interrupt Status Enable Register 0x0 */
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152 | d7dfca08 | Igor Mitsyanko | #define SDHC_NORINTSTSEN 0x34 |
153 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_CMDCMP 0x0001 |
154 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_TRSCMP 0x0002 |
155 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_DMA 0x0008 |
156 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_WBUFRDY 0x0010 |
157 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_RBUFRDY 0x0020 |
158 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_INSERT 0x0040 |
159 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_REMOVE 0x0080 |
160 | d7dfca08 | Igor Mitsyanko | #define SDHC_NISEN_CARDINT 0x0100 |
161 | d7dfca08 | Igor Mitsyanko | |
162 | d7dfca08 | Igor Mitsyanko | /* R/W Error Interrupt Status Enable Register 0x0 */
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163 | d7dfca08 | Igor Mitsyanko | #define SDHC_ERRINTSTSEN 0x36 |
164 | d7dfca08 | Igor Mitsyanko | #define SDHC_EISEN_CMDTIMEOUT 0x0001 |
165 | d7dfca08 | Igor Mitsyanko | #define SDHC_EISEN_BLKGAP 0x0004 |
166 | d7dfca08 | Igor Mitsyanko | #define SDHC_EISEN_CMDIDX 0x0008 |
167 | d7dfca08 | Igor Mitsyanko | #define SDHC_EISEN_ADMAERR 0x0200 |
168 | d7dfca08 | Igor Mitsyanko | |
169 | d7dfca08 | Igor Mitsyanko | /* R/W Normal Interrupt Signal Enable Register 0x0 */
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170 | d7dfca08 | Igor Mitsyanko | #define SDHC_NORINTSIGEN 0x38 |
171 | d7dfca08 | Igor Mitsyanko | #define SDHC_NORINTSIG_INSERT (1 << 6) |
172 | d7dfca08 | Igor Mitsyanko | #define SDHC_NORINTSIG_REMOVE (1 << 7) |
173 | d7dfca08 | Igor Mitsyanko | |
174 | d7dfca08 | Igor Mitsyanko | /* R/W Error Interrupt Signal Enable Register 0x0 */
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175 | d7dfca08 | Igor Mitsyanko | #define SDHC_ERRINTSIGEN 0x3A |
176 | d7dfca08 | Igor Mitsyanko | |
177 | d7dfca08 | Igor Mitsyanko | /* ROC Auto CMD12 error status register 0x0 */
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178 | d7dfca08 | Igor Mitsyanko | #define SDHC_ACMD12ERRSTS 0x3C |
179 | d7dfca08 | Igor Mitsyanko | |
180 | d7dfca08 | Igor Mitsyanko | /* HWInit Capabilities Register 0x05E80080 */
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181 | d7dfca08 | Igor Mitsyanko | #define SDHC_CAPAREG 0x40 |
182 | d7dfca08 | Igor Mitsyanko | #define SDHC_CAN_DO_DMA 0x00400000 |
183 | d7dfca08 | Igor Mitsyanko | #define SDHC_CAN_DO_ADMA2 0x00080000 |
184 | d7dfca08 | Igor Mitsyanko | #define SDHC_CAN_DO_ADMA1 0x00100000 |
185 | d7dfca08 | Igor Mitsyanko | #define SDHC_64_BIT_BUS_SUPPORT (1 << 28) |
186 | d7dfca08 | Igor Mitsyanko | #define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) |
187 | d7dfca08 | Igor Mitsyanko | |
188 | d7dfca08 | Igor Mitsyanko | /* HWInit Maximum Current Capabilities Register 0x0 */
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189 | d7dfca08 | Igor Mitsyanko | #define SDHC_MAXCURR 0x48 |
190 | d7dfca08 | Igor Mitsyanko | |
191 | d7dfca08 | Igor Mitsyanko | /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
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192 | d7dfca08 | Igor Mitsyanko | #define SDHC_FEAER 0x50 |
193 | d7dfca08 | Igor Mitsyanko | /* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
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194 | d7dfca08 | Igor Mitsyanko | #define SDHC_FEERR 0x52 |
195 | d7dfca08 | Igor Mitsyanko | |
196 | d7dfca08 | Igor Mitsyanko | /* R/W ADMA Error Status Register 0x00 */
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197 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR 0x54 |
198 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR_LENGTH_MISMATCH (1 << 2) |
199 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR_STATE_ST_STOP (0 << 0) |
200 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR_STATE_ST_FDS (1 << 0) |
201 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR_STATE_ST_TFR (3 << 0) |
202 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMAERR_STATE_MASK (3 << 0) |
203 | d7dfca08 | Igor Mitsyanko | |
204 | d7dfca08 | Igor Mitsyanko | /* R/W ADMA System Address Register 0x00 */
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205 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMASYSADDR 0x58 |
206 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_SET_LEN (1 << 4) |
207 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_ACT_TRAN (1 << 5) |
208 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_ACT_LINK (3 << 4) |
209 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_INT (1 << 2) |
210 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_END (1 << 1) |
211 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_VALID (1 << 0) |
212 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_ATTR_ACT_MASK ((1 << 4)|(1 << 5)) |
213 | d7dfca08 | Igor Mitsyanko | |
214 | d7dfca08 | Igor Mitsyanko | /* Slot interrupt status */
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215 | d7dfca08 | Igor Mitsyanko | #define SDHC_SLOT_INT_STATUS 0xFC |
216 | d7dfca08 | Igor Mitsyanko | |
217 | d7dfca08 | Igor Mitsyanko | /* HWInit Host Controller Version Register 0x0401 */
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218 | d7dfca08 | Igor Mitsyanko | #define SDHC_HCVER 0xFE |
219 | d7dfca08 | Igor Mitsyanko | #define SD_HOST_SPECv2_VERS 0x2401 |
220 | d7dfca08 | Igor Mitsyanko | |
221 | d7dfca08 | Igor Mitsyanko | #define SDHC_REGISTERS_MAP_SIZE 0x100 |
222 | d7dfca08 | Igor Mitsyanko | #define SDHC_INSERTION_DELAY (get_ticks_per_sec())
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223 | d7dfca08 | Igor Mitsyanko | #define SDHC_TRANSFER_DELAY 100 |
224 | d7dfca08 | Igor Mitsyanko | #define SDHC_ADMA_DESCS_PER_DELAY 5 |
225 | d7dfca08 | Igor Mitsyanko | #define SDHC_CMD_RESPONSE (3 << 0) |
226 | d7dfca08 | Igor Mitsyanko | |
227 | d7dfca08 | Igor Mitsyanko | enum {
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228 | d7dfca08 | Igor Mitsyanko | sdhc_not_stopped = 0, /* normal SDHC state */ |
229 | d7dfca08 | Igor Mitsyanko | sdhc_gap_read = 1, /* SDHC stopped at block gap during read operation */ |
230 | d7dfca08 | Igor Mitsyanko | sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ |
231 | d7dfca08 | Igor Mitsyanko | }; |
232 | d7dfca08 | Igor Mitsyanko | |
233 | d7dfca08 | Igor Mitsyanko | /* SD/MMC host controller state */
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234 | d7dfca08 | Igor Mitsyanko | typedef struct SDHCIState { |
235 | d7dfca08 | Igor Mitsyanko | SysBusDevice busdev; |
236 | d7dfca08 | Igor Mitsyanko | SDState *card; |
237 | d7dfca08 | Igor Mitsyanko | MemoryRegion iomem; |
238 | d7dfca08 | Igor Mitsyanko | |
239 | d7dfca08 | Igor Mitsyanko | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
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240 | d7dfca08 | Igor Mitsyanko | QEMUTimer *transfer_timer; |
241 | d7dfca08 | Igor Mitsyanko | qemu_irq eject_cb; |
242 | d7dfca08 | Igor Mitsyanko | qemu_irq ro_cb; |
243 | d7dfca08 | Igor Mitsyanko | qemu_irq irq; |
244 | d7dfca08 | Igor Mitsyanko | |
245 | d7dfca08 | Igor Mitsyanko | uint32_t sdmasysad; /* SDMA System Address register */
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246 | d7dfca08 | Igor Mitsyanko | uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
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247 | d7dfca08 | Igor Mitsyanko | uint16_t blkcnt; /* Blocks count for current transfer */
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248 | d7dfca08 | Igor Mitsyanko | uint32_t argument; /* Command Argument Register */
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249 | d7dfca08 | Igor Mitsyanko | uint16_t trnmod; /* Transfer Mode Setting Register */
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250 | d7dfca08 | Igor Mitsyanko | uint16_t cmdreg; /* Command Register */
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251 | d7dfca08 | Igor Mitsyanko | uint32_t rspreg[4]; /* Response Registers 0-3 */ |
252 | d7dfca08 | Igor Mitsyanko | uint32_t prnsts; /* Present State Register */
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253 | d7dfca08 | Igor Mitsyanko | uint8_t hostctl; /* Host Control Register */
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254 | d7dfca08 | Igor Mitsyanko | uint8_t pwrcon; /* Power control Register */
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255 | d7dfca08 | Igor Mitsyanko | uint8_t blkgap; /* Block Gap Control Register */
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256 | d7dfca08 | Igor Mitsyanko | uint8_t wakcon; /* WakeUp Control Register */
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257 | d7dfca08 | Igor Mitsyanko | uint16_t clkcon; /* Clock control Register */
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258 | d7dfca08 | Igor Mitsyanko | uint8_t timeoutcon; /* Timeout Control Register */
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259 | d7dfca08 | Igor Mitsyanko | uint8_t admaerr; /* ADMA Error Status Register */
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260 | d7dfca08 | Igor Mitsyanko | uint16_t norintsts; /* Normal Interrupt Status Register */
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261 | d7dfca08 | Igor Mitsyanko | uint16_t errintsts; /* Error Interrupt Status Register */
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262 | d7dfca08 | Igor Mitsyanko | uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
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263 | d7dfca08 | Igor Mitsyanko | uint16_t errintstsen; /* Error Interrupt Status Enable Register */
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264 | d7dfca08 | Igor Mitsyanko | uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
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265 | d7dfca08 | Igor Mitsyanko | uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
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266 | d7dfca08 | Igor Mitsyanko | uint16_t acmd12errsts; /* Auto CMD12 error status register */
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267 | d7dfca08 | Igor Mitsyanko | uint64_t admasysaddr; /* ADMA System Address Register */
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268 | d7dfca08 | Igor Mitsyanko | |
269 | d7dfca08 | Igor Mitsyanko | uint32_t capareg; /* Capabilities Register */
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270 | d7dfca08 | Igor Mitsyanko | uint32_t maxcurr; /* Maximum Current Capabilities Register */
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271 | d7dfca08 | Igor Mitsyanko | uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
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272 | d7dfca08 | Igor Mitsyanko | uint32_t buf_maxsz; |
273 | d7dfca08 | Igor Mitsyanko | uint16_t data_count; /* current element in FIFO buffer */
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274 | d7dfca08 | Igor Mitsyanko | uint8_t stopped_state;/* Current SDHC state */
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275 | d7dfca08 | Igor Mitsyanko | /* Buffer Data Port Register - virtual access point to R and W buffers */
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276 | d7dfca08 | Igor Mitsyanko | /* Software Reset Register - always reads as 0 */
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277 | d7dfca08 | Igor Mitsyanko | /* Force Event Auto CMD12 Error Interrupt Reg - write only */
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278 | d7dfca08 | Igor Mitsyanko | /* Force Event Error Interrupt Register- write only */
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279 | d7dfca08 | Igor Mitsyanko | /* RO Host Controller Version Register always reads as 0x2401 */
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280 | d7dfca08 | Igor Mitsyanko | } SDHCIState; |
281 | d7dfca08 | Igor Mitsyanko | |
282 | d7dfca08 | Igor Mitsyanko | typedef struct SDHCIClass { |
283 | d7dfca08 | Igor Mitsyanko | SysBusDeviceClass busdev_class; |
284 | d7dfca08 | Igor Mitsyanko | |
285 | d7dfca08 | Igor Mitsyanko | void (*reset)(SDHCIState *s);
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286 | d7dfca08 | Igor Mitsyanko | uint32_t (*mem_read)(SDHCIState *s, unsigned int offset, unsigned size); |
287 | d7dfca08 | Igor Mitsyanko | void (*mem_write)(SDHCIState *s, unsigned int offset, uint32_t value, |
288 | d7dfca08 | Igor Mitsyanko | unsigned size);
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289 | d7dfca08 | Igor Mitsyanko | void (*send_command)(SDHCIState *s);
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290 | d7dfca08 | Igor Mitsyanko | bool (*can_issue_command)(SDHCIState *s);
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291 | d7dfca08 | Igor Mitsyanko | void (*data_transfer)(SDHCIState *s);
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292 | d7dfca08 | Igor Mitsyanko | void (*end_data_transfer)(SDHCIState *s);
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293 | d7dfca08 | Igor Mitsyanko | void (*do_sdma_single)(SDHCIState *s);
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294 | d7dfca08 | Igor Mitsyanko | void (*do_sdma_multi)(SDHCIState *s);
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295 | d7dfca08 | Igor Mitsyanko | void (*do_adma)(SDHCIState *s);
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296 | d7dfca08 | Igor Mitsyanko | void (*read_block_from_card)(SDHCIState *s);
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297 | d7dfca08 | Igor Mitsyanko | void (*write_block_to_card)(SDHCIState *s);
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298 | d7dfca08 | Igor Mitsyanko | uint32_t (*bdata_read)(SDHCIState *s, unsigned size);
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299 | d7dfca08 | Igor Mitsyanko | void (*bdata_write)(SDHCIState *s, uint32_t value, unsigned size); |
300 | d7dfca08 | Igor Mitsyanko | } SDHCIClass; |
301 | d7dfca08 | Igor Mitsyanko | |
302 | d7dfca08 | Igor Mitsyanko | extern const VMStateDescription sdhci_vmstate; |
303 | d7dfca08 | Igor Mitsyanko | |
304 | d7dfca08 | Igor Mitsyanko | #define TYPE_SDHCI "generic-sdhci" |
305 | d7dfca08 | Igor Mitsyanko | #define SDHCI(obj) \
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306 | d7dfca08 | Igor Mitsyanko | OBJECT_CHECK(SDHCIState, (obj), TYPE_SDHCI) |
307 | d7dfca08 | Igor Mitsyanko | #define SDHCI_CLASS(klass) \
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308 | d7dfca08 | Igor Mitsyanko | OBJECT_CLASS_CHECK(SDHCIClass, (klass), TYPE_SDHCI) |
309 | d7dfca08 | Igor Mitsyanko | #define SDHCI_GET_CLASS(obj) \
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310 | d7dfca08 | Igor Mitsyanko | OBJECT_GET_CLASS(SDHCIClass, (obj), TYPE_SDHCI) |
311 | d7dfca08 | Igor Mitsyanko | |
312 | d7dfca08 | Igor Mitsyanko | #endif /* SDHCI_H */ |