root / hw / alpha / pci.c @ 47b43a1f
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| 1 | 80bb2ff7 | Richard Henderson | /*
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| 2 | 80bb2ff7 | Richard Henderson | * QEMU Alpha PCI support functions.
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| 3 | 80bb2ff7 | Richard Henderson | *
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| 4 | 80bb2ff7 | Richard Henderson | * Some of this isn't very Alpha specific at all.
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| 5 | 80bb2ff7 | Richard Henderson | *
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| 6 | 80bb2ff7 | Richard Henderson | * ??? Sparse memory access not implemented.
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| 7 | 80bb2ff7 | Richard Henderson | */
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| 8 | 80bb2ff7 | Richard Henderson | |
| 9 | 80bb2ff7 | Richard Henderson | #include "config.h" |
| 10 | 47b43a1f | Paolo Bonzini | #include "alpha_sys.h" |
| 11 | 1de7afc9 | Paolo Bonzini | #include "qemu/log.h" |
| 12 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
| 13 | 80bb2ff7 | Richard Henderson | |
| 14 | 80bb2ff7 | Richard Henderson | |
| 15 | 80bb2ff7 | Richard Henderson | /* PCI IO reads/writes, to byte-word addressable memory. */
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| 16 | 80bb2ff7 | Richard Henderson | /* ??? Doesn't handle multiple PCI busses. */
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| 17 | 80bb2ff7 | Richard Henderson | |
| 18 | a8170e5e | Avi Kivity | static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size) |
| 19 | 80bb2ff7 | Richard Henderson | {
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| 20 | 80bb2ff7 | Richard Henderson | switch (size) {
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| 21 | 80bb2ff7 | Richard Henderson | case 1: |
| 22 | 80bb2ff7 | Richard Henderson | return cpu_inb(addr);
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| 23 | 80bb2ff7 | Richard Henderson | case 2: |
| 24 | 80bb2ff7 | Richard Henderson | return cpu_inw(addr);
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| 25 | 80bb2ff7 | Richard Henderson | case 4: |
| 26 | 80bb2ff7 | Richard Henderson | return cpu_inl(addr);
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| 27 | 80bb2ff7 | Richard Henderson | } |
| 28 | 80bb2ff7 | Richard Henderson | abort(); |
| 29 | 80bb2ff7 | Richard Henderson | } |
| 30 | 80bb2ff7 | Richard Henderson | |
| 31 | a8170e5e | Avi Kivity | static void bw_io_write(void *opaque, hwaddr addr, |
| 32 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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| 33 | 80bb2ff7 | Richard Henderson | {
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| 34 | 80bb2ff7 | Richard Henderson | switch (size) {
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| 35 | 80bb2ff7 | Richard Henderson | case 1: |
| 36 | 80bb2ff7 | Richard Henderson | cpu_outb(addr, val); |
| 37 | 80bb2ff7 | Richard Henderson | break;
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| 38 | 80bb2ff7 | Richard Henderson | case 2: |
| 39 | 80bb2ff7 | Richard Henderson | cpu_outw(addr, val); |
| 40 | 80bb2ff7 | Richard Henderson | break;
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| 41 | 80bb2ff7 | Richard Henderson | case 4: |
| 42 | 80bb2ff7 | Richard Henderson | cpu_outl(addr, val); |
| 43 | 80bb2ff7 | Richard Henderson | break;
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| 44 | 80bb2ff7 | Richard Henderson | default:
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| 45 | 80bb2ff7 | Richard Henderson | abort(); |
| 46 | 80bb2ff7 | Richard Henderson | } |
| 47 | 80bb2ff7 | Richard Henderson | } |
| 48 | 80bb2ff7 | Richard Henderson | |
| 49 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_bw_io_ops = {
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| 50 | 80bb2ff7 | Richard Henderson | .read = bw_io_read, |
| 51 | 80bb2ff7 | Richard Henderson | .write = bw_io_write, |
| 52 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
| 53 | 80bb2ff7 | Richard Henderson | .impl = {
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| 54 | 80bb2ff7 | Richard Henderson | .min_access_size = 1,
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| 55 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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| 56 | 80bb2ff7 | Richard Henderson | }, |
| 57 | 80bb2ff7 | Richard Henderson | }; |
| 58 | 80bb2ff7 | Richard Henderson | |
| 59 | 80bb2ff7 | Richard Henderson | /* PCI config space reads/writes, to byte-word addressable memory. */
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| 60 | a8170e5e | Avi Kivity | static uint64_t bw_conf1_read(void *opaque, hwaddr addr, |
| 61 | 80bb2ff7 | Richard Henderson | unsigned size)
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| 62 | 80bb2ff7 | Richard Henderson | {
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| 63 | 80bb2ff7 | Richard Henderson | PCIBus *b = opaque; |
| 64 | 80bb2ff7 | Richard Henderson | return pci_data_read(b, addr, size);
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| 65 | 80bb2ff7 | Richard Henderson | } |
| 66 | 80bb2ff7 | Richard Henderson | |
| 67 | a8170e5e | Avi Kivity | static void bw_conf1_write(void *opaque, hwaddr addr, |
| 68 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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| 69 | 80bb2ff7 | Richard Henderson | {
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| 70 | 80bb2ff7 | Richard Henderson | PCIBus *b = opaque; |
| 71 | 80bb2ff7 | Richard Henderson | pci_data_write(b, addr, val, size); |
| 72 | 80bb2ff7 | Richard Henderson | } |
| 73 | 80bb2ff7 | Richard Henderson | |
| 74 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_conf1_ops = {
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| 75 | 80bb2ff7 | Richard Henderson | .read = bw_conf1_read, |
| 76 | 80bb2ff7 | Richard Henderson | .write = bw_conf1_write, |
| 77 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
| 78 | 80bb2ff7 | Richard Henderson | .impl = {
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| 79 | 80bb2ff7 | Richard Henderson | .min_access_size = 1,
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| 80 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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| 81 | 80bb2ff7 | Richard Henderson | }, |
| 82 | 80bb2ff7 | Richard Henderson | }; |
| 83 | 80bb2ff7 | Richard Henderson | |
| 84 | 80bb2ff7 | Richard Henderson | /* PCI/EISA Interrupt Acknowledge Cycle. */
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| 85 | 80bb2ff7 | Richard Henderson | |
| 86 | a8170e5e | Avi Kivity | static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) |
| 87 | 80bb2ff7 | Richard Henderson | {
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| 88 | 80bb2ff7 | Richard Henderson | return pic_read_irq(isa_pic);
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| 89 | 80bb2ff7 | Richard Henderson | } |
| 90 | 80bb2ff7 | Richard Henderson | |
| 91 | a8170e5e | Avi Kivity | static void special_write(void *opaque, hwaddr addr, |
| 92 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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| 93 | 80bb2ff7 | Richard Henderson | {
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| 94 | 80bb2ff7 | Richard Henderson | qemu_log("pci: special write cycle");
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| 95 | 80bb2ff7 | Richard Henderson | } |
| 96 | 80bb2ff7 | Richard Henderson | |
| 97 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_iack_ops = {
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| 98 | 80bb2ff7 | Richard Henderson | .read = iack_read, |
| 99 | 80bb2ff7 | Richard Henderson | .write = special_write, |
| 100 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
| 101 | 80bb2ff7 | Richard Henderson | .valid = {
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| 102 | 80bb2ff7 | Richard Henderson | .min_access_size = 4,
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| 103 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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| 104 | 80bb2ff7 | Richard Henderson | }, |
| 105 | 80bb2ff7 | Richard Henderson | .impl = {
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| 106 | 80bb2ff7 | Richard Henderson | .min_access_size = 4,
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| 107 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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| 108 | 80bb2ff7 | Richard Henderson | }, |
| 109 | 80bb2ff7 | Richard Henderson | }; |