Archipelago » qemu

/* Alpha cores and system support chips.  */

#ifndef HW_ALPHA_H

#define HW_ALPHA_H 1

#include "hw/pci/pci.h"

#include "hw/pci/pci_host.h"

#include "hw/ide.h"

#include "hw/i386/pc.h"

#include "hw/irq.h"

PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4],

                     pci_map_irq_fn);

/* alpha_pci.c.  */

extern const MemoryRegionOps alpha_pci_bw_io_ops;

extern const MemoryRegionOps alpha_pci_conf1_ops;

extern const MemoryRegionOps alpha_pci_iack_ops;

#endif

#include "alpha_sys.h"

#include "alpha_sys.h"

#include "alpha_sys.h"

#include "strongarm.h"

#include "strongarm.h"

#ifndef _STRONGARM_H

#define _STRONGARM_H

#include "exec/memory.h"

#define SA_CS0          0x00000000

#define SA_CS1          0x08000000

#define SA_CS2          0x10000000

#define SA_CS3          0x18000000

#define SA_PCMCIA_CS0   0x20000000

#define SA_PCMCIA_CS1   0x30000000

#define SA_CS4          0x40000000

#define SA_CS5          0x48000000

/* system registers here */

#define SA_SDCS0        0xc0000000

#define SA_SDCS1        0xc8000000

#define SA_SDCS2        0xd0000000

#define SA_SDCS3        0xd8000000

enum {

    SA_PIC_GPIO0_EDGE = 0,

    SA_PIC_GPIO1_EDGE,

    SA_PIC_GPIO2_EDGE,

    SA_PIC_GPIO3_EDGE,

    SA_PIC_GPIO4_EDGE,

    SA_PIC_GPIO5_EDGE,

    SA_PIC_GPIO6_EDGE,

    SA_PIC_GPIO7_EDGE,

    SA_PIC_GPIO8_EDGE,

    SA_PIC_GPIO9_EDGE,

    SA_PIC_GPIO10_EDGE,

    SA_PIC_GPIOX_EDGE,

    SA_PIC_LCD,

    SA_PIC_UDC,

    SA_PIC_RSVD1,

    SA_PIC_UART1,

    SA_PIC_UART2,

    SA_PIC_UART3,

    SA_PIC_MCP,

    SA_PIC_SSP,

    SA_PIC_DMA_CH0,

    SA_PIC_DMA_CH1,

    SA_PIC_DMA_CH2,

    SA_PIC_DMA_CH3,

    SA_PIC_DMA_CH4,

    SA_PIC_DMA_CH5,

    SA_PIC_OSTC0,

    SA_PIC_OSTC1,

    SA_PIC_OSTC2,

    SA_PIC_OSTC3,

    SA_PIC_RTC_HZ,

    SA_PIC_RTC_ALARM,

};

typedef struct {

    ARMCPU *cpu;

    MemoryRegion sdram;

    DeviceState *pic;

    DeviceState *gpio;

    DeviceState *ppc;

    DeviceState *ssp;

    SSIBus *ssp_bus;

} StrongARMState;

StrongARMState *sa1110_init(MemoryRegion *sysmem,

                            unsigned int sdram_size, const char *rev);

#endif

#include "fmopl.h"

#include "fmopl.h"

#ifndef __FMOPL_H_

#define __FMOPL_H_

/* --- select emulation chips --- */

#define BUILD_YM3812 (HAS_YM3812)

//#define BUILD_YM3526 (HAS_YM3526)

//#define BUILD_Y8950  (HAS_Y8950)

/* --- system optimize --- */

/* select bit size of output : 8 or 16 */

#define OPL_OUTPUT_BIT 16

/* compiler dependence */

#ifndef OSD_CPU_H

#define OSD_CPU_H

typedef unsigned char	UINT8;   /* unsigned  8bit */

typedef unsigned short	UINT16;  /* unsigned 16bit */

typedef unsigned int	UINT32;  /* unsigned 32bit */

typedef signed char		INT8;    /* signed  8bit   */

typedef signed short	INT16;   /* signed 16bit   */

typedef signed int		INT32;   /* signed 32bit   */

#endif

#if (OPL_OUTPUT_BIT==16)

typedef INT16 OPLSAMPLE;

#endif

#if (OPL_OUTPUT_BIT==8)

typedef unsigned char  OPLSAMPLE;

#endif

#if BUILD_Y8950

#include "ymdeltat.h"

#endif

typedef void (*OPL_TIMERHANDLER)(int channel,double interval_Sec);

typedef void (*OPL_IRQHANDLER)(int param,int irq);

typedef void (*OPL_UPDATEHANDLER)(int param,int min_interval_us);

typedef void (*OPL_PORTHANDLER_W)(int param,unsigned char data);

typedef unsigned char (*OPL_PORTHANDLER_R)(int param);

/* !!!!! here is private section , do not access there member direct !!!!! */

#define OPL_TYPE_WAVESEL   0x01  /* waveform select    */

#define OPL_TYPE_ADPCM     0x02  /* DELTA-T ADPCM unit */

#define OPL_TYPE_KEYBOARD  0x04  /* keyboard interface */

#define OPL_TYPE_IO        0x08  /* I/O port */

/* Saving is necessary for member of the 'R' mark for suspend/resume */

/* ---------- OPL one of slot  ---------- */

typedef struct fm_opl_slot {

	INT32 TL;		/* total level     :TL << 8            */

	INT32 TLL;		/* adjusted now TL                     */

	UINT8  KSR;		/* key scale rate  :(shift down bit)   */

	INT32 *AR;		/* attack rate     :&AR_TABLE[AR<<2]   */

	INT32 *DR;		/* decay rate      :&DR_TALBE[DR<<2]   */

	INT32 SL;		/* sustin level    :SL_TALBE[SL]       */

	INT32 *RR;		/* release rate    :&DR_TABLE[RR<<2]   */

	UINT8 ksl;		/* keyscale level  :(shift down bits)  */

	UINT8 ksr;		/* key scale rate  :kcode>>KSR         */

	UINT32 mul;		/* multiple        :ML_TABLE[ML]       */

	UINT32 Cnt;		/* frequency count :                   */

	UINT32 Incr;	/* frequency step  :                   */

	/* envelope generator state */

	UINT8 eg_typ;	/* envelope type flag                  */

	UINT8 evm;		/* envelope phase                      */

	INT32 evc;		/* envelope counter                    */

	INT32 eve;		/* envelope counter end point          */

	INT32 evs;		/* envelope counter step               */

	INT32 evsa;	/* envelope step for AR :AR[ksr]           */

	INT32 evsd;	/* envelope step for DR :DR[ksr]           */

	INT32 evsr;	/* envelope step for RR :RR[ksr]           */

	/* LFO */

	UINT8 ams;		/* ams flag                            */

	UINT8 vib;		/* vibrate flag                        */

	/* wave selector */

	INT32 **wavetable;

}OPL_SLOT;

/* ---------- OPL one of channel  ---------- */

typedef struct fm_opl_channel {

	OPL_SLOT SLOT[2];

	UINT8 CON;			/* connection type                     */

	UINT8 FB;			/* feed back       :(shift down bit)   */

	INT32 *connect1;	/* slot1 output pointer                */

	INT32 *connect2;	/* slot2 output pointer                */

	INT32 op1_out[2];	/* slot1 output for selfeedback        */

	/* phase generator state */

	UINT32  block_fnum;	/* block+fnum      :                   */

	UINT8 kcode;		/* key code        : KeyScaleCode      */

	UINT32  fc;			/* Freq. Increment base                */

	UINT32  ksl_base;	/* KeyScaleLevel Base step             */

	UINT8 keyon;		/* key on/off flag                     */

} OPL_CH;

/* OPL state */

typedef struct fm_opl_f {

	UINT8 type;			/* chip type                         */

	int clock;			/* master clock  (Hz)                */

	int rate;			/* sampling rate (Hz)                */

	double freqbase;	/* frequency base                    */

	double TimerBase;	/* Timer base time (==sampling time) */

	UINT8 address;		/* address register                  */

	UINT8 status;		/* status flag                       */

	UINT8 statusmask;	/* status mask                       */

	UINT32 mode;		/* Reg.08 : CSM , notesel,etc.       */

	/* Timer */

	int T[2];			/* timer counter                     */

	UINT8 st[2];		/* timer enable                      */

	/* FM channel slots */

	OPL_CH *P_CH;		/* pointer of CH                     */

	int	max_ch;			/* maximum channel                   */

	/* Rhythm sention */

	UINT8 rhythm;		/* Rhythm mode , key flag */

#if BUILD_Y8950

	/* Delta-T ADPCM unit (Y8950) */

	YM_DELTAT *deltat;			/* DELTA-T ADPCM       */

#endif

	/* Keyboard / I/O interface unit (Y8950) */

	UINT8 portDirection;

	UINT8 portLatch;

	OPL_PORTHANDLER_R porthandler_r;

	OPL_PORTHANDLER_W porthandler_w;

	int port_param;

	OPL_PORTHANDLER_R keyboardhandler_r;

	OPL_PORTHANDLER_W keyboardhandler_w;

	int keyboard_param;

	/* time tables */

	INT32 AR_TABLE[75];	/* atttack rate tables */

	INT32 DR_TABLE[75];	/* decay rate tables   */

	UINT32 FN_TABLE[1024];  /* fnumber -> increment counter */

	/* LFO */

	INT32 *ams_table;

	INT32 *vib_table;

	INT32 amsCnt;

	INT32 amsIncr;

	INT32 vibCnt;

	INT32 vibIncr;

	/* wave selector enable flag */

	UINT8 wavesel;

	/* external event callback handler */

	OPL_TIMERHANDLER  TimerHandler;		/* TIMER handler   */

	int TimerParam;						/* TIMER parameter */

	OPL_IRQHANDLER    IRQHandler;		/* IRQ handler    */

	int IRQParam;						/* IRQ parameter  */

	OPL_UPDATEHANDLER UpdateHandler;	/* stream update handler   */

	int UpdateParam;					/* stream update parameter */

} FM_OPL;

/* ---------- Generic interface section ---------- */

#define OPL_TYPE_YM3526 (0)

#define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)

#define OPL_TYPE_Y8950  (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)

FM_OPL *OPLCreate(int type, int clock, int rate);

void OPLDestroy(FM_OPL *OPL);

void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset);

void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param);

void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param);

/* Y8950 port handlers */

void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param);

void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param);

void OPLResetChip(FM_OPL *OPL);

int OPLWrite(FM_OPL *OPL,int a,int v);

unsigned char OPLRead(FM_OPL *OPL,int a);

int OPLTimerOver(FM_OPL *OPL,int c);

/* YM3626/YM3812 local section */

void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);

void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);

#endif

#include "gusemu.h"

#include "gustate.h"

/*

 * GUSEMU32 - API

 *

 * Copyright (C) 2000-2007 Tibor "TS" Schütz

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#ifndef GUSEMU_H

#define GUSEMU_H

/* data types (need to be adjusted if neither a VC6 nor a C99 compatible compiler is used) */

#if defined _WIN32 && defined _MSC_VER /* doesn't support other win32 compilers yet, do it yourself... */

 typedef unsigned char GUSbyte;

 typedef unsigned short GUSword;

 typedef unsigned int GUSdword;

 typedef signed char GUSchar;

 typedef signed short GUSsample;

#else

 #include <stdint.h>

 typedef int8_t GUSchar;

 typedef uint8_t GUSbyte;

 typedef uint16_t GUSword;

 typedef uint32_t GUSdword;

 typedef int16_t GUSsample;

#endif

typedef struct _GUSEmuState

{

 GUSbyte *himemaddr; /* 1024*1024 bytes used for storing uploaded samples (+32 additional bytes for read padding) */

 GUSbyte *gusdatapos; /* (gusdataend-gusdata) bytes used for storing emulated GF1/mixer register states (32*32+4 bytes in initial GUSemu32 version) */

 uint32_t gusirq;

 uint32_t gusdma;

 unsigned int timer1fraction;

 unsigned int timer2fraction;

 void *opaque;

} GUSEmuState;

/* ** Callback functions needed: */

/* NMI is defined as hwirq=-1 (not supported (yet?)) */

/* GUS_irqrequest returns the number of IRQs actually scheduled into the virtual machine */

/* Level triggered IRQ simulations normally return 1 */

/* Event triggered IRQ simulation can safely ignore GUS_irqclear calls */

int  GUS_irqrequest(GUSEmuState *state, int hwirq, int num);/* needed in both mixer and bus emulation functions. */

void GUS_irqclear(  GUSEmuState *state, int hwirq); /* used by gus_write() only - can be left empty for mixer functions */

void GUS_dmarequest(GUSEmuState *state);            /* used by gus_write() only - can be left empty for mixer functions */

/* ** ISA bus interface functions: */

/* Port I/O handlers */

/* support the following ports: */

/* 2x0,2x6,2x8...2xF,3x0...3x7;  */

/* optional: 388,389 (at least writes should be forwarded or some GUS detection algorithms will fail) */

/* data is passed in host byte order */

unsigned int gus_read( GUSEmuState *state, int port, int size);

void         gus_write(GUSEmuState *state, int port, int size, unsigned int data);

/* size is given in bytes (1 for byte, 2 for word) */

/* DMA data transfer function */

/* data pointed to is passed in native x86 order */

void gus_dma_transferdata(GUSEmuState *state, char *dma_addr, unsigned int count, int TC);

/* Called back by GUS_start_DMA as soon as the emulated DMA controller is ready for a transfer to or from GUS */

/* (might be immediately if the DMA controller was programmed first) */

/* dma_addr is an already translated address directly pointing to the beginning of the memory block */

/* do not forget to update DMA states after the call, including the DREQ and TC flags */

/* it is possible to break down a single transfer into multiple ones, but take care that: */

/* -dma_count is actually count-1 */

/* -before and during a transfer, DREQ is set and TC cleared */

/* -when calling gus_dma_transferdata(), TC is only set true for call transferring the last byte */

/* -after the last transfer, DREQ is cleared and TC is set */

/* ** GF1 mixer emulation functions: */

/* Usually, gus_irqgen should be called directly after gus_mixvoices if you can meet the recommended ranges. */

/* If the interrupts are executed immediately (i.e., are synchronous), it may be useful to break this */

/* down into a sequence of gus_mixvoice();gus_irqgen(); calls while mixing an audio block. */

/* If the interrupts are asynchronous, it may be needed to use a separate thread mixing into a temporary */

/* audio buffer in order to avoid quality loss caused by large numsamples and elapsed_time values. */

void gus_mixvoices(GUSEmuState *state, unsigned int playback_freq, unsigned int numsamples, GUSsample *bufferpos);

/* recommended range: 10 < numsamples < 100 */

/* lower values may result in increased rounding error, higher values often cause audible timing delays */

void gus_irqgen(GUSEmuState *state, unsigned int elapsed_time);

/* recommended range: 80us < elapsed_time < max(1000us, numsamples/playback_freq) */

/* lower values won´t provide any benefit at all, higher values can cause audible timing delays */

/* note: masked timers are also calculated by this function, thus it might be needed even without any IRQs in use! */

#endif  /* gusemu.h */

#include "gustate.h"

#include "gusemu.h"

#include "gusemu.h"

#include "gustate.h"

/*

 * GUSEMU32 - persistent GUS register state

 *

 * Copyright (C) 2000-2007 Tibor "TS" Schütz

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#ifndef GUSTATE_H

#define GUSTATE_H

/*state block offset*/

#define gusdata (0)

/* data stored using this structure is in host byte order! */

/*access type*/

#define PortRead  (0)

#define PortWrite (1)

#define Port8Bitacc  (0)

#define Port16Bitacc (1)

/*voice register offsets (in bytes)*/

#define VSRegs (0)

#define VSRControl          (0)

#define VSRegsEnd (VSRControl+VSRegs + 32*(16*2))

#define VSRFreq             (2)

#define VSRLoopStartHi      (4)

#define VSRLoopStartLo      (6)

#define VSRLoopEndHi        (8)

#define VSRLoopEndLo       (10)

#define VSRVolRampRate     (12)

#define VSRVolRampStartVol (14)

#define VSRVolRampEndVol   (16)

#define VSRCurrVol         (18)

#define VSRCurrPosHi       (20)

#define VSRCurrPosLo       (22)

#define VSRPanning         (24)

#define VSRVolRampControl  (26)

/*voice register offsets (in words)*/

#define wVSRegs (0)

#define wVSRControl         (0)

#define wVSRegsEnd (wVSRControl+wVSRegs + 32*(16))

#define wVSRFreq            (1)

#define wVSRLoopStartHi     (2)

#define wVSRLoopStartLo     (3)

#define wVSRLoopEndHi       (4)

#define wVSRLoopEndLo       (5)

#define wVSRVolRampRate     (6)

#define wVSRVolRampStartVol (7)

#define wVSRVolRampEndVol   (8)

#define wVSRCurrVol         (9)

#define wVSRCurrPosHi      (10)

#define wVSRCurrPosLo      (11)

#define wVSRPanning        (12)

#define wVSRVolRampControl (13)

/*GUS register state block: 32 voices, padding filled with remaining registers*/

#define DataRegLoByte3x4  (VSRVolRampControl+2)

#define  DataRegWord3x4 (DataRegLoByte3x4)

#define DataRegHiByte3x5  (VSRVolRampControl+2       +1)

#define DMA_2xB (VSRVolRampControl+2+2)

#define IRQ_2xB (VSRVolRampControl+2+3)

#define RegCtrl_2xF       (VSRVolRampControl+2+(16*2))

#define Jumper_2xB        (VSRVolRampControl+2+(16*2)+1)

#define GUS42DMAStart     (VSRVolRampControl+2+(16*2)+2)

#define GUS43DRAMIOlo     (VSRVolRampControl+2+(16*2)*2)

#define  GUSDRAMPOS24bit (GUS43DRAMIOlo)

#define GUS44DRAMIOhi     (VSRVolRampControl+2+(16*2)*2+2)

#define voicewavetableirq (VSRVolRampControl+2+(16*2)*3) /* voice IRQ pseudoqueue: 1 bit per voice */

#define voicevolrampirq   (VSRVolRampControl+2+(16*2)*4) /* voice IRQ pseudoqueue: 1 bit per voice */

#define startvoices       (VSRVolRampControl+2+(16*2)*5) /* statistics / optimizations */

#define IRQStatReg2x6     (VSRVolRampControl+2+(16*2)*6)

#define TimerStatus2x8    (VSRVolRampControl+2+(16*2)*6+1)

#define TimerDataReg2x9   (VSRVolRampControl+2+(16*2)*6+2)

#define MixerCtrlReg2x0   (VSRVolRampControl+2+(16*2)*6+3)

#define VoiceSelReg3x2    (VSRVolRampControl+2+(16*2)*7)

#define FunkSelReg3x3     (VSRVolRampControl+2+(16*2)*7+1)

#define AdLibStatus2x8    (VSRVolRampControl+2+(16*2)*7+2)

#define StatRead_2xF      (VSRVolRampControl+2+(16*2)*7+3)

#define GUS48SampSpeed    (VSRVolRampControl+2+(16*2)*8)

#define GUS41DMACtrl      (VSRVolRampControl+2+(16*2)*8+1)

#define GUS45TimerCtrl    (VSRVolRampControl+2+(16*2)*8+2)

#define GUS46Counter1     (VSRVolRampControl+2+(16*2)*8+3)

#define GUS47Counter2     (VSRVolRampControl+2+(16*2)*9)

#define GUS49SampCtrl     (VSRVolRampControl+2+(16*2)*9+1)

#define GUS4cReset        (VSRVolRampControl+2+(16*2)*9+2)

#define NumVoices         (VSRVolRampControl+2+(16*2)*9+3)

#define TimerIRQs         (VSRVolRampControl+2+(16*2)*10)   /* delayed IRQ, statistics */

#define BusyTimerIRQs     (VSRVolRampControl+2+(16*2)*10+2) /* delayed IRQ, statistics */

#define AdLibCommand2xA   (VSRVolRampControl+2+(16*2)*11)

#define AdLibData2x9      (VSRVolRampControl+2+(16*2)*11+1)

#define SB2xCd            (VSRVolRampControl+2+(16*2)*11+2)

#define SB2xE             (VSRVolRampControl+2+(16*2)*11+3)

#define SynVoiceIRQ8f     (VSRVolRampControl+2+(16*2)*12)

#define GUS50DMAHigh      (VSRVolRampControl+2+(16*2)*12+1)

#define portaccesses (VSRegsEnd) /* statistics / suspend mode */

#define gusdataend (VSRegsEnd+4)

#endif  /* gustate.h */

#include "intel-hda.h"

#include "intel-hda-defs.h"

#ifndef HW_INTEL_HDA_DEFS_H

#define HW_INTEL_HDA_DEFS_H

/* qemu */

#define HDA_BUFFER_SIZE 256

/* --------------------------------------------------------------------- */

/* from linux/sound/pci/hda/hda_intel.c                                  */

/*

 * registers

 */

#define ICH6_REG_GCAP			0x00

#define   ICH6_GCAP_64OK	(1 << 0)   /* 64bit address support */

#define   ICH6_GCAP_NSDO	(3 << 1)   /* # of serial data out signals */

#define   ICH6_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */

#define   ICH6_GCAP_ISS		(15 << 8)  /* # of input streams */

#define   ICH6_GCAP_OSS		(15 << 12) /* # of output streams */

#define ICH6_REG_VMIN			0x02

#define ICH6_REG_VMAJ			0x03

#define ICH6_REG_OUTPAY			0x04

#define ICH6_REG_INPAY			0x06

#define ICH6_REG_GCTL			0x08

#define   ICH6_GCTL_RESET	(1 << 0)   /* controller reset */

#define   ICH6_GCTL_FCNTRL	(1 << 1)   /* flush control */

#define   ICH6_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */

#define ICH6_REG_WAKEEN			0x0c

#define ICH6_REG_STATESTS		0x0e

#define ICH6_REG_GSTS			0x10

#define   ICH6_GSTS_FSTS	(1 << 1)   /* flush status */

#define ICH6_REG_INTCTL			0x20

#define ICH6_REG_INTSTS			0x24

#define ICH6_REG_WALLCLK		0x30	/* 24Mhz source */

#define ICH6_REG_SYNC			0x34

#define ICH6_REG_CORBLBASE		0x40

#define ICH6_REG_CORBUBASE		0x44

#define ICH6_REG_CORBWP			0x48

#define ICH6_REG_CORBRP			0x4a

#define   ICH6_CORBRP_RST	(1 << 15)  /* read pointer reset */

#define ICH6_REG_CORBCTL		0x4c

#define   ICH6_CORBCTL_RUN	(1 << 1)   /* enable DMA */

#define   ICH6_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */

#define ICH6_REG_CORBSTS		0x4d

#define   ICH6_CORBSTS_CMEI	(1 << 0)   /* memory error indication */

#define ICH6_REG_CORBSIZE		0x4e

#define ICH6_REG_RIRBLBASE		0x50

#define ICH6_REG_RIRBUBASE		0x54

#define ICH6_REG_RIRBWP			0x58

#define   ICH6_RIRBWP_RST	(1 << 15)  /* write pointer reset */

#define ICH6_REG_RINTCNT		0x5a

#define ICH6_REG_RIRBCTL		0x5c

#define   ICH6_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */

#define   ICH6_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */

#define   ICH6_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */

#define ICH6_REG_RIRBSTS		0x5d

#define   ICH6_RBSTS_IRQ	(1 << 0)   /* response irq */

#define   ICH6_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */

#define ICH6_REG_RIRBSIZE		0x5e

#define ICH6_REG_IC			0x60

#define ICH6_REG_IR			0x64

#define ICH6_REG_IRS			0x68

#define   ICH6_IRS_VALID	(1<<1)

#define   ICH6_IRS_BUSY		(1<<0)

#define ICH6_REG_DPLBASE		0x70

#define ICH6_REG_DPUBASE		0x74

#define   ICH6_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */

enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */

#define ICH6_REG_SD_CTL			0x00

#define ICH6_REG_SD_STS			0x03

#define ICH6_REG_SD_LPIB		0x04

#define ICH6_REG_SD_CBL			0x08

#define ICH6_REG_SD_LVI			0x0c

#define ICH6_REG_SD_FIFOW		0x0e

#define ICH6_REG_SD_FIFOSIZE		0x10

#define ICH6_REG_SD_FORMAT		0x12

#define ICH6_REG_SD_BDLPL		0x18

#define ICH6_REG_SD_BDLPU		0x1c

/* PCI space */

#define ICH6_PCIREG_TCSEL	0x44

/*

 * other constants

 */

/* max number of SDs */

/* ICH, ATI and VIA have 4 playback and 4 capture */

#define ICH6_NUM_CAPTURE	4

#define ICH6_NUM_PLAYBACK	4

/* ULI has 6 playback and 5 capture */

#define ULI_NUM_CAPTURE		5

#define ULI_NUM_PLAYBACK	6

/* ATI HDMI has 1 playback and 0 capture */

#define ATIHDMI_NUM_CAPTURE	0

#define ATIHDMI_NUM_PLAYBACK	1

/* TERA has 4 playback and 3 capture */

#define TERA_NUM_CAPTURE	3

#define TERA_NUM_PLAYBACK	4

/* this number is statically defined for simplicity */

#define MAX_AZX_DEV		16

/* max number of fragments - we may use more if allocating more pages for BDL */

#define BDL_SIZE		4096

#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)

#define AZX_MAX_FRAG		32

/* max buffer size - no h/w limit, you can increase as you like */

#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */

#define RIRB_INT_RESPONSE	0x01

#define RIRB_INT_OVERRUN	0x04

#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */

#define AZX_MAX_CODECS		8

#define AZX_DEFAULT_CODECS	4

#define STATESTS_INT_MASK	((1 << AZX_MAX_CODECS) - 1)

/* SD_CTL bits */

#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */

#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */

#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */

#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */

#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */

#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)

#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */

#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */

#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */

#define SD_INT_COMPLETE		0x04	/* completion interrupt */

#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\

				 SD_INT_COMPLETE)

/* SD_STS */

#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */

#define ICH6_INT_ALL_STREAM	0xff	   /* all stream interrupts */

#define ICH6_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */

#define ICH6_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */

#define ICH6_MAX_CORB_ENTRIES	256

#define ICH6_MAX_RIRB_ENTRIES	256

/* position fix mode */

enum {

	POS_FIX_AUTO,

	POS_FIX_LPIB,

	POS_FIX_POSBUF,

};

/* Defines for ATI HD Audio support in SB450 south bridge */

#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42

#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

/* Defines for Nvidia HDA support */

#define NVIDIA_HDA_TRANSREG_ADDR      0x4e

#define NVIDIA_HDA_ENABLE_COHBITS     0x0f

#define NVIDIA_HDA_ISTRM_COH          0x4d

#define NVIDIA_HDA_OSTRM_COH          0x4c

#define NVIDIA_HDA_ENABLE_COHBIT      0x01

/* Defines for Intel SCH HDA snoop control */

#define INTEL_SCH_HDA_DEVC      0x78

#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

/* Define IN stream 0 FIFO size offset in VIA controller */

#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90

/* Define VIA HD Audio Device ID*/

#define VIA_HDAC_DEVICE_ID		0x3288

/* HD Audio class code */

#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403

/* --------------------------------------------------------------------- */

/* from linux/sound/pci/hda/hda_codec.h                                  */

/*

 * nodes

 */

#define	AC_NODE_ROOT		0x00

/*

 * function group types

 */

enum {

	AC_GRP_AUDIO_FUNCTION = 0x01,

	AC_GRP_MODEM_FUNCTION = 0x02,

};

/*

 * widget types

 */

enum {

	AC_WID_AUD_OUT,		/* Audio Out */

	AC_WID_AUD_IN,		/* Audio In */

	AC_WID_AUD_MIX,		/* Audio Mixer */

	AC_WID_AUD_SEL,		/* Audio Selector */

	AC_WID_PIN,		/* Pin Complex */

	AC_WID_POWER,		/* Power */

	AC_WID_VOL_KNB,		/* Volume Knob */

	AC_WID_BEEP,		/* Beep Generator */

	AC_WID_VENDOR = 0x0f	/* Vendor specific */

};

/*

 * GET verbs

 */

#define AC_VERB_GET_STREAM_FORMAT		0x0a00

#define AC_VERB_GET_AMP_GAIN_MUTE		0x0b00

#define AC_VERB_GET_PROC_COEF			0x0c00

#define AC_VERB_GET_COEF_INDEX			0x0d00

#define AC_VERB_PARAMETERS			0x0f00

#define AC_VERB_GET_CONNECT_SEL			0x0f01

#define AC_VERB_GET_CONNECT_LIST		0x0f02

#define AC_VERB_GET_PROC_STATE			0x0f03

#define AC_VERB_GET_SDI_SELECT			0x0f04

#define AC_VERB_GET_POWER_STATE			0x0f05

#define AC_VERB_GET_CONV			0x0f06

#define AC_VERB_GET_PIN_WIDGET_CONTROL		0x0f07

#define AC_VERB_GET_UNSOLICITED_RESPONSE	0x0f08

#define AC_VERB_GET_PIN_SENSE			0x0f09

#define AC_VERB_GET_BEEP_CONTROL		0x0f0a

#define AC_VERB_GET_EAPD_BTLENABLE		0x0f0c

#define AC_VERB_GET_DIGI_CONVERT_1		0x0f0d

#define AC_VERB_GET_DIGI_CONVERT_2		0x0f0e /* unused */

#define AC_VERB_GET_VOLUME_KNOB_CONTROL		0x0f0f

/* f10-f1a: GPIO */

#define AC_VERB_GET_GPIO_DATA			0x0f15

#define AC_VERB_GET_GPIO_MASK			0x0f16

#define AC_VERB_GET_GPIO_DIRECTION		0x0f17

#define AC_VERB_GET_GPIO_WAKE_MASK		0x0f18

#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK	0x0f19

#define AC_VERB_GET_GPIO_STICKY_MASK		0x0f1a

#define AC_VERB_GET_CONFIG_DEFAULT		0x0f1c

/* f20: AFG/MFG */

#define AC_VERB_GET_SUBSYSTEM_ID		0x0f20

#define AC_VERB_GET_CVT_CHAN_COUNT		0x0f2d

#define AC_VERB_GET_HDMI_DIP_SIZE		0x0f2e

#define AC_VERB_GET_HDMI_ELDD			0x0f2f

#define AC_VERB_GET_HDMI_DIP_INDEX		0x0f30

#define AC_VERB_GET_HDMI_DIP_DATA		0x0f31

#define AC_VERB_GET_HDMI_DIP_XMIT		0x0f32

#define AC_VERB_GET_HDMI_CP_CTRL		0x0f33

#define AC_VERB_GET_HDMI_CHAN_SLOT		0x0f34

/*

 * SET verbs

 */

#define AC_VERB_SET_STREAM_FORMAT		0x200

#define AC_VERB_SET_AMP_GAIN_MUTE		0x300

#define AC_VERB_SET_PROC_COEF			0x400

#define AC_VERB_SET_COEF_INDEX			0x500

#define AC_VERB_SET_CONNECT_SEL			0x701

#define AC_VERB_SET_PROC_STATE			0x703

#define AC_VERB_SET_SDI_SELECT			0x704

#define AC_VERB_SET_POWER_STATE			0x705

#define AC_VERB_SET_CHANNEL_STREAMID		0x706

#define AC_VERB_SET_PIN_WIDGET_CONTROL		0x707

#define AC_VERB_SET_UNSOLICITED_ENABLE		0x708

#define AC_VERB_SET_PIN_SENSE			0x709

#define AC_VERB_SET_BEEP_CONTROL		0x70a

#define AC_VERB_SET_EAPD_BTLENABLE		0x70c

#define AC_VERB_SET_DIGI_CONVERT_1		0x70d

#define AC_VERB_SET_DIGI_CONVERT_2		0x70e

#define AC_VERB_SET_VOLUME_KNOB_CONTROL		0x70f

#define AC_VERB_SET_GPIO_DATA			0x715

#define AC_VERB_SET_GPIO_MASK			0x716

#define AC_VERB_SET_GPIO_DIRECTION		0x717

#define AC_VERB_SET_GPIO_WAKE_MASK		0x718

#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK	0x719

#define AC_VERB_SET_GPIO_STICKY_MASK		0x71a

#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0	0x71c

#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1	0x71d

#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2	0x71e

#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3	0x71f

#define AC_VERB_SET_EAPD				0x788

#define AC_VERB_SET_CODEC_RESET			0x7ff

#define AC_VERB_SET_CVT_CHAN_COUNT		0x72d

#define AC_VERB_SET_HDMI_DIP_INDEX		0x730

#define AC_VERB_SET_HDMI_DIP_DATA		0x731

#define AC_VERB_SET_HDMI_DIP_XMIT		0x732

#define AC_VERB_SET_HDMI_CP_CTRL		0x733

#define AC_VERB_SET_HDMI_CHAN_SLOT		0x734

/*

 * Parameter IDs

 */

#define AC_PAR_VENDOR_ID		0x00

#define AC_PAR_SUBSYSTEM_ID		0x01

#define AC_PAR_REV_ID			0x02

#define AC_PAR_NODE_COUNT		0x04

#define AC_PAR_FUNCTION_TYPE		0x05

#define AC_PAR_AUDIO_FG_CAP		0x08

#define AC_PAR_AUDIO_WIDGET_CAP		0x09

#define AC_PAR_PCM			0x0a

#define AC_PAR_STREAM			0x0b

#define AC_PAR_PIN_CAP			0x0c

#define AC_PAR_AMP_IN_CAP		0x0d

#define AC_PAR_CONNLIST_LEN		0x0e

#define AC_PAR_POWER_STATE		0x0f

#define AC_PAR_PROC_CAP			0x10

#define AC_PAR_GPIO_CAP			0x11

#define AC_PAR_AMP_OUT_CAP		0x12

#define AC_PAR_VOL_KNB_CAP		0x13

#define AC_PAR_HDMI_LPCM_CAP		0x20

/*

 * AC_VERB_PARAMETERS results (32bit)

 */

/* Function Group Type */

#define AC_FGT_TYPE			(0xff<<0)

#define AC_FGT_TYPE_SHIFT		0

#define AC_FGT_UNSOL_CAP		(1<<8)

/* Audio Function Group Capabilities */

#define AC_AFG_OUT_DELAY		(0xf<<0)

#define AC_AFG_IN_DELAY			(0xf<<8)

#define AC_AFG_BEEP_GEN			(1<<16)

/* Audio Widget Capabilities */

#define AC_WCAP_STEREO			(1<<0)	/* stereo I/O */

#define AC_WCAP_IN_AMP			(1<<1)	/* AMP-in present */

#define AC_WCAP_OUT_AMP			(1<<2)	/* AMP-out present */

#define AC_WCAP_AMP_OVRD		(1<<3)	/* AMP-parameter override */

#define AC_WCAP_FORMAT_OVRD		(1<<4)	/* format override */

#define AC_WCAP_STRIPE			(1<<5)	/* stripe */

#define AC_WCAP_PROC_WID		(1<<6)	/* Proc Widget */

#define AC_WCAP_UNSOL_CAP		(1<<7)	/* Unsol capable */

#define AC_WCAP_CONN_LIST		(1<<8)	/* connection list */

#define AC_WCAP_DIGITAL			(1<<9)	/* digital I/O */

#define AC_WCAP_POWER			(1<<10)	/* power control */

#define AC_WCAP_LR_SWAP			(1<<11)	/* L/R swap */

#define AC_WCAP_CP_CAPS			(1<<12) /* content protection */

#define AC_WCAP_CHAN_CNT_EXT		(7<<13)	/* channel count ext */

#define AC_WCAP_DELAY			(0xf<<16)

#define AC_WCAP_DELAY_SHIFT		16

#define AC_WCAP_TYPE			(0xf<<20)

#define AC_WCAP_TYPE_SHIFT		20

/* supported PCM rates and bits */

#define AC_SUPPCM_RATES			(0xfff << 0)

#define AC_SUPPCM_BITS_8		(1<<16)

#define AC_SUPPCM_BITS_16		(1<<17)

#define AC_SUPPCM_BITS_20		(1<<18)

#define AC_SUPPCM_BITS_24		(1<<19)

#define AC_SUPPCM_BITS_32		(1<<20)

/* supported PCM stream format */

#define AC_SUPFMT_PCM			(1<<0)

#define AC_SUPFMT_FLOAT32		(1<<1)

#define AC_SUPFMT_AC3			(1<<2)

/* GP I/O count */

#define AC_GPIO_IO_COUNT		(0xff<<0)

#define AC_GPIO_O_COUNT			(0xff<<8)

#define AC_GPIO_O_COUNT_SHIFT		8

#define AC_GPIO_I_COUNT			(0xff<<16)

#define AC_GPIO_I_COUNT_SHIFT		16

#define AC_GPIO_UNSOLICITED		(1<<30)

#define AC_GPIO_WAKE			(1<<31)

/* Converter stream, channel */

#define AC_CONV_CHANNEL			(0xf<<0)

#define AC_CONV_STREAM			(0xf<<4)

#define AC_CONV_STREAM_SHIFT		4

/* Input converter SDI select */

#define AC_SDI_SELECT			(0xf<<0)

/* stream format id */

#define AC_FMT_CHAN_SHIFT		0

#define AC_FMT_CHAN_MASK		(0x0f << 0)

#define AC_FMT_BITS_SHIFT		4

#define AC_FMT_BITS_MASK		(7 << 4)

#define AC_FMT_BITS_8			(0 << 4)

#define AC_FMT_BITS_16			(1 << 4)

#define AC_FMT_BITS_20			(2 << 4)

#define AC_FMT_BITS_24			(3 << 4)

#define AC_FMT_BITS_32			(4 << 4)

#define AC_FMT_DIV_SHIFT		8

#define AC_FMT_DIV_MASK			(7 << 8)

#define AC_FMT_MULT_SHIFT		11

#define AC_FMT_MULT_MASK		(7 << 11)

#define AC_FMT_BASE_SHIFT		14

#define AC_FMT_BASE_48K			(0 << 14)

#define AC_FMT_BASE_44K			(1 << 14)

#define AC_FMT_TYPE_SHIFT		15

#define AC_FMT_TYPE_PCM			(0 << 15)

#define AC_FMT_TYPE_NON_PCM		(1 << 15)

/* Unsolicited response control */

#define AC_UNSOL_TAG			(0x3f<<0)

#define AC_UNSOL_ENABLED		(1<<7)

#define AC_USRSP_EN			AC_UNSOL_ENABLED

/* Unsolicited responses */

#define AC_UNSOL_RES_TAG		(0x3f<<26)

#define AC_UNSOL_RES_TAG_SHIFT		26

#define AC_UNSOL_RES_SUBTAG		(0x1f<<21)

#define AC_UNSOL_RES_SUBTAG_SHIFT	21

#define AC_UNSOL_RES_ELDV		(1<<1)	/* ELD Data valid (for HDMI) */

#define AC_UNSOL_RES_PD			(1<<0)	/* pinsense detect */

#define AC_UNSOL_RES_CP_STATE		(1<<1)	/* content protection */

#define AC_UNSOL_RES_CP_READY		(1<<0)	/* content protection */

/* Pin widget capabilies */

#define AC_PINCAP_IMP_SENSE		(1<<0)	/* impedance sense capable */

#define AC_PINCAP_TRIG_REQ		(1<<1)	/* trigger required */

#define AC_PINCAP_PRES_DETECT		(1<<2)	/* presence detect capable */

#define AC_PINCAP_HP_DRV		(1<<3)	/* headphone drive capable */

#define AC_PINCAP_OUT			(1<<4)	/* output capable */

#define AC_PINCAP_IN			(1<<5)	/* input capable */

#define AC_PINCAP_BALANCE		(1<<6)	/* balanced I/O capable */

/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,

 *       but is marked reserved in the Intel HDA specification.

 */

#define AC_PINCAP_LR_SWAP		(1<<7)	/* L/R swap */

/* Note: The same bit as LR_SWAP is newly defined as HDMI capability

 *       in HD-audio specification

 */

#define AC_PINCAP_HDMI			(1<<7)	/* HDMI pin */

#define AC_PINCAP_DP			(1<<24)	/* DisplayPort pin, can

						 * coexist with AC_PINCAP_HDMI

						 */

#define AC_PINCAP_VREF			(0x37<<8)

#define AC_PINCAP_VREF_SHIFT		8

#define AC_PINCAP_EAPD			(1<<16)	/* EAPD capable */

#define AC_PINCAP_HBR			(1<<27)	/* High Bit Rate */

/* Vref status (used in pin cap) */

#define AC_PINCAP_VREF_HIZ		(1<<0)	/* Hi-Z */

#define AC_PINCAP_VREF_50		(1<<1)	/* 50% */

#define AC_PINCAP_VREF_GRD		(1<<2)	/* ground */

#define AC_PINCAP_VREF_80		(1<<4)	/* 80% */

#define AC_PINCAP_VREF_100		(1<<5)	/* 100% */

/* Amplifier capabilities */

#define AC_AMPCAP_OFFSET		(0x7f<<0)  /* 0dB offset */

#define AC_AMPCAP_OFFSET_SHIFT		0

#define AC_AMPCAP_NUM_STEPS		(0x7f<<8)  /* number of steps */

#define AC_AMPCAP_NUM_STEPS_SHIFT	8

#define AC_AMPCAP_STEP_SIZE		(0x7f<<16) /* step size 0-32dB

						    * in 0.25dB

						    */

#define AC_AMPCAP_STEP_SIZE_SHIFT	16

#define AC_AMPCAP_MUTE			(1<<31)    /* mute capable */

#define AC_AMPCAP_MUTE_SHIFT		31

/* Connection list */

#define AC_CLIST_LENGTH			(0x7f<<0)

#define AC_CLIST_LONG			(1<<7)

/* Supported power status */

#define AC_PWRST_D0SUP			(1<<0)

#define AC_PWRST_D1SUP			(1<<1)

#define AC_PWRST_D2SUP			(1<<2)

#define AC_PWRST_D3SUP			(1<<3)

#define AC_PWRST_D3COLDSUP		(1<<4)

#define AC_PWRST_S3D3COLDSUP		(1<<29)

#define AC_PWRST_CLKSTOP		(1<<30)

#define AC_PWRST_EPSS			(1U<<31)

/* Power state values */

#define AC_PWRST_SETTING		(0xf<<0)

#define AC_PWRST_ACTUAL			(0xf<<4)

#define AC_PWRST_ACTUAL_SHIFT		4

#define AC_PWRST_D0			0x00

#define AC_PWRST_D1			0x01

#define AC_PWRST_D2			0x02

#define AC_PWRST_D3			0x03

/* Processing capabilies */

#define AC_PCAP_BENIGN			(1<<0)

#define AC_PCAP_NUM_COEF		(0xff<<8)

#define AC_PCAP_NUM_COEF_SHIFT		8

/* Volume knobs capabilities */

#define AC_KNBCAP_NUM_STEPS		(0x7f<<0)

#define AC_KNBCAP_DELTA			(1<<7)

/* HDMI LPCM capabilities */

#define AC_LPCMCAP_48K_CP_CHNS		(0x0f<<0) /* max channels w/ CP-on */	

#define AC_LPCMCAP_48K_NO_CHNS		(0x0f<<4) /* max channels w/o CP-on */

#define AC_LPCMCAP_48K_20BIT		(1<<8)	/* 20b bitrate supported */

#define AC_LPCMCAP_48K_24BIT		(1<<9)	/* 24b bitrate supported */

#define AC_LPCMCAP_96K_CP_CHNS		(0x0f<<10) /* max channels w/ CP-on */	

#define AC_LPCMCAP_96K_NO_CHNS		(0x0f<<14) /* max channels w/o CP-on */

#define AC_LPCMCAP_96K_20BIT		(1<<18)	/* 20b bitrate supported */

#define AC_LPCMCAP_96K_24BIT		(1<<19)	/* 24b bitrate supported */

#define AC_LPCMCAP_192K_CP_CHNS		(0x0f<<20) /* max channels w/ CP-on */	

#define AC_LPCMCAP_192K_NO_CHNS		(0x0f<<24) /* max channels w/o CP-on */

#define AC_LPCMCAP_192K_20BIT		(1<<28)	/* 20b bitrate supported */

#define AC_LPCMCAP_192K_24BIT		(1<<29)	/* 24b bitrate supported */

#define AC_LPCMCAP_44K			(1<<30)	/* 44.1kHz support */

#define AC_LPCMCAP_44K_MS		(1<<31)	/* 44.1kHz-multiplies support */

/*

 * Control Parameters

 */

/* Amp gain/mute */

#define AC_AMP_MUTE			(1<<7)

#define AC_AMP_GAIN			(0x7f)

#define AC_AMP_GET_INDEX		(0xf<<0)

#define AC_AMP_GET_LEFT			(1<<13)

#define AC_AMP_GET_RIGHT		(0<<13)

#define AC_AMP_GET_OUTPUT		(1<<15)

#define AC_AMP_GET_INPUT		(0<<15)

#define AC_AMP_SET_INDEX		(0xf<<8)

#define AC_AMP_SET_INDEX_SHIFT		8

#define AC_AMP_SET_RIGHT		(1<<12)

#define AC_AMP_SET_LEFT			(1<<13)

#define AC_AMP_SET_INPUT		(1<<14)

#define AC_AMP_SET_OUTPUT		(1<<15)

/* DIGITAL1 bits */

#define AC_DIG1_ENABLE			(1<<0)

#define AC_DIG1_V			(1<<1)

#define AC_DIG1_VCFG			(1<<2)

#define AC_DIG1_EMPHASIS		(1<<3)

#define AC_DIG1_COPYRIGHT		(1<<4)

#define AC_DIG1_NONAUDIO		(1<<5)

#define AC_DIG1_PROFESSIONAL		(1<<6)

#define AC_DIG1_LEVEL			(1<<7)

/* DIGITAL2 bits */

#define AC_DIG2_CC			(0x7f<<0)

/* Pin widget control - 8bit */

#define AC_PINCTL_EPT			(0x3<<0)

#define AC_PINCTL_EPT_NATIVE		0

#define AC_PINCTL_EPT_HBR		3

#define AC_PINCTL_VREFEN		(0x7<<0)

#define AC_PINCTL_VREF_HIZ		0	/* Hi-Z */

#define AC_PINCTL_VREF_50		1	/* 50% */

#define AC_PINCTL_VREF_GRD		2	/* ground */

#define AC_PINCTL_VREF_80		4	/* 80% */

#define AC_PINCTL_VREF_100		5	/* 100% */

#define AC_PINCTL_IN_EN			(1<<5)

#define AC_PINCTL_OUT_EN		(1<<6)

#define AC_PINCTL_HP_EN			(1<<7)

/* Pin sense - 32bit */

#define AC_PINSENSE_IMPEDANCE_MASK	(0x7fffffff)

#define AC_PINSENSE_PRESENCE		(1<<31)

#define AC_PINSENSE_ELDV		(1<<30)	/* ELD valid (HDMI) */

/* EAPD/BTL enable - 32bit */

#define AC_EAPDBTL_BALANCED		(1<<0)

#define AC_EAPDBTL_EAPD			(1<<1)

#define AC_EAPDBTL_LR_SWAP		(1<<2)

/* HDMI ELD data */

#define AC_ELDD_ELD_VALID		(1<<31)

#define AC_ELDD_ELD_DATA		0xff

/* HDMI DIP size */

#define AC_DIPSIZE_ELD_BUF		(1<<3) /* ELD buf size of packet size */

#define AC_DIPSIZE_PACK_IDX		(0x07<<0) /* packet index */

/* HDMI DIP index */

#define AC_DIPIDX_PACK_IDX		(0x07<<5) /* packet idnex */

#define AC_DIPIDX_BYTE_IDX		(0x1f<<0) /* byte index */

/* HDMI DIP xmit (transmit) control */

#define AC_DIPXMIT_MASK			(0x3<<6)

#define AC_DIPXMIT_DISABLE		(0x0<<6) /* disable xmit */

#define AC_DIPXMIT_ONCE			(0x2<<6) /* xmit once then disable */

#define AC_DIPXMIT_BEST			(0x3<<6) /* best effort */

/* HDMI content protection (CP) control */

#define AC_CPCTRL_CES			(1<<9) /* current encryption state */

#define AC_CPCTRL_READY			(1<<8) /* ready bit */

#define AC_CPCTRL_SUBTAG		(0x1f<<3) /* subtag for unsol-resp */

#define AC_CPCTRL_STATE			(3<<0) /* current CP request state */

/* Converter channel <-> HDMI slot mapping */

#define AC_CVTMAP_HDMI_SLOT		(0xf<<0) /* HDMI slot number */

#define AC_CVTMAP_CHAN			(0xf<<4) /* converter channel number */

/* configuration default - 32bit */

#define AC_DEFCFG_SEQUENCE		(0xf<<0)

#define AC_DEFCFG_DEF_ASSOC		(0xf<<4)

#define AC_DEFCFG_ASSOC_SHIFT		4

#define AC_DEFCFG_MISC			(0xf<<8)

#define AC_DEFCFG_MISC_SHIFT		8

#define AC_DEFCFG_MISC_NO_PRESENCE	(1<<0)

#define AC_DEFCFG_COLOR			(0xf<<12)

#define AC_DEFCFG_COLOR_SHIFT		12

#define AC_DEFCFG_CONN_TYPE		(0xf<<16)

#define AC_DEFCFG_CONN_TYPE_SHIFT	16

#define AC_DEFCFG_DEVICE		(0xf<<20)

#define AC_DEFCFG_DEVICE_SHIFT		20

#define AC_DEFCFG_LOCATION		(0x3f<<24)

#define AC_DEFCFG_LOCATION_SHIFT	24

#define AC_DEFCFG_PORT_CONN		(0x3<<30)

#define AC_DEFCFG_PORT_CONN_SHIFT	30

/* device device types (0x0-0xf) */

enum {

	AC_JACK_LINE_OUT,

	AC_JACK_SPEAKER,

	AC_JACK_HP_OUT,

	AC_JACK_CD,

	AC_JACK_SPDIF_OUT,

	AC_JACK_DIG_OTHER_OUT,

	AC_JACK_MODEM_LINE_SIDE,

	AC_JACK_MODEM_HAND_SIDE,

	AC_JACK_LINE_IN,

	AC_JACK_AUX,

	AC_JACK_MIC_IN,

	AC_JACK_TELEPHONY,

	AC_JACK_SPDIF_IN,

	AC_JACK_DIG_OTHER_IN,

	AC_JACK_OTHER = 0xf,

};