root / hw / sh_intc.c @ 47ce9ef7
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1 | 80f515e6 | balrog | /*
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2 | 80f515e6 | balrog | * SuperH interrupt controller module
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3 | 80f515e6 | balrog | *
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4 | 80f515e6 | balrog | * Copyright (c) 2007 Magnus Damm
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5 | 80f515e6 | balrog | * Based on sh_timer.c and arm_timer.c by Paul Brook
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6 | 80f515e6 | balrog | * Copyright (c) 2005-2006 CodeSourcery.
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7 | 80f515e6 | balrog | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | 80f515e6 | balrog | */
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10 | 80f515e6 | balrog | |
11 | 80f515e6 | balrog | #include "sh_intc.h" |
12 | 87ecb68b | pbrook | #include "hw.h" |
13 | 87ecb68b | pbrook | #include "sh.h" |
14 | 80f515e6 | balrog | |
15 | 80f515e6 | balrog | //#define DEBUG_INTC
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16 | e96e2044 | ths | //#define DEBUG_INTC_SOURCES
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17 | 80f515e6 | balrog | |
18 | 80f515e6 | balrog | #define INTC_A7(x) ((x) & 0x1fffffff) |
19 | 80f515e6 | balrog | |
20 | e96e2044 | ths | void sh_intc_toggle_source(struct intc_source *source, |
21 | e96e2044 | ths | int enable_adj, int assert_adj) |
22 | e96e2044 | ths | { |
23 | e96e2044 | ths | int enable_changed = 0; |
24 | e96e2044 | ths | int pending_changed = 0; |
25 | e96e2044 | ths | int old_pending;
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26 | e96e2044 | ths | |
27 | e96e2044 | ths | if ((source->enable_count == source->enable_max) && (enable_adj == -1)) |
28 | e96e2044 | ths | enable_changed = -1;
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29 | e96e2044 | ths | |
30 | e96e2044 | ths | source->enable_count += enable_adj; |
31 | e96e2044 | ths | |
32 | e96e2044 | ths | if (source->enable_count == source->enable_max)
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33 | e96e2044 | ths | enable_changed = 1;
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34 | e96e2044 | ths | |
35 | e96e2044 | ths | source->asserted += assert_adj; |
36 | e96e2044 | ths | |
37 | e96e2044 | ths | old_pending = source->pending; |
38 | e96e2044 | ths | source->pending = source->asserted && |
39 | e96e2044 | ths | (source->enable_count == source->enable_max); |
40 | e96e2044 | ths | |
41 | e96e2044 | ths | if (old_pending != source->pending)
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42 | e96e2044 | ths | pending_changed = 1;
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43 | e96e2044 | ths | |
44 | e96e2044 | ths | if (pending_changed) {
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45 | e96e2044 | ths | if (source->pending) {
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46 | e96e2044 | ths | source->parent->pending++; |
47 | e96e2044 | ths | if (source->parent->pending == 1) |
48 | e96e2044 | ths | cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
49 | e96e2044 | ths | } |
50 | e96e2044 | ths | else {
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51 | e96e2044 | ths | source->parent->pending--; |
52 | e96e2044 | ths | if (source->parent->pending == 0) |
53 | e96e2044 | ths | cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
54 | e96e2044 | ths | } |
55 | e96e2044 | ths | } |
56 | e96e2044 | ths | |
57 | e96e2044 | ths | if (enable_changed || assert_adj || pending_changed) {
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58 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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59 | e96e2044 | ths | printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
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60 | e96e2044 | ths | source->parent->pending, |
61 | e96e2044 | ths | source->asserted, |
62 | e96e2044 | ths | source->enable_count, |
63 | e96e2044 | ths | source->enable_max, |
64 | e96e2044 | ths | source->vect, |
65 | e96e2044 | ths | source->asserted ? "asserted " :
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66 | e96e2044 | ths | assert_adj ? "deasserted" : "", |
67 | e96e2044 | ths | enable_changed == 1 ? "enabled " : |
68 | e96e2044 | ths | enable_changed == -1 ? "disabled " : "", |
69 | e96e2044 | ths | source->pending ? "pending" : ""); |
70 | e96e2044 | ths | #endif
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71 | e96e2044 | ths | } |
72 | e96e2044 | ths | } |
73 | e96e2044 | ths | |
74 | b79e1752 | aurel32 | static void sh_intc_set_irq (void *opaque, int n, int level) |
75 | 96e2fc41 | aurel32 | { |
76 | 96e2fc41 | aurel32 | struct intc_desc *desc = opaque;
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77 | 96e2fc41 | aurel32 | struct intc_source *source = &(desc->sources[n]);
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78 | 96e2fc41 | aurel32 | |
79 | 4e7ed2d1 | aurel32 | if (level && !source->asserted)
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80 | 4e7ed2d1 | aurel32 | sh_intc_toggle_source(source, 0, 1); |
81 | 4e7ed2d1 | aurel32 | else if (!level && source->asserted) |
82 | 4e7ed2d1 | aurel32 | sh_intc_toggle_source(source, 0, -1); |
83 | 96e2fc41 | aurel32 | } |
84 | 96e2fc41 | aurel32 | |
85 | e96e2044 | ths | int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) |
86 | e96e2044 | ths | { |
87 | e96e2044 | ths | unsigned int i; |
88 | e96e2044 | ths | |
89 | e96e2044 | ths | /* slow: use a linked lists of pending sources instead */
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90 | e96e2044 | ths | /* wrong: take interrupt priority into account (one list per priority) */
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91 | e96e2044 | ths | |
92 | e96e2044 | ths | if (imask == 0x0f) { |
93 | e96e2044 | ths | return -1; /* FIXME, update code to include priority per source */ |
94 | e96e2044 | ths | } |
95 | e96e2044 | ths | |
96 | e96e2044 | ths | for (i = 0; i < desc->nr_sources; i++) { |
97 | e96e2044 | ths | struct intc_source *source = desc->sources + i;
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98 | e96e2044 | ths | |
99 | e96e2044 | ths | if (source->pending) {
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100 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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101 | e96e2044 | ths | printf("sh_intc: (%d) returning interrupt source 0x%x\n",
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102 | e96e2044 | ths | desc->pending, source->vect); |
103 | e96e2044 | ths | #endif
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104 | e96e2044 | ths | return source->vect;
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105 | e96e2044 | ths | } |
106 | e96e2044 | ths | } |
107 | e96e2044 | ths | |
108 | 43dc2a64 | Blue Swirl | abort(); |
109 | e96e2044 | ths | } |
110 | e96e2044 | ths | |
111 | 80f515e6 | balrog | #define INTC_MODE_NONE 0 |
112 | 80f515e6 | balrog | #define INTC_MODE_DUAL_SET 1 |
113 | 80f515e6 | balrog | #define INTC_MODE_DUAL_CLR 2 |
114 | 80f515e6 | balrog | #define INTC_MODE_ENABLE_REG 3 |
115 | 80f515e6 | balrog | #define INTC_MODE_MASK_REG 4 |
116 | 80f515e6 | balrog | #define INTC_MODE_IS_PRIO 8 |
117 | 80f515e6 | balrog | |
118 | 80f515e6 | balrog | static unsigned int sh_intc_mode(unsigned long address, |
119 | 80f515e6 | balrog | unsigned long set_reg, unsigned long clr_reg) |
120 | 80f515e6 | balrog | { |
121 | 80f515e6 | balrog | if ((address != INTC_A7(set_reg)) &&
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122 | 80f515e6 | balrog | (address != INTC_A7(clr_reg))) |
123 | 80f515e6 | balrog | return INTC_MODE_NONE;
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124 | 80f515e6 | balrog | |
125 | 80f515e6 | balrog | if (set_reg && clr_reg) {
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126 | 80f515e6 | balrog | if (address == INTC_A7(set_reg))
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127 | 80f515e6 | balrog | return INTC_MODE_DUAL_SET;
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128 | 80f515e6 | balrog | else
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129 | 80f515e6 | balrog | return INTC_MODE_DUAL_CLR;
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130 | 80f515e6 | balrog | } |
131 | 80f515e6 | balrog | |
132 | 80f515e6 | balrog | if (set_reg)
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133 | 80f515e6 | balrog | return INTC_MODE_ENABLE_REG;
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134 | 80f515e6 | balrog | else
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135 | 80f515e6 | balrog | return INTC_MODE_MASK_REG;
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136 | 80f515e6 | balrog | } |
137 | 80f515e6 | balrog | |
138 | 80f515e6 | balrog | static void sh_intc_locate(struct intc_desc *desc, |
139 | 80f515e6 | balrog | unsigned long address, |
140 | 80f515e6 | balrog | unsigned long **datap, |
141 | 80f515e6 | balrog | intc_enum **enums, |
142 | 80f515e6 | balrog | unsigned int *first, |
143 | 80f515e6 | balrog | unsigned int *width, |
144 | 80f515e6 | balrog | unsigned int *modep) |
145 | 80f515e6 | balrog | { |
146 | 80f515e6 | balrog | unsigned int i, mode; |
147 | 80f515e6 | balrog | |
148 | 80f515e6 | balrog | /* this is slow but works for now */
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149 | 80f515e6 | balrog | |
150 | 80f515e6 | balrog | if (desc->mask_regs) {
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151 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
152 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
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153 | 80f515e6 | balrog | |
154 | 80f515e6 | balrog | mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); |
155 | 80f515e6 | balrog | if (mode == INTC_MODE_NONE)
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156 | 80f515e6 | balrog | continue;
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157 | 80f515e6 | balrog | |
158 | 80f515e6 | balrog | *modep = mode; |
159 | 80f515e6 | balrog | *datap = &mr->value; |
160 | 80f515e6 | balrog | *enums = mr->enum_ids; |
161 | 80f515e6 | balrog | *first = mr->reg_width - 1;
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162 | 80f515e6 | balrog | *width = 1;
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163 | 80f515e6 | balrog | return;
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164 | 80f515e6 | balrog | } |
165 | 80f515e6 | balrog | } |
166 | 80f515e6 | balrog | |
167 | 80f515e6 | balrog | if (desc->prio_regs) {
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168 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
169 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
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170 | 80f515e6 | balrog | |
171 | 80f515e6 | balrog | mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); |
172 | 80f515e6 | balrog | if (mode == INTC_MODE_NONE)
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173 | 80f515e6 | balrog | continue;
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174 | 80f515e6 | balrog | |
175 | 80f515e6 | balrog | *modep = mode | INTC_MODE_IS_PRIO; |
176 | 80f515e6 | balrog | *datap = &pr->value; |
177 | 80f515e6 | balrog | *enums = pr->enum_ids; |
178 | 80f515e6 | balrog | *first = (pr->reg_width / pr->field_width) - 1;
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179 | 80f515e6 | balrog | *width = pr->field_width; |
180 | 80f515e6 | balrog | return;
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181 | 80f515e6 | balrog | } |
182 | 80f515e6 | balrog | } |
183 | 80f515e6 | balrog | |
184 | 43dc2a64 | Blue Swirl | abort(); |
185 | 80f515e6 | balrog | } |
186 | 80f515e6 | balrog | |
187 | e96e2044 | ths | static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, |
188 | e96e2044 | ths | int enable, int is_group) |
189 | 80f515e6 | balrog | { |
190 | 80f515e6 | balrog | struct intc_source *source = desc->sources + id;
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191 | 80f515e6 | balrog | |
192 | 80f515e6 | balrog | if (!id)
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193 | 80f515e6 | balrog | return;
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194 | 80f515e6 | balrog | |
195 | 80f515e6 | balrog | if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
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196 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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197 | 80f515e6 | balrog | printf("sh_intc: reserved interrupt source %d modified\n", id);
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198 | 80f515e6 | balrog | #endif
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199 | 80f515e6 | balrog | return;
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200 | 80f515e6 | balrog | } |
201 | 80f515e6 | balrog | |
202 | e96e2044 | ths | if (source->vect)
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203 | e96e2044 | ths | sh_intc_toggle_source(source, enable ? 1 : -1, 0); |
204 | 80f515e6 | balrog | |
205 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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206 | 80f515e6 | balrog | else {
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207 | 80f515e6 | balrog | printf("setting interrupt group %d to %d\n", id, !!enable);
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208 | 80f515e6 | balrog | } |
209 | 80f515e6 | balrog | #endif
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210 | 80f515e6 | balrog | |
211 | 80f515e6 | balrog | if ((is_group || !source->vect) && source->next_enum_id) {
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212 | e96e2044 | ths | sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
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213 | 80f515e6 | balrog | } |
214 | 80f515e6 | balrog | |
215 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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216 | 80f515e6 | balrog | if (!source->vect) {
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217 | 80f515e6 | balrog | printf("setting interrupt group %d to %d - done\n", id, !!enable);
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218 | 80f515e6 | balrog | } |
219 | 80f515e6 | balrog | #endif
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220 | 80f515e6 | balrog | } |
221 | 80f515e6 | balrog | |
222 | b279e5ef | Benoît Canet | static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset, |
223 | b279e5ef | Benoît Canet | unsigned size)
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224 | 80f515e6 | balrog | { |
225 | 80f515e6 | balrog | struct intc_desc *desc = opaque;
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226 | 80f515e6 | balrog | intc_enum *enum_ids = NULL;
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227 | 80f515e6 | balrog | unsigned int first = 0; |
228 | 80f515e6 | balrog | unsigned int width = 0; |
229 | 80f515e6 | balrog | unsigned int mode = 0; |
230 | 80f515e6 | balrog | unsigned long *valuep; |
231 | 80f515e6 | balrog | |
232 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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233 | 80f515e6 | balrog | printf("sh_intc_read 0x%lx\n", (unsigned long) offset); |
234 | 80f515e6 | balrog | #endif
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235 | 80f515e6 | balrog | |
236 | 80f515e6 | balrog | sh_intc_locate(desc, (unsigned long)offset, &valuep, |
237 | 80f515e6 | balrog | &enum_ids, &first, &width, &mode); |
238 | 80f515e6 | balrog | return *valuep;
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239 | 80f515e6 | balrog | } |
240 | 80f515e6 | balrog | |
241 | c227f099 | Anthony Liguori | static void sh_intc_write(void *opaque, target_phys_addr_t offset, |
242 | b279e5ef | Benoît Canet | uint64_t value, unsigned size)
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243 | 80f515e6 | balrog | { |
244 | 80f515e6 | balrog | struct intc_desc *desc = opaque;
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245 | 80f515e6 | balrog | intc_enum *enum_ids = NULL;
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246 | 80f515e6 | balrog | unsigned int first = 0; |
247 | 80f515e6 | balrog | unsigned int width = 0; |
248 | 80f515e6 | balrog | unsigned int mode = 0; |
249 | 80f515e6 | balrog | unsigned int k; |
250 | 80f515e6 | balrog | unsigned long *valuep; |
251 | 80f515e6 | balrog | unsigned long mask; |
252 | 80f515e6 | balrog | |
253 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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254 | 80f515e6 | balrog | printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
255 | 80f515e6 | balrog | #endif
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256 | 80f515e6 | balrog | |
257 | 80f515e6 | balrog | sh_intc_locate(desc, (unsigned long)offset, &valuep, |
258 | 80f515e6 | balrog | &enum_ids, &first, &width, &mode); |
259 | 80f515e6 | balrog | |
260 | 80f515e6 | balrog | switch (mode) {
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261 | 80f515e6 | balrog | case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; |
262 | 80f515e6 | balrog | case INTC_MODE_DUAL_SET: value |= *valuep; break; |
263 | 80f515e6 | balrog | case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; |
264 | 43dc2a64 | Blue Swirl | default: abort();
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265 | 80f515e6 | balrog | } |
266 | 80f515e6 | balrog | |
267 | 80f515e6 | balrog | for (k = 0; k <= first; k++) { |
268 | 80f515e6 | balrog | mask = ((1 << width) - 1) << ((first - k) * width); |
269 | 80f515e6 | balrog | |
270 | 80f515e6 | balrog | if ((*valuep & mask) == (value & mask))
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271 | 80f515e6 | balrog | continue;
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272 | 80f515e6 | balrog | #if 0
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273 | 80f515e6 | balrog | printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
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274 | 80f515e6 | balrog | k, first, enum_ids[k], (unsigned int)mask);
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275 | 80f515e6 | balrog | #endif
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276 | e96e2044 | ths | sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
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277 | 80f515e6 | balrog | } |
278 | 80f515e6 | balrog | |
279 | 80f515e6 | balrog | *valuep = value; |
280 | 80f515e6 | balrog | |
281 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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282 | 80f515e6 | balrog | printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value); |
283 | 80f515e6 | balrog | #endif
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284 | 80f515e6 | balrog | } |
285 | 80f515e6 | balrog | |
286 | 12f30833 | Stefan Weil | static const MemoryRegionOps sh_intc_ops = { |
287 | b279e5ef | Benoît Canet | .read = sh_intc_read, |
288 | b279e5ef | Benoît Canet | .write = sh_intc_write, |
289 | b279e5ef | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
290 | 80f515e6 | balrog | }; |
291 | 80f515e6 | balrog | |
292 | 80f515e6 | balrog | struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) |
293 | 80f515e6 | balrog | { |
294 | 80f515e6 | balrog | if (id)
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295 | 80f515e6 | balrog | return desc->sources + id;
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296 | 80f515e6 | balrog | |
297 | 80f515e6 | balrog | return NULL; |
298 | 80f515e6 | balrog | } |
299 | 80f515e6 | balrog | |
300 | b279e5ef | Benoît Canet | static unsigned int sh_intc_register(MemoryRegion *sysmem, |
301 | b279e5ef | Benoît Canet | struct intc_desc *desc,
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302 | b279e5ef | Benoît Canet | const unsigned long address, |
303 | b279e5ef | Benoît Canet | const char *type, |
304 | b279e5ef | Benoît Canet | const char *action, |
305 | b279e5ef | Benoît Canet | const unsigned int index) |
306 | 80f515e6 | balrog | { |
307 | b279e5ef | Benoît Canet | char name[60]; |
308 | b279e5ef | Benoît Canet | MemoryRegion *iomem, *iomem_p4, *iomem_a7; |
309 | b279e5ef | Benoît Canet | |
310 | b279e5ef | Benoît Canet | if (!address) {
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311 | b279e5ef | Benoît Canet | return 0; |
312 | 5c16736a | balrog | } |
313 | b279e5ef | Benoît Canet | |
314 | b279e5ef | Benoît Canet | iomem = &desc->iomem; |
315 | b279e5ef | Benoît Canet | iomem_p4 = desc->iomem_aliases + index; |
316 | b279e5ef | Benoît Canet | iomem_a7 = iomem_p4 + 1;
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317 | b279e5ef | Benoît Canet | |
318 | b279e5ef | Benoît Canet | #define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s" |
319 | b279e5ef | Benoît Canet | snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4"); |
320 | b279e5ef | Benoît Canet | memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
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321 | b279e5ef | Benoît Canet | memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4); |
322 | b279e5ef | Benoît Canet | |
323 | b279e5ef | Benoît Canet | snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7"); |
324 | b279e5ef | Benoît Canet | memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
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325 | b279e5ef | Benoît Canet | memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7); |
326 | b279e5ef | Benoît Canet | #undef SH_INTC_IOMEM_FORMAT
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327 | b279e5ef | Benoît Canet | |
328 | b279e5ef | Benoît Canet | /* used to increment aliases index */
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329 | b279e5ef | Benoît Canet | return 2; |
330 | 80f515e6 | balrog | } |
331 | 80f515e6 | balrog | |
332 | 80f515e6 | balrog | static void sh_intc_register_source(struct intc_desc *desc, |
333 | 80f515e6 | balrog | intc_enum source, |
334 | 80f515e6 | balrog | struct intc_group *groups,
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335 | 80f515e6 | balrog | int nr_groups)
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336 | 80f515e6 | balrog | { |
337 | 80f515e6 | balrog | unsigned int i, k; |
338 | 80f515e6 | balrog | struct intc_source *s;
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339 | 80f515e6 | balrog | |
340 | 80f515e6 | balrog | if (desc->mask_regs) {
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341 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
342 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
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343 | 80f515e6 | balrog | |
344 | b1503cda | malc | for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { |
345 | 80f515e6 | balrog | if (mr->enum_ids[k] != source)
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346 | 80f515e6 | balrog | continue;
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347 | 80f515e6 | balrog | |
348 | 80f515e6 | balrog | s = sh_intc_source(desc, mr->enum_ids[k]); |
349 | 80f515e6 | balrog | if (s)
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350 | 80f515e6 | balrog | s->enable_max++; |
351 | 80f515e6 | balrog | } |
352 | 80f515e6 | balrog | } |
353 | 80f515e6 | balrog | } |
354 | 80f515e6 | balrog | |
355 | 80f515e6 | balrog | if (desc->prio_regs) {
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356 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
357 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
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358 | 80f515e6 | balrog | |
359 | b1503cda | malc | for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { |
360 | 80f515e6 | balrog | if (pr->enum_ids[k] != source)
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361 | 80f515e6 | balrog | continue;
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362 | 80f515e6 | balrog | |
363 | 80f515e6 | balrog | s = sh_intc_source(desc, pr->enum_ids[k]); |
364 | 80f515e6 | balrog | if (s)
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365 | 80f515e6 | balrog | s->enable_max++; |
366 | 80f515e6 | balrog | } |
367 | 80f515e6 | balrog | } |
368 | 80f515e6 | balrog | } |
369 | 80f515e6 | balrog | |
370 | 80f515e6 | balrog | if (groups) {
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371 | 80f515e6 | balrog | for (i = 0; i < nr_groups; i++) { |
372 | 80f515e6 | balrog | struct intc_group *gr = groups + i;
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373 | 80f515e6 | balrog | |
374 | b1503cda | malc | for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { |
375 | 80f515e6 | balrog | if (gr->enum_ids[k] != source)
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376 | 80f515e6 | balrog | continue;
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377 | 80f515e6 | balrog | |
378 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_ids[k]); |
379 | 80f515e6 | balrog | if (s)
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380 | 80f515e6 | balrog | s->enable_max++; |
381 | 80f515e6 | balrog | } |
382 | 80f515e6 | balrog | } |
383 | 80f515e6 | balrog | } |
384 | 80f515e6 | balrog | |
385 | 80f515e6 | balrog | } |
386 | 80f515e6 | balrog | |
387 | 80f515e6 | balrog | void sh_intc_register_sources(struct intc_desc *desc, |
388 | 80f515e6 | balrog | struct intc_vect *vectors,
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389 | 80f515e6 | balrog | int nr_vectors,
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390 | 80f515e6 | balrog | struct intc_group *groups,
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391 | 80f515e6 | balrog | int nr_groups)
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392 | 80f515e6 | balrog | { |
393 | 80f515e6 | balrog | unsigned int i, k; |
394 | 80f515e6 | balrog | struct intc_source *s;
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395 | 80f515e6 | balrog | |
396 | 80f515e6 | balrog | for (i = 0; i < nr_vectors; i++) { |
397 | 80f515e6 | balrog | struct intc_vect *vect = vectors + i;
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398 | 80f515e6 | balrog | |
399 | 80f515e6 | balrog | sh_intc_register_source(desc, vect->enum_id, groups, nr_groups); |
400 | 80f515e6 | balrog | s = sh_intc_source(desc, vect->enum_id); |
401 | 6f9faa91 | Stefan Weil | if (s) {
|
402 | 6f9faa91 | Stefan Weil | s->vect = vect->vect; |
403 | 80f515e6 | balrog | |
404 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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405 | 6f9faa91 | Stefan Weil | printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
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406 | 6f9faa91 | Stefan Weil | vect->enum_id, s->vect, s->enable_count, s->enable_max); |
407 | 80f515e6 | balrog | #endif
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408 | 6f9faa91 | Stefan Weil | } |
409 | 80f515e6 | balrog | } |
410 | 80f515e6 | balrog | |
411 | 80f515e6 | balrog | if (groups) {
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412 | 80f515e6 | balrog | for (i = 0; i < nr_groups; i++) { |
413 | 80f515e6 | balrog | struct intc_group *gr = groups + i;
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414 | 80f515e6 | balrog | |
415 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_id); |
416 | 80f515e6 | balrog | s->next_enum_id = gr->enum_ids[0];
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417 | 80f515e6 | balrog | |
418 | b1503cda | malc | for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { |
419 | 80f515e6 | balrog | if (!gr->enum_ids[k])
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420 | 80f515e6 | balrog | continue;
|
421 | 80f515e6 | balrog | |
422 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_ids[k - 1]);
|
423 | 80f515e6 | balrog | s->next_enum_id = gr->enum_ids[k]; |
424 | 80f515e6 | balrog | } |
425 | 80f515e6 | balrog | |
426 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
|
427 | 80f515e6 | balrog | printf("sh_intc: registered group %d (%d/%d)\n",
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428 | 80f515e6 | balrog | gr->enum_id, s->enable_count, s->enable_max); |
429 | 80f515e6 | balrog | #endif
|
430 | 80f515e6 | balrog | } |
431 | 80f515e6 | balrog | } |
432 | 80f515e6 | balrog | } |
433 | 80f515e6 | balrog | |
434 | b279e5ef | Benoît Canet | int sh_intc_init(MemoryRegion *sysmem,
|
435 | b279e5ef | Benoît Canet | struct intc_desc *desc,
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436 | 80f515e6 | balrog | int nr_sources,
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437 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs,
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438 | 80f515e6 | balrog | int nr_mask_regs,
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439 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs,
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440 | 80f515e6 | balrog | int nr_prio_regs)
|
441 | 80f515e6 | balrog | { |
442 | b279e5ef | Benoît Canet | unsigned int i, j; |
443 | 80f515e6 | balrog | |
444 | e96e2044 | ths | desc->pending = 0;
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445 | 80f515e6 | balrog | desc->nr_sources = nr_sources; |
446 | 80f515e6 | balrog | desc->mask_regs = mask_regs; |
447 | 80f515e6 | balrog | desc->nr_mask_regs = nr_mask_regs; |
448 | 80f515e6 | balrog | desc->prio_regs = prio_regs; |
449 | 80f515e6 | balrog | desc->nr_prio_regs = nr_prio_regs; |
450 | b279e5ef | Benoît Canet | /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases).
|
451 | b279e5ef | Benoît Canet | **/
|
452 | b279e5ef | Benoît Canet | desc->iomem_aliases = g_new0(MemoryRegion, |
453 | b279e5ef | Benoît Canet | (nr_mask_regs + nr_prio_regs) * 4);
|
454 | 80f515e6 | balrog | |
455 | b279e5ef | Benoît Canet | j = 0;
|
456 | 80f515e6 | balrog | i = sizeof(struct intc_source) * nr_sources; |
457 | 7267c094 | Anthony Liguori | desc->sources = g_malloc0(i); |
458 | 80f515e6 | balrog | |
459 | e96e2044 | ths | for (i = 0; i < desc->nr_sources; i++) { |
460 | e96e2044 | ths | struct intc_source *source = desc->sources + i;
|
461 | e96e2044 | ths | |
462 | e96e2044 | ths | source->parent = desc; |
463 | e96e2044 | ths | } |
464 | 96e2fc41 | aurel32 | |
465 | 96e2fc41 | aurel32 | desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); |
466 | 80f515e6 | balrog | |
467 | b279e5ef | Benoît Canet | memory_region_init_io(&desc->iomem, &sh_intc_ops, desc, |
468 | b279e5ef | Benoît Canet | "interrupt-controller", 0x100000000ULL); |
469 | b279e5ef | Benoît Canet | |
470 | b279e5ef | Benoît Canet | #define INT_REG_PARAMS(reg_struct, type, action, j) \
|
471 | b279e5ef | Benoît Canet | reg_struct->action##_reg, #type, #action, j |
472 | 80f515e6 | balrog | if (desc->mask_regs) {
|
473 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
474 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
|
475 | 80f515e6 | balrog | |
476 | b279e5ef | Benoît Canet | j += sh_intc_register(sysmem, desc, |
477 | b279e5ef | Benoît Canet | INT_REG_PARAMS(mr, mask, set, j)); |
478 | b279e5ef | Benoît Canet | j += sh_intc_register(sysmem, desc, |
479 | b279e5ef | Benoît Canet | INT_REG_PARAMS(mr, mask, clr, j)); |
480 | 80f515e6 | balrog | } |
481 | 80f515e6 | balrog | } |
482 | 80f515e6 | balrog | |
483 | 80f515e6 | balrog | if (desc->prio_regs) {
|
484 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
485 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
|
486 | 80f515e6 | balrog | |
487 | b279e5ef | Benoît Canet | j += sh_intc_register(sysmem, desc, |
488 | b279e5ef | Benoît Canet | INT_REG_PARAMS(pr, prio, set, j)); |
489 | b279e5ef | Benoît Canet | j += sh_intc_register(sysmem, desc, |
490 | b279e5ef | Benoît Canet | INT_REG_PARAMS(pr, prio, clr, j)); |
491 | 80f515e6 | balrog | } |
492 | 80f515e6 | balrog | } |
493 | b279e5ef | Benoît Canet | #undef INT_REG_PARAMS
|
494 | 80f515e6 | balrog | |
495 | 80f515e6 | balrog | return 0; |
496 | 80f515e6 | balrog | } |
497 | c6d86a33 | balrog | |
498 | c6d86a33 | balrog | /* Assert level <n> IRL interrupt.
|
499 | c6d86a33 | balrog | 0:deassert. 1:lowest priority,... 15:highest priority. */
|
500 | c6d86a33 | balrog | void sh_intc_set_irl(void *opaque, int n, int level) |
501 | c6d86a33 | balrog | { |
502 | c6d86a33 | balrog | struct intc_source *s = opaque;
|
503 | c6d86a33 | balrog | int i, irl = level ^ 15; |
504 | c6d86a33 | balrog | for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { |
505 | c6d86a33 | balrog | if (i == irl)
|
506 | c6d86a33 | balrog | sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); |
507 | c6d86a33 | balrog | else
|
508 | c6d86a33 | balrog | if (s->asserted)
|
509 | c6d86a33 | balrog | sh_intc_toggle_source(s, 0, -1); |
510 | c6d86a33 | balrog | } |
511 | c6d86a33 | balrog | } |