root / hw / cs4231.c @ 47e4ca5a
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1 | b8174937 | bellard | /*
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2 | b8174937 | bellard | * QEMU Crystal CS4231 audio chip emulation
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3 | b8174937 | bellard | *
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4 | b8174937 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | b8174937 | bellard | *
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6 | b8174937 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | b8174937 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | b8174937 | bellard | * in the Software without restriction, including without limitation the rights
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9 | b8174937 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | b8174937 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | b8174937 | bellard | * furnished to do so, subject to the following conditions:
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12 | b8174937 | bellard | *
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13 | b8174937 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | b8174937 | bellard | * all copies or substantial portions of the Software.
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15 | b8174937 | bellard | *
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16 | b8174937 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | b8174937 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | b8174937 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | b8174937 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | b8174937 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | b8174937 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | b8174937 | bellard | * THE SOFTWARE.
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23 | b8174937 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | b8174937 | bellard | |
27 | b8174937 | bellard | /* debug CS4231 */
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28 | b8174937 | bellard | //#define DEBUG_CS
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29 | b8174937 | bellard | |
30 | b8174937 | bellard | /*
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31 | b8174937 | bellard | * In addition to Crystal CS4231 there is a DMA controller on Sparc.
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32 | b8174937 | bellard | */
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33 | b8174937 | bellard | #define CS_MAXADDR 0x3f |
34 | 5aca8c3b | blueswir1 | #define CS_SIZE (CS_MAXADDR + 1) |
35 | b8174937 | bellard | #define CS_REGS 16 |
36 | b8174937 | bellard | #define CS_DREGS 32 |
37 | b8174937 | bellard | #define CS_MAXDREG (CS_DREGS - 1) |
38 | b8174937 | bellard | |
39 | b8174937 | bellard | typedef struct CSState { |
40 | b8174937 | bellard | uint32_t regs[CS_REGS]; |
41 | b8174937 | bellard | uint8_t dregs[CS_DREGS]; |
42 | b8174937 | bellard | void *intctl;
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43 | b8174937 | bellard | } CSState; |
44 | b8174937 | bellard | |
45 | b8174937 | bellard | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
46 | b8174937 | bellard | #define CS_VER 0xa0 |
47 | b8174937 | bellard | #define CS_CDC_VER 0x8a |
48 | b8174937 | bellard | |
49 | b8174937 | bellard | #ifdef DEBUG_CS
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50 | b8174937 | bellard | #define DPRINTF(fmt, args...) \
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51 | b8174937 | bellard | do { printf("CS: " fmt , ##args); } while (0) |
52 | b8174937 | bellard | #else
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53 | b8174937 | bellard | #define DPRINTF(fmt, args...)
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54 | b8174937 | bellard | #endif
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55 | b8174937 | bellard | |
56 | b8174937 | bellard | static void cs_reset(void *opaque) |
57 | b8174937 | bellard | { |
58 | b8174937 | bellard | CSState *s = opaque; |
59 | b8174937 | bellard | |
60 | b8174937 | bellard | memset(s->regs, 0, CS_REGS * 4); |
61 | b8174937 | bellard | memset(s->dregs, 0, CS_DREGS);
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62 | b8174937 | bellard | s->dregs[12] = CS_CDC_VER;
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63 | b8174937 | bellard | s->dregs[25] = CS_VER;
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64 | b8174937 | bellard | } |
65 | b8174937 | bellard | |
66 | b8174937 | bellard | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
67 | b8174937 | bellard | { |
68 | b8174937 | bellard | CSState *s = opaque; |
69 | b8174937 | bellard | uint32_t saddr, ret; |
70 | b8174937 | bellard | |
71 | b8174937 | bellard | saddr = (addr & CS_MAXADDR) >> 2;
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72 | b8174937 | bellard | switch (saddr) {
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73 | b8174937 | bellard | case 1: |
74 | b8174937 | bellard | switch (CS_RAP(s)) {
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75 | b8174937 | bellard | case 3: // Write only |
76 | b8174937 | bellard | ret = 0;
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77 | b8174937 | bellard | break;
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78 | b8174937 | bellard | default:
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79 | b8174937 | bellard | ret = s->dregs[CS_RAP(s)]; |
80 | b8174937 | bellard | break;
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81 | b8174937 | bellard | } |
82 | b8174937 | bellard | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
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83 | f930d07e | blueswir1 | break;
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84 | b8174937 | bellard | default:
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85 | b8174937 | bellard | ret = s->regs[saddr]; |
86 | b8174937 | bellard | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
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87 | f930d07e | blueswir1 | break;
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88 | b8174937 | bellard | } |
89 | b8174937 | bellard | return ret;
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90 | b8174937 | bellard | } |
91 | b8174937 | bellard | |
92 | b8174937 | bellard | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
93 | b8174937 | bellard | { |
94 | b8174937 | bellard | CSState *s = opaque; |
95 | b8174937 | bellard | uint32_t saddr; |
96 | b8174937 | bellard | |
97 | b8174937 | bellard | saddr = (addr & CS_MAXADDR) >> 2;
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98 | b8174937 | bellard | DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
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99 | b8174937 | bellard | switch (saddr) {
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100 | b8174937 | bellard | case 1: |
101 | b8174937 | bellard | DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
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102 | b8174937 | bellard | switch(CS_RAP(s)) {
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103 | b8174937 | bellard | case 11: |
104 | b8174937 | bellard | case 25: // Read only |
105 | b8174937 | bellard | break;
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106 | b8174937 | bellard | case 12: |
107 | b8174937 | bellard | val &= 0x40;
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108 | b8174937 | bellard | val |= CS_CDC_VER; // Codec version
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109 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
110 | b8174937 | bellard | break;
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111 | b8174937 | bellard | default:
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112 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
113 | b8174937 | bellard | break;
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114 | b8174937 | bellard | } |
115 | b8174937 | bellard | break;
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116 | b8174937 | bellard | case 2: // Read only |
117 | b8174937 | bellard | break;
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118 | b8174937 | bellard | case 4: |
119 | b8174937 | bellard | if (val & 1) |
120 | b8174937 | bellard | cs_reset(s); |
121 | b8174937 | bellard | val &= 0x7f;
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122 | b8174937 | bellard | s->regs[saddr] = val; |
123 | b8174937 | bellard | break;
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124 | b8174937 | bellard | default:
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125 | b8174937 | bellard | s->regs[saddr] = val; |
126 | f930d07e | blueswir1 | break;
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127 | b8174937 | bellard | } |
128 | b8174937 | bellard | } |
129 | b8174937 | bellard | |
130 | b8174937 | bellard | static CPUReadMemoryFunc *cs_mem_read[3] = { |
131 | b8174937 | bellard | cs_mem_readl, |
132 | b8174937 | bellard | cs_mem_readl, |
133 | b8174937 | bellard | cs_mem_readl, |
134 | b8174937 | bellard | }; |
135 | b8174937 | bellard | |
136 | b8174937 | bellard | static CPUWriteMemoryFunc *cs_mem_write[3] = { |
137 | b8174937 | bellard | cs_mem_writel, |
138 | b8174937 | bellard | cs_mem_writel, |
139 | b8174937 | bellard | cs_mem_writel, |
140 | b8174937 | bellard | }; |
141 | b8174937 | bellard | |
142 | b8174937 | bellard | static void cs_save(QEMUFile *f, void *opaque) |
143 | b8174937 | bellard | { |
144 | b8174937 | bellard | CSState *s = opaque; |
145 | b8174937 | bellard | unsigned int i; |
146 | b8174937 | bellard | |
147 | b8174937 | bellard | for (i = 0; i < CS_REGS; i++) |
148 | b8174937 | bellard | qemu_put_be32s(f, &s->regs[i]); |
149 | b8174937 | bellard | |
150 | b8174937 | bellard | qemu_put_buffer(f, s->dregs, CS_DREGS); |
151 | b8174937 | bellard | } |
152 | b8174937 | bellard | |
153 | b8174937 | bellard | static int cs_load(QEMUFile *f, void *opaque, int version_id) |
154 | b8174937 | bellard | { |
155 | b8174937 | bellard | CSState *s = opaque; |
156 | b8174937 | bellard | unsigned int i; |
157 | b8174937 | bellard | |
158 | b8174937 | bellard | if (version_id > 1) |
159 | b8174937 | bellard | return -EINVAL;
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160 | b8174937 | bellard | |
161 | b8174937 | bellard | for (i = 0; i < CS_REGS; i++) |
162 | b8174937 | bellard | qemu_get_be32s(f, &s->regs[i]); |
163 | b8174937 | bellard | |
164 | b8174937 | bellard | qemu_get_buffer(f, s->dregs, CS_DREGS); |
165 | b8174937 | bellard | return 0; |
166 | b8174937 | bellard | } |
167 | b8174937 | bellard | |
168 | b8174937 | bellard | void cs_init(target_phys_addr_t base, int irq, void *intctl) |
169 | b8174937 | bellard | { |
170 | b8174937 | bellard | int cs_io_memory;
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171 | b8174937 | bellard | CSState *s; |
172 | b8174937 | bellard | |
173 | b8174937 | bellard | s = qemu_mallocz(sizeof(CSState));
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174 | b8174937 | bellard | if (!s)
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175 | b8174937 | bellard | return;
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176 | b8174937 | bellard | |
177 | b8174937 | bellard | cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
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178 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base, CS_SIZE, cs_io_memory); |
179 | b8174937 | bellard | register_savevm("cs4231", base, 1, cs_save, cs_load, s); |
180 | b8174937 | bellard | qemu_register_reset(cs_reset, s); |
181 | b8174937 | bellard | cs_reset(s); |
182 | b8174937 | bellard | } |