root / hw / lsi53c895a.c @ 47e4ca5a
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1 | 5fafdf24 | ths | /*
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2 | 7d8406be | pbrook | * QEMU LSI53C895A SCSI Host Bus Adapter emulation
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3 | 7d8406be | pbrook | *
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4 | 7d8406be | pbrook | * Copyright (c) 2006 CodeSourcery.
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5 | 7d8406be | pbrook | * Written by Paul Brook
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6 | 7d8406be | pbrook | *
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7 | 7d8406be | pbrook | * This code is licenced under the LGPL.
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8 | 7d8406be | pbrook | */
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9 | 7d8406be | pbrook | |
10 | 7d8406be | pbrook | /* ??? Need to check if the {read,write}[wl] routines work properly on
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11 | 7d8406be | pbrook | big-endian targets. */
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12 | 7d8406be | pbrook | |
13 | 87ecb68b | pbrook | #include "hw.h" |
14 | 87ecb68b | pbrook | #include "pci.h" |
15 | 87ecb68b | pbrook | #include "scsi-disk.h" |
16 | 7d8406be | pbrook | |
17 | 7d8406be | pbrook | //#define DEBUG_LSI
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18 | 7d8406be | pbrook | //#define DEBUG_LSI_REG
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19 | 7d8406be | pbrook | |
20 | 7d8406be | pbrook | #ifdef DEBUG_LSI
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21 | 7d8406be | pbrook | #define DPRINTF(fmt, args...) \
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22 | 7d8406be | pbrook | do { printf("lsi_scsi: " fmt , ##args); } while (0) |
23 | 7d8406be | pbrook | #define BADF(fmt, args...) \
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24 | a917d384 | pbrook | do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0) |
25 | 7d8406be | pbrook | #else
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26 | 7d8406be | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
27 | 7d8406be | pbrook | #define BADF(fmt, args...) \
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28 | a917d384 | pbrook | do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0) |
29 | 7d8406be | pbrook | #endif
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30 | 7d8406be | pbrook | |
31 | 7d8406be | pbrook | #define LSI_SCNTL0_TRG 0x01 |
32 | 7d8406be | pbrook | #define LSI_SCNTL0_AAP 0x02 |
33 | 7d8406be | pbrook | #define LSI_SCNTL0_EPC 0x08 |
34 | 7d8406be | pbrook | #define LSI_SCNTL0_WATN 0x10 |
35 | 7d8406be | pbrook | #define LSI_SCNTL0_START 0x20 |
36 | 7d8406be | pbrook | |
37 | 7d8406be | pbrook | #define LSI_SCNTL1_SST 0x01 |
38 | 7d8406be | pbrook | #define LSI_SCNTL1_IARB 0x02 |
39 | 7d8406be | pbrook | #define LSI_SCNTL1_AESP 0x04 |
40 | 7d8406be | pbrook | #define LSI_SCNTL1_RST 0x08 |
41 | 7d8406be | pbrook | #define LSI_SCNTL1_CON 0x10 |
42 | 7d8406be | pbrook | #define LSI_SCNTL1_DHP 0x20 |
43 | 7d8406be | pbrook | #define LSI_SCNTL1_ADB 0x40 |
44 | 7d8406be | pbrook | #define LSI_SCNTL1_EXC 0x80 |
45 | 7d8406be | pbrook | |
46 | 7d8406be | pbrook | #define LSI_SCNTL2_WSR 0x01 |
47 | 7d8406be | pbrook | #define LSI_SCNTL2_VUE0 0x02 |
48 | 7d8406be | pbrook | #define LSI_SCNTL2_VUE1 0x04 |
49 | 7d8406be | pbrook | #define LSI_SCNTL2_WSS 0x08 |
50 | 7d8406be | pbrook | #define LSI_SCNTL2_SLPHBEN 0x10 |
51 | 7d8406be | pbrook | #define LSI_SCNTL2_SLPMD 0x20 |
52 | 7d8406be | pbrook | #define LSI_SCNTL2_CHM 0x40 |
53 | 7d8406be | pbrook | #define LSI_SCNTL2_SDU 0x80 |
54 | 7d8406be | pbrook | |
55 | 7d8406be | pbrook | #define LSI_ISTAT0_DIP 0x01 |
56 | 7d8406be | pbrook | #define LSI_ISTAT0_SIP 0x02 |
57 | 7d8406be | pbrook | #define LSI_ISTAT0_INTF 0x04 |
58 | 7d8406be | pbrook | #define LSI_ISTAT0_CON 0x08 |
59 | 7d8406be | pbrook | #define LSI_ISTAT0_SEM 0x10 |
60 | 7d8406be | pbrook | #define LSI_ISTAT0_SIGP 0x20 |
61 | 7d8406be | pbrook | #define LSI_ISTAT0_SRST 0x40 |
62 | 7d8406be | pbrook | #define LSI_ISTAT0_ABRT 0x80 |
63 | 7d8406be | pbrook | |
64 | 7d8406be | pbrook | #define LSI_ISTAT1_SI 0x01 |
65 | 7d8406be | pbrook | #define LSI_ISTAT1_SRUN 0x02 |
66 | 7d8406be | pbrook | #define LSI_ISTAT1_FLSH 0x04 |
67 | 7d8406be | pbrook | |
68 | 7d8406be | pbrook | #define LSI_SSTAT0_SDP0 0x01 |
69 | 7d8406be | pbrook | #define LSI_SSTAT0_RST 0x02 |
70 | 7d8406be | pbrook | #define LSI_SSTAT0_WOA 0x04 |
71 | 7d8406be | pbrook | #define LSI_SSTAT0_LOA 0x08 |
72 | 7d8406be | pbrook | #define LSI_SSTAT0_AIP 0x10 |
73 | 7d8406be | pbrook | #define LSI_SSTAT0_OLF 0x20 |
74 | 7d8406be | pbrook | #define LSI_SSTAT0_ORF 0x40 |
75 | 7d8406be | pbrook | #define LSI_SSTAT0_ILF 0x80 |
76 | 7d8406be | pbrook | |
77 | 7d8406be | pbrook | #define LSI_SIST0_PAR 0x01 |
78 | 7d8406be | pbrook | #define LSI_SIST0_RST 0x02 |
79 | 7d8406be | pbrook | #define LSI_SIST0_UDC 0x04 |
80 | 7d8406be | pbrook | #define LSI_SIST0_SGE 0x08 |
81 | 7d8406be | pbrook | #define LSI_SIST0_RSL 0x10 |
82 | 7d8406be | pbrook | #define LSI_SIST0_SEL 0x20 |
83 | 7d8406be | pbrook | #define LSI_SIST0_CMP 0x40 |
84 | 7d8406be | pbrook | #define LSI_SIST0_MA 0x80 |
85 | 7d8406be | pbrook | |
86 | 7d8406be | pbrook | #define LSI_SIST1_HTH 0x01 |
87 | 7d8406be | pbrook | #define LSI_SIST1_GEN 0x02 |
88 | 7d8406be | pbrook | #define LSI_SIST1_STO 0x04 |
89 | 7d8406be | pbrook | #define LSI_SIST1_SBMC 0x10 |
90 | 7d8406be | pbrook | |
91 | 7d8406be | pbrook | #define LSI_SOCL_IO 0x01 |
92 | 7d8406be | pbrook | #define LSI_SOCL_CD 0x02 |
93 | 7d8406be | pbrook | #define LSI_SOCL_MSG 0x04 |
94 | 7d8406be | pbrook | #define LSI_SOCL_ATN 0x08 |
95 | 7d8406be | pbrook | #define LSI_SOCL_SEL 0x10 |
96 | 7d8406be | pbrook | #define LSI_SOCL_BSY 0x20 |
97 | 7d8406be | pbrook | #define LSI_SOCL_ACK 0x40 |
98 | 7d8406be | pbrook | #define LSI_SOCL_REQ 0x80 |
99 | 7d8406be | pbrook | |
100 | 7d8406be | pbrook | #define LSI_DSTAT_IID 0x01 |
101 | 7d8406be | pbrook | #define LSI_DSTAT_SIR 0x04 |
102 | 7d8406be | pbrook | #define LSI_DSTAT_SSI 0x08 |
103 | 7d8406be | pbrook | #define LSI_DSTAT_ABRT 0x10 |
104 | 7d8406be | pbrook | #define LSI_DSTAT_BF 0x20 |
105 | 7d8406be | pbrook | #define LSI_DSTAT_MDPE 0x40 |
106 | 7d8406be | pbrook | #define LSI_DSTAT_DFE 0x80 |
107 | 7d8406be | pbrook | |
108 | 7d8406be | pbrook | #define LSI_DCNTL_COM 0x01 |
109 | 7d8406be | pbrook | #define LSI_DCNTL_IRQD 0x02 |
110 | 7d8406be | pbrook | #define LSI_DCNTL_STD 0x04 |
111 | 7d8406be | pbrook | #define LSI_DCNTL_IRQM 0x08 |
112 | 7d8406be | pbrook | #define LSI_DCNTL_SSM 0x10 |
113 | 7d8406be | pbrook | #define LSI_DCNTL_PFEN 0x20 |
114 | 7d8406be | pbrook | #define LSI_DCNTL_PFF 0x40 |
115 | 7d8406be | pbrook | #define LSI_DCNTL_CLSE 0x80 |
116 | 7d8406be | pbrook | |
117 | 7d8406be | pbrook | #define LSI_DMODE_MAN 0x01 |
118 | 7d8406be | pbrook | #define LSI_DMODE_BOF 0x02 |
119 | 7d8406be | pbrook | #define LSI_DMODE_ERMP 0x04 |
120 | 7d8406be | pbrook | #define LSI_DMODE_ERL 0x08 |
121 | 7d8406be | pbrook | #define LSI_DMODE_DIOM 0x10 |
122 | 7d8406be | pbrook | #define LSI_DMODE_SIOM 0x20 |
123 | 7d8406be | pbrook | |
124 | 7d8406be | pbrook | #define LSI_CTEST2_DACK 0x01 |
125 | 7d8406be | pbrook | #define LSI_CTEST2_DREQ 0x02 |
126 | 7d8406be | pbrook | #define LSI_CTEST2_TEOP 0x04 |
127 | 7d8406be | pbrook | #define LSI_CTEST2_PCICIE 0x08 |
128 | 7d8406be | pbrook | #define LSI_CTEST2_CM 0x10 |
129 | 7d8406be | pbrook | #define LSI_CTEST2_CIO 0x20 |
130 | 7d8406be | pbrook | #define LSI_CTEST2_SIGP 0x40 |
131 | 7d8406be | pbrook | #define LSI_CTEST2_DDIR 0x80 |
132 | 7d8406be | pbrook | |
133 | 7d8406be | pbrook | #define LSI_CTEST5_BL2 0x04 |
134 | 7d8406be | pbrook | #define LSI_CTEST5_DDIR 0x08 |
135 | 7d8406be | pbrook | #define LSI_CTEST5_MASR 0x10 |
136 | 7d8406be | pbrook | #define LSI_CTEST5_DFSN 0x20 |
137 | 7d8406be | pbrook | #define LSI_CTEST5_BBCK 0x40 |
138 | 7d8406be | pbrook | #define LSI_CTEST5_ADCK 0x80 |
139 | 7d8406be | pbrook | |
140 | 7d8406be | pbrook | #define LSI_CCNTL0_DILS 0x01 |
141 | 7d8406be | pbrook | #define LSI_CCNTL0_DISFC 0x10 |
142 | 7d8406be | pbrook | #define LSI_CCNTL0_ENNDJ 0x20 |
143 | 7d8406be | pbrook | #define LSI_CCNTL0_PMJCTL 0x40 |
144 | 7d8406be | pbrook | #define LSI_CCNTL0_ENPMJ 0x80 |
145 | 7d8406be | pbrook | |
146 | 7d8406be | pbrook | #define PHASE_DO 0 |
147 | 7d8406be | pbrook | #define PHASE_DI 1 |
148 | 7d8406be | pbrook | #define PHASE_CMD 2 |
149 | 7d8406be | pbrook | #define PHASE_ST 3 |
150 | 7d8406be | pbrook | #define PHASE_MO 6 |
151 | 7d8406be | pbrook | #define PHASE_MI 7 |
152 | 7d8406be | pbrook | #define PHASE_MASK 7 |
153 | 7d8406be | pbrook | |
154 | a917d384 | pbrook | /* Maximum length of MSG IN data. */
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155 | a917d384 | pbrook | #define LSI_MAX_MSGIN_LEN 8 |
156 | a917d384 | pbrook | |
157 | a917d384 | pbrook | /* Flag set if this is a tagged command. */
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158 | a917d384 | pbrook | #define LSI_TAG_VALID (1 << 16) |
159 | a917d384 | pbrook | |
160 | a917d384 | pbrook | typedef struct { |
161 | a917d384 | pbrook | uint32_t tag; |
162 | a917d384 | pbrook | uint32_t pending; |
163 | a917d384 | pbrook | int out;
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164 | a917d384 | pbrook | } lsi_queue; |
165 | 4d611c9a | pbrook | |
166 | 7d8406be | pbrook | typedef struct { |
167 | 7d8406be | pbrook | PCIDevice pci_dev; |
168 | 7d8406be | pbrook | int mmio_io_addr;
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169 | 7d8406be | pbrook | int ram_io_addr;
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170 | 7d8406be | pbrook | uint32_t script_ram_base; |
171 | 7d8406be | pbrook | |
172 | 7d8406be | pbrook | int carry; /* ??? Should this be an a visible register somewhere? */ |
173 | 7d8406be | pbrook | int sense;
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174 | a917d384 | pbrook | /* Action to take at the end of a MSG IN phase.
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175 | a917d384 | pbrook | 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
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176 | a917d384 | pbrook | int msg_action;
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177 | a917d384 | pbrook | int msg_len;
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178 | a917d384 | pbrook | uint8_t msg[LSI_MAX_MSGIN_LEN]; |
179 | 4d611c9a | pbrook | /* 0 if SCRIPTS are running or stopped.
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180 | 4d611c9a | pbrook | * 1 if a Wait Reselect instruction has been issued.
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181 | a917d384 | pbrook | * 2 if processing DMA from lsi_execute_script.
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182 | a917d384 | pbrook | * 3 if a DMA operation is in progress. */
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183 | 7d8406be | pbrook | int waiting;
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184 | 7d8406be | pbrook | SCSIDevice *scsi_dev[LSI_MAX_DEVS]; |
185 | 7d8406be | pbrook | SCSIDevice *current_dev; |
186 | 7d8406be | pbrook | int current_lun;
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187 | a917d384 | pbrook | /* The tag is a combination of the device ID and the SCSI tag. */
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188 | a917d384 | pbrook | uint32_t current_tag; |
189 | a917d384 | pbrook | uint32_t current_dma_len; |
190 | 8ccc2ace | ths | int command_complete;
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191 | a917d384 | pbrook | uint8_t *dma_buf; |
192 | a917d384 | pbrook | lsi_queue *queue; |
193 | a917d384 | pbrook | int queue_len;
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194 | a917d384 | pbrook | int active_commands;
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195 | 7d8406be | pbrook | |
196 | 7d8406be | pbrook | uint32_t dsa; |
197 | 7d8406be | pbrook | uint32_t temp; |
198 | 7d8406be | pbrook | uint32_t dnad; |
199 | 7d8406be | pbrook | uint32_t dbc; |
200 | 7d8406be | pbrook | uint8_t istat0; |
201 | 7d8406be | pbrook | uint8_t istat1; |
202 | 7d8406be | pbrook | uint8_t dcmd; |
203 | 7d8406be | pbrook | uint8_t dstat; |
204 | 7d8406be | pbrook | uint8_t dien; |
205 | 7d8406be | pbrook | uint8_t sist0; |
206 | 7d8406be | pbrook | uint8_t sist1; |
207 | 7d8406be | pbrook | uint8_t sien0; |
208 | 7d8406be | pbrook | uint8_t sien1; |
209 | 7d8406be | pbrook | uint8_t mbox0; |
210 | 7d8406be | pbrook | uint8_t mbox1; |
211 | 7d8406be | pbrook | uint8_t dfifo; |
212 | 7d8406be | pbrook | uint8_t ctest3; |
213 | 7d8406be | pbrook | uint8_t ctest4; |
214 | 7d8406be | pbrook | uint8_t ctest5; |
215 | 7d8406be | pbrook | uint8_t ccntl0; |
216 | 7d8406be | pbrook | uint8_t ccntl1; |
217 | 7d8406be | pbrook | uint32_t dsp; |
218 | 7d8406be | pbrook | uint32_t dsps; |
219 | 7d8406be | pbrook | uint8_t dmode; |
220 | 7d8406be | pbrook | uint8_t dcntl; |
221 | 7d8406be | pbrook | uint8_t scntl0; |
222 | 7d8406be | pbrook | uint8_t scntl1; |
223 | 7d8406be | pbrook | uint8_t scntl2; |
224 | 7d8406be | pbrook | uint8_t scntl3; |
225 | 7d8406be | pbrook | uint8_t sstat0; |
226 | 7d8406be | pbrook | uint8_t sstat1; |
227 | 7d8406be | pbrook | uint8_t scid; |
228 | 7d8406be | pbrook | uint8_t sxfer; |
229 | 7d8406be | pbrook | uint8_t socl; |
230 | 7d8406be | pbrook | uint8_t sdid; |
231 | a917d384 | pbrook | uint8_t ssid; |
232 | 7d8406be | pbrook | uint8_t sfbr; |
233 | 7d8406be | pbrook | uint8_t stest1; |
234 | 7d8406be | pbrook | uint8_t stest2; |
235 | 7d8406be | pbrook | uint8_t stest3; |
236 | a917d384 | pbrook | uint8_t sidl; |
237 | 7d8406be | pbrook | uint8_t stime0; |
238 | 7d8406be | pbrook | uint8_t respid0; |
239 | 7d8406be | pbrook | uint8_t respid1; |
240 | 7d8406be | pbrook | uint32_t mmrs; |
241 | 7d8406be | pbrook | uint32_t mmws; |
242 | 7d8406be | pbrook | uint32_t sfs; |
243 | 7d8406be | pbrook | uint32_t drs; |
244 | 7d8406be | pbrook | uint32_t sbms; |
245 | 7d8406be | pbrook | uint32_t dmbs; |
246 | 7d8406be | pbrook | uint32_t dnad64; |
247 | 7d8406be | pbrook | uint32_t pmjad1; |
248 | 7d8406be | pbrook | uint32_t pmjad2; |
249 | 7d8406be | pbrook | uint32_t rbc; |
250 | 7d8406be | pbrook | uint32_t ua; |
251 | 7d8406be | pbrook | uint32_t ia; |
252 | 7d8406be | pbrook | uint32_t sbc; |
253 | 7d8406be | pbrook | uint32_t csbc; |
254 | dcfb9014 | ths | uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ |
255 | 7d8406be | pbrook | |
256 | 7d8406be | pbrook | /* Script ram is stored as 32-bit words in host byteorder. */
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257 | 7d8406be | pbrook | uint32_t script_ram[2048];
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258 | 7d8406be | pbrook | } LSIState; |
259 | 7d8406be | pbrook | |
260 | 7d8406be | pbrook | static void lsi_soft_reset(LSIState *s) |
261 | 7d8406be | pbrook | { |
262 | 7d8406be | pbrook | DPRINTF("Reset\n");
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263 | 7d8406be | pbrook | s->carry = 0;
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264 | 7d8406be | pbrook | |
265 | 7d8406be | pbrook | s->waiting = 0;
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266 | 7d8406be | pbrook | s->dsa = 0;
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267 | 7d8406be | pbrook | s->dnad = 0;
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268 | 7d8406be | pbrook | s->dbc = 0;
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269 | 7d8406be | pbrook | s->temp = 0;
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270 | 7d8406be | pbrook | memset(s->scratch, 0, sizeof(s->scratch)); |
271 | 7d8406be | pbrook | s->istat0 = 0;
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272 | 7d8406be | pbrook | s->istat1 = 0;
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273 | 7d8406be | pbrook | s->dcmd = 0;
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274 | 7d8406be | pbrook | s->dstat = 0;
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275 | 7d8406be | pbrook | s->dien = 0;
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276 | 7d8406be | pbrook | s->sist0 = 0;
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277 | 7d8406be | pbrook | s->sist1 = 0;
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278 | 7d8406be | pbrook | s->sien0 = 0;
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279 | 7d8406be | pbrook | s->sien1 = 0;
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280 | 7d8406be | pbrook | s->mbox0 = 0;
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281 | 7d8406be | pbrook | s->mbox1 = 0;
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282 | 7d8406be | pbrook | s->dfifo = 0;
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283 | 7d8406be | pbrook | s->ctest3 = 0;
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284 | 7d8406be | pbrook | s->ctest4 = 0;
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285 | 7d8406be | pbrook | s->ctest5 = 0;
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286 | 7d8406be | pbrook | s->ccntl0 = 0;
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287 | 7d8406be | pbrook | s->ccntl1 = 0;
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288 | 7d8406be | pbrook | s->dsp = 0;
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289 | 7d8406be | pbrook | s->dsps = 0;
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290 | 7d8406be | pbrook | s->dmode = 0;
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291 | 7d8406be | pbrook | s->dcntl = 0;
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292 | 7d8406be | pbrook | s->scntl0 = 0xc0;
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293 | 7d8406be | pbrook | s->scntl1 = 0;
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294 | 7d8406be | pbrook | s->scntl2 = 0;
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295 | 7d8406be | pbrook | s->scntl3 = 0;
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296 | 7d8406be | pbrook | s->sstat0 = 0;
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297 | 7d8406be | pbrook | s->sstat1 = 0;
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298 | 7d8406be | pbrook | s->scid = 7;
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299 | 7d8406be | pbrook | s->sxfer = 0;
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300 | 7d8406be | pbrook | s->socl = 0;
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301 | 7d8406be | pbrook | s->stest1 = 0;
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302 | 7d8406be | pbrook | s->stest2 = 0;
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303 | 7d8406be | pbrook | s->stest3 = 0;
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304 | a917d384 | pbrook | s->sidl = 0;
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305 | 7d8406be | pbrook | s->stime0 = 0;
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306 | 7d8406be | pbrook | s->respid0 = 0x80;
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307 | 7d8406be | pbrook | s->respid1 = 0;
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308 | 7d8406be | pbrook | s->mmrs = 0;
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309 | 7d8406be | pbrook | s->mmws = 0;
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310 | 7d8406be | pbrook | s->sfs = 0;
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311 | 7d8406be | pbrook | s->drs = 0;
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312 | 7d8406be | pbrook | s->sbms = 0;
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313 | 7d8406be | pbrook | s->dmbs = 0;
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314 | 7d8406be | pbrook | s->dnad64 = 0;
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315 | 7d8406be | pbrook | s->pmjad1 = 0;
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316 | 7d8406be | pbrook | s->pmjad2 = 0;
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317 | 7d8406be | pbrook | s->rbc = 0;
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318 | 7d8406be | pbrook | s->ua = 0;
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319 | 7d8406be | pbrook | s->ia = 0;
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320 | 7d8406be | pbrook | s->sbc = 0;
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321 | 7d8406be | pbrook | s->csbc = 0;
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322 | 7d8406be | pbrook | } |
323 | 7d8406be | pbrook | |
324 | 7d8406be | pbrook | static uint8_t lsi_reg_readb(LSIState *s, int offset); |
325 | 7d8406be | pbrook | static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val); |
326 | 4d611c9a | pbrook | static void lsi_execute_script(LSIState *s); |
327 | 7d8406be | pbrook | |
328 | 7d8406be | pbrook | static inline uint32_t read_dword(LSIState *s, uint32_t addr) |
329 | 7d8406be | pbrook | { |
330 | 7d8406be | pbrook | uint32_t buf; |
331 | 7d8406be | pbrook | |
332 | 7d8406be | pbrook | /* Optimize reading from SCRIPTS RAM. */
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333 | 7d8406be | pbrook | if ((addr & 0xffffe000) == s->script_ram_base) { |
334 | 7d8406be | pbrook | return s->script_ram[(addr & 0x1fff) >> 2]; |
335 | 7d8406be | pbrook | } |
336 | 7d8406be | pbrook | cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
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337 | 7d8406be | pbrook | return cpu_to_le32(buf);
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338 | 7d8406be | pbrook | } |
339 | 7d8406be | pbrook | |
340 | 7d8406be | pbrook | static void lsi_stop_script(LSIState *s) |
341 | 7d8406be | pbrook | { |
342 | 7d8406be | pbrook | s->istat1 &= ~LSI_ISTAT1_SRUN; |
343 | 7d8406be | pbrook | } |
344 | 7d8406be | pbrook | |
345 | 7d8406be | pbrook | static void lsi_update_irq(LSIState *s) |
346 | 7d8406be | pbrook | { |
347 | 7d8406be | pbrook | int level;
|
348 | 7d8406be | pbrook | static int last_level; |
349 | 7d8406be | pbrook | |
350 | 7d8406be | pbrook | /* It's unclear whether the DIP/SIP bits should be cleared when the
|
351 | 7d8406be | pbrook | Interrupt Status Registers are cleared or when istat0 is read.
|
352 | 7d8406be | pbrook | We currently do the formwer, which seems to work. */
|
353 | 7d8406be | pbrook | level = 0;
|
354 | 7d8406be | pbrook | if (s->dstat) {
|
355 | 7d8406be | pbrook | if (s->dstat & s->dien)
|
356 | 7d8406be | pbrook | level = 1;
|
357 | 7d8406be | pbrook | s->istat0 |= LSI_ISTAT0_DIP; |
358 | 7d8406be | pbrook | } else {
|
359 | 7d8406be | pbrook | s->istat0 &= ~LSI_ISTAT0_DIP; |
360 | 7d8406be | pbrook | } |
361 | 7d8406be | pbrook | |
362 | 7d8406be | pbrook | if (s->sist0 || s->sist1) {
|
363 | 7d8406be | pbrook | if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
|
364 | 7d8406be | pbrook | level = 1;
|
365 | 7d8406be | pbrook | s->istat0 |= LSI_ISTAT0_SIP; |
366 | 7d8406be | pbrook | } else {
|
367 | 7d8406be | pbrook | s->istat0 &= ~LSI_ISTAT0_SIP; |
368 | 7d8406be | pbrook | } |
369 | 7d8406be | pbrook | if (s->istat0 & LSI_ISTAT0_INTF)
|
370 | 7d8406be | pbrook | level = 1;
|
371 | 7d8406be | pbrook | |
372 | 7d8406be | pbrook | if (level != last_level) {
|
373 | 7d8406be | pbrook | DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
|
374 | 7d8406be | pbrook | level, s->dstat, s->sist1, s->sist0); |
375 | 7d8406be | pbrook | last_level = level; |
376 | 7d8406be | pbrook | } |
377 | d537cf6c | pbrook | qemu_set_irq(s->pci_dev.irq[0], level);
|
378 | 7d8406be | pbrook | } |
379 | 7d8406be | pbrook | |
380 | 7d8406be | pbrook | /* Stop SCRIPTS execution and raise a SCSI interrupt. */
|
381 | 7d8406be | pbrook | static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1) |
382 | 7d8406be | pbrook | { |
383 | 7d8406be | pbrook | uint32_t mask0; |
384 | 7d8406be | pbrook | uint32_t mask1; |
385 | 7d8406be | pbrook | |
386 | 7d8406be | pbrook | DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
|
387 | 7d8406be | pbrook | stat1, stat0, s->sist1, s->sist0); |
388 | 7d8406be | pbrook | s->sist0 |= stat0; |
389 | 7d8406be | pbrook | s->sist1 |= stat1; |
390 | 7d8406be | pbrook | /* Stop processor on fatal or unmasked interrupt. As a special hack
|
391 | 7d8406be | pbrook | we don't stop processing when raising STO. Instead continue
|
392 | 7d8406be | pbrook | execution and stop at the next insn that accesses the SCSI bus. */
|
393 | 7d8406be | pbrook | mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL); |
394 | 7d8406be | pbrook | mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH); |
395 | 7d8406be | pbrook | mask1 &= ~LSI_SIST1_STO; |
396 | 7d8406be | pbrook | if (s->sist0 & mask0 || s->sist1 & mask1) {
|
397 | 7d8406be | pbrook | lsi_stop_script(s); |
398 | 7d8406be | pbrook | } |
399 | 7d8406be | pbrook | lsi_update_irq(s); |
400 | 7d8406be | pbrook | } |
401 | 7d8406be | pbrook | |
402 | 7d8406be | pbrook | /* Stop SCRIPTS execution and raise a DMA interrupt. */
|
403 | 7d8406be | pbrook | static void lsi_script_dma_interrupt(LSIState *s, int stat) |
404 | 7d8406be | pbrook | { |
405 | 7d8406be | pbrook | DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
|
406 | 7d8406be | pbrook | s->dstat |= stat; |
407 | 7d8406be | pbrook | lsi_update_irq(s); |
408 | 7d8406be | pbrook | lsi_stop_script(s); |
409 | 7d8406be | pbrook | } |
410 | 7d8406be | pbrook | |
411 | 7d8406be | pbrook | static inline void lsi_set_phase(LSIState *s, int phase) |
412 | 7d8406be | pbrook | { |
413 | 7d8406be | pbrook | s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase; |
414 | 7d8406be | pbrook | } |
415 | 7d8406be | pbrook | |
416 | 7d8406be | pbrook | static void lsi_bad_phase(LSIState *s, int out, int new_phase) |
417 | 7d8406be | pbrook | { |
418 | 7d8406be | pbrook | /* Trigger a phase mismatch. */
|
419 | 7d8406be | pbrook | if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
|
420 | 7d8406be | pbrook | if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
|
421 | 7d8406be | pbrook | s->dsp = s->pmjad1; |
422 | 7d8406be | pbrook | } else {
|
423 | 7d8406be | pbrook | s->dsp = s->pmjad2; |
424 | 7d8406be | pbrook | } |
425 | 7d8406be | pbrook | DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
|
426 | 7d8406be | pbrook | } else {
|
427 | 7d8406be | pbrook | DPRINTF("Phase mismatch interrupt\n");
|
428 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
|
429 | 7d8406be | pbrook | lsi_stop_script(s); |
430 | 7d8406be | pbrook | } |
431 | 7d8406be | pbrook | lsi_set_phase(s, new_phase); |
432 | 7d8406be | pbrook | } |
433 | 7d8406be | pbrook | |
434 | a917d384 | pbrook | |
435 | a917d384 | pbrook | /* Resume SCRIPTS execution after a DMA operation. */
|
436 | a917d384 | pbrook | static void lsi_resume_script(LSIState *s) |
437 | a917d384 | pbrook | { |
438 | a917d384 | pbrook | if (s->waiting != 2) { |
439 | a917d384 | pbrook | s->waiting = 0;
|
440 | a917d384 | pbrook | lsi_execute_script(s); |
441 | a917d384 | pbrook | } else {
|
442 | a917d384 | pbrook | s->waiting = 0;
|
443 | a917d384 | pbrook | } |
444 | a917d384 | pbrook | } |
445 | a917d384 | pbrook | |
446 | 4d611c9a | pbrook | /* Initiate a SCSI layer data transfer. */
|
447 | 7d8406be | pbrook | static void lsi_do_dma(LSIState *s, int out) |
448 | 7d8406be | pbrook | { |
449 | 7d8406be | pbrook | uint32_t count; |
450 | a917d384 | pbrook | uint32_t addr; |
451 | 7d8406be | pbrook | |
452 | a917d384 | pbrook | if (!s->current_dma_len) {
|
453 | a917d384 | pbrook | /* Wait until data is available. */
|
454 | a917d384 | pbrook | DPRINTF("DMA no data available\n");
|
455 | a917d384 | pbrook | return;
|
456 | 7d8406be | pbrook | } |
457 | 7d8406be | pbrook | |
458 | a917d384 | pbrook | count = s->dbc; |
459 | a917d384 | pbrook | if (count > s->current_dma_len)
|
460 | a917d384 | pbrook | count = s->current_dma_len; |
461 | a917d384 | pbrook | DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
|
462 | a917d384 | pbrook | |
463 | a917d384 | pbrook | addr = s->dnad; |
464 | 7d8406be | pbrook | s->csbc += count; |
465 | a917d384 | pbrook | s->dnad += count; |
466 | a917d384 | pbrook | s->dbc -= count; |
467 | a917d384 | pbrook | |
468 | a917d384 | pbrook | if (s->dma_buf == NULL) { |
469 | 8ccc2ace | ths | s->dma_buf = s->current_dev->get_buf(s->current_dev, |
470 | 8ccc2ace | ths | s->current_tag); |
471 | a917d384 | pbrook | } |
472 | 7d8406be | pbrook | |
473 | 7d8406be | pbrook | /* ??? Set SFBR to first data byte. */
|
474 | a917d384 | pbrook | if (out) {
|
475 | a917d384 | pbrook | cpu_physical_memory_read(addr, s->dma_buf, count); |
476 | a917d384 | pbrook | } else {
|
477 | a917d384 | pbrook | cpu_physical_memory_write(addr, s->dma_buf, count); |
478 | a917d384 | pbrook | } |
479 | a917d384 | pbrook | s->current_dma_len -= count; |
480 | a917d384 | pbrook | if (s->current_dma_len == 0) { |
481 | a917d384 | pbrook | s->dma_buf = NULL;
|
482 | a917d384 | pbrook | if (out) {
|
483 | a917d384 | pbrook | /* Write the data. */
|
484 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, s->current_tag); |
485 | a917d384 | pbrook | } else {
|
486 | a917d384 | pbrook | /* Request any remaining data. */
|
487 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, s->current_tag); |
488 | a917d384 | pbrook | } |
489 | a917d384 | pbrook | } else {
|
490 | a917d384 | pbrook | s->dma_buf += count; |
491 | a917d384 | pbrook | lsi_resume_script(s); |
492 | a917d384 | pbrook | } |
493 | a917d384 | pbrook | } |
494 | a917d384 | pbrook | |
495 | a917d384 | pbrook | |
496 | a917d384 | pbrook | /* Add a command to the queue. */
|
497 | a917d384 | pbrook | static void lsi_queue_command(LSIState *s) |
498 | a917d384 | pbrook | { |
499 | a917d384 | pbrook | lsi_queue *p; |
500 | a917d384 | pbrook | |
501 | a917d384 | pbrook | DPRINTF("Queueing tag=0x%x\n", s->current_tag);
|
502 | a917d384 | pbrook | if (s->queue_len == s->active_commands) {
|
503 | a917d384 | pbrook | s->queue_len++; |
504 | a917d384 | pbrook | s->queue = realloc(s->queue, s->queue_len * sizeof(lsi_queue));
|
505 | a917d384 | pbrook | } |
506 | a917d384 | pbrook | p = &s->queue[s->active_commands++]; |
507 | a917d384 | pbrook | p->tag = s->current_tag; |
508 | a917d384 | pbrook | p->pending = 0;
|
509 | a917d384 | pbrook | p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
510 | a917d384 | pbrook | } |
511 | a917d384 | pbrook | |
512 | a917d384 | pbrook | /* Queue a byte for a MSG IN phase. */
|
513 | a917d384 | pbrook | static void lsi_add_msg_byte(LSIState *s, uint8_t data) |
514 | a917d384 | pbrook | { |
515 | a917d384 | pbrook | if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
|
516 | a917d384 | pbrook | BADF("MSG IN data too long\n");
|
517 | 4d611c9a | pbrook | } else {
|
518 | a917d384 | pbrook | DPRINTF("MSG IN 0x%02x\n", data);
|
519 | a917d384 | pbrook | s->msg[s->msg_len++] = data; |
520 | 7d8406be | pbrook | } |
521 | a917d384 | pbrook | } |
522 | a917d384 | pbrook | |
523 | a917d384 | pbrook | /* Perform reselection to continue a command. */
|
524 | a917d384 | pbrook | static void lsi_reselect(LSIState *s, uint32_t tag) |
525 | a917d384 | pbrook | { |
526 | a917d384 | pbrook | lsi_queue *p; |
527 | a917d384 | pbrook | int n;
|
528 | a917d384 | pbrook | int id;
|
529 | a917d384 | pbrook | |
530 | a917d384 | pbrook | p = NULL;
|
531 | a917d384 | pbrook | for (n = 0; n < s->active_commands; n++) { |
532 | a917d384 | pbrook | p = &s->queue[n]; |
533 | a917d384 | pbrook | if (p->tag == tag)
|
534 | a917d384 | pbrook | break;
|
535 | a917d384 | pbrook | } |
536 | a917d384 | pbrook | if (n == s->active_commands) {
|
537 | a917d384 | pbrook | BADF("Reselected non-existant command tag=0x%x\n", tag);
|
538 | a917d384 | pbrook | return;
|
539 | a917d384 | pbrook | } |
540 | a917d384 | pbrook | id = (tag >> 8) & 0xf; |
541 | a917d384 | pbrook | s->ssid = id | 0x80;
|
542 | a917d384 | pbrook | DPRINTF("Reselected target %d\n", id);
|
543 | a917d384 | pbrook | s->current_dev = s->scsi_dev[id]; |
544 | a917d384 | pbrook | s->current_tag = tag; |
545 | a917d384 | pbrook | s->scntl1 |= LSI_SCNTL1_CON; |
546 | a917d384 | pbrook | lsi_set_phase(s, PHASE_MI); |
547 | a917d384 | pbrook | s->msg_action = p->out ? 2 : 3; |
548 | a917d384 | pbrook | s->current_dma_len = p->pending; |
549 | a917d384 | pbrook | s->dma_buf = NULL;
|
550 | a917d384 | pbrook | lsi_add_msg_byte(s, 0x80);
|
551 | a917d384 | pbrook | if (s->current_tag & LSI_TAG_VALID) {
|
552 | a917d384 | pbrook | lsi_add_msg_byte(s, 0x20);
|
553 | a917d384 | pbrook | lsi_add_msg_byte(s, tag & 0xff);
|
554 | a917d384 | pbrook | } |
555 | a917d384 | pbrook | |
556 | a917d384 | pbrook | s->active_commands--; |
557 | a917d384 | pbrook | if (n != s->active_commands) {
|
558 | a917d384 | pbrook | s->queue[n] = s->queue[s->active_commands]; |
559 | a917d384 | pbrook | } |
560 | a917d384 | pbrook | } |
561 | a917d384 | pbrook | |
562 | a917d384 | pbrook | /* Record that data is available for a queued command. Returns zero if
|
563 | a917d384 | pbrook | the device was reselected, nonzero if the IO is deferred. */
|
564 | a917d384 | pbrook | static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg) |
565 | a917d384 | pbrook | { |
566 | a917d384 | pbrook | lsi_queue *p; |
567 | a917d384 | pbrook | int i;
|
568 | a917d384 | pbrook | for (i = 0; i < s->active_commands; i++) { |
569 | a917d384 | pbrook | p = &s->queue[i]; |
570 | a917d384 | pbrook | if (p->tag == tag) {
|
571 | a917d384 | pbrook | if (p->pending) {
|
572 | a917d384 | pbrook | BADF("Multiple IO pending for tag %d\n", tag);
|
573 | a917d384 | pbrook | } |
574 | a917d384 | pbrook | p->pending = arg; |
575 | a917d384 | pbrook | if (s->waiting == 1) { |
576 | a917d384 | pbrook | /* Reselect device. */
|
577 | a917d384 | pbrook | lsi_reselect(s, tag); |
578 | a917d384 | pbrook | return 0; |
579 | a917d384 | pbrook | } else {
|
580 | a917d384 | pbrook | DPRINTF("Queueing IO tag=0x%x\n", tag);
|
581 | a917d384 | pbrook | p->pending = arg; |
582 | a917d384 | pbrook | return 1; |
583 | a917d384 | pbrook | } |
584 | a917d384 | pbrook | } |
585 | a917d384 | pbrook | } |
586 | a917d384 | pbrook | BADF("IO with unknown tag %d\n", tag);
|
587 | a917d384 | pbrook | return 1; |
588 | 7d8406be | pbrook | } |
589 | 7d8406be | pbrook | |
590 | 4d611c9a | pbrook | /* Callback to indicate that the SCSI layer has completed a transfer. */
|
591 | a917d384 | pbrook | static void lsi_command_complete(void *opaque, int reason, uint32_t tag, |
592 | a917d384 | pbrook | uint32_t arg) |
593 | 4d611c9a | pbrook | { |
594 | 4d611c9a | pbrook | LSIState *s = (LSIState *)opaque; |
595 | 4d611c9a | pbrook | int out;
|
596 | 4d611c9a | pbrook | |
597 | a917d384 | pbrook | out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
598 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
|
599 | a917d384 | pbrook | DPRINTF("Command complete sense=%d\n", (int)arg); |
600 | a917d384 | pbrook | s->sense = arg; |
601 | 8ccc2ace | ths | s->command_complete = 2;
|
602 | a917d384 | pbrook | if (s->waiting && s->dbc != 0) { |
603 | a917d384 | pbrook | /* Raise phase mismatch for short transfers. */
|
604 | a917d384 | pbrook | lsi_bad_phase(s, out, PHASE_ST); |
605 | a917d384 | pbrook | } else {
|
606 | a917d384 | pbrook | lsi_set_phase(s, PHASE_ST); |
607 | a917d384 | pbrook | } |
608 | a917d384 | pbrook | lsi_resume_script(s); |
609 | a917d384 | pbrook | return;
|
610 | 4d611c9a | pbrook | } |
611 | 4d611c9a | pbrook | |
612 | a917d384 | pbrook | if (s->waiting == 1 || tag != s->current_tag) { |
613 | a917d384 | pbrook | if (lsi_queue_tag(s, tag, arg))
|
614 | a917d384 | pbrook | return;
|
615 | a917d384 | pbrook | } |
616 | a917d384 | pbrook | DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
|
617 | a917d384 | pbrook | s->current_dma_len = arg; |
618 | 8ccc2ace | ths | s->command_complete = 1;
|
619 | a917d384 | pbrook | if (!s->waiting)
|
620 | a917d384 | pbrook | return;
|
621 | a917d384 | pbrook | if (s->waiting == 1 || s->dbc == 0) { |
622 | a917d384 | pbrook | lsi_resume_script(s); |
623 | a917d384 | pbrook | } else {
|
624 | 4d611c9a | pbrook | lsi_do_dma(s, out); |
625 | 4d611c9a | pbrook | } |
626 | 4d611c9a | pbrook | } |
627 | 7d8406be | pbrook | |
628 | 7d8406be | pbrook | static void lsi_do_command(LSIState *s) |
629 | 7d8406be | pbrook | { |
630 | 7d8406be | pbrook | uint8_t buf[16];
|
631 | 7d8406be | pbrook | int n;
|
632 | 7d8406be | pbrook | |
633 | 7d8406be | pbrook | DPRINTF("Send command len=%d\n", s->dbc);
|
634 | 7d8406be | pbrook | if (s->dbc > 16) |
635 | 7d8406be | pbrook | s->dbc = 16;
|
636 | 7d8406be | pbrook | cpu_physical_memory_read(s->dnad, buf, s->dbc); |
637 | 7d8406be | pbrook | s->sfbr = buf[0];
|
638 | 8ccc2ace | ths | s->command_complete = 0;
|
639 | 8ccc2ace | ths | n = s->current_dev->send_command(s->current_dev, s->current_tag, buf, |
640 | 8ccc2ace | ths | s->current_lun); |
641 | 7d8406be | pbrook | if (n > 0) { |
642 | 7d8406be | pbrook | lsi_set_phase(s, PHASE_DI); |
643 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, s->current_tag); |
644 | 7d8406be | pbrook | } else if (n < 0) { |
645 | 7d8406be | pbrook | lsi_set_phase(s, PHASE_DO); |
646 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, s->current_tag); |
647 | a917d384 | pbrook | } |
648 | 8ccc2ace | ths | |
649 | 8ccc2ace | ths | if (!s->command_complete) {
|
650 | 8ccc2ace | ths | if (n) {
|
651 | 8ccc2ace | ths | /* Command did not complete immediately so disconnect. */
|
652 | 8ccc2ace | ths | lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */ |
653 | 8ccc2ace | ths | lsi_add_msg_byte(s, 4); /* DISCONNECT */ |
654 | 8ccc2ace | ths | /* wait data */
|
655 | 8ccc2ace | ths | lsi_set_phase(s, PHASE_MI); |
656 | 8ccc2ace | ths | s->msg_action = 1;
|
657 | 8ccc2ace | ths | lsi_queue_command(s); |
658 | 8ccc2ace | ths | } else {
|
659 | 8ccc2ace | ths | /* wait command complete */
|
660 | 8ccc2ace | ths | lsi_set_phase(s, PHASE_DI); |
661 | 8ccc2ace | ths | } |
662 | 7d8406be | pbrook | } |
663 | 7d8406be | pbrook | } |
664 | 7d8406be | pbrook | |
665 | 7d8406be | pbrook | static void lsi_do_status(LSIState *s) |
666 | 7d8406be | pbrook | { |
667 | a917d384 | pbrook | uint8_t sense; |
668 | 7d8406be | pbrook | DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
|
669 | 7d8406be | pbrook | if (s->dbc != 1) |
670 | 7d8406be | pbrook | BADF("Bad Status move\n");
|
671 | 7d8406be | pbrook | s->dbc = 1;
|
672 | a917d384 | pbrook | sense = s->sense; |
673 | a917d384 | pbrook | s->sfbr = sense; |
674 | a917d384 | pbrook | cpu_physical_memory_write(s->dnad, &sense, 1);
|
675 | 7d8406be | pbrook | lsi_set_phase(s, PHASE_MI); |
676 | a917d384 | pbrook | s->msg_action = 1;
|
677 | a917d384 | pbrook | lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */ |
678 | 7d8406be | pbrook | } |
679 | 7d8406be | pbrook | |
680 | 7d8406be | pbrook | static void lsi_disconnect(LSIState *s) |
681 | 7d8406be | pbrook | { |
682 | 7d8406be | pbrook | s->scntl1 &= ~LSI_SCNTL1_CON; |
683 | 7d8406be | pbrook | s->sstat1 &= ~PHASE_MASK; |
684 | 7d8406be | pbrook | } |
685 | 7d8406be | pbrook | |
686 | 7d8406be | pbrook | static void lsi_do_msgin(LSIState *s) |
687 | 7d8406be | pbrook | { |
688 | a917d384 | pbrook | int len;
|
689 | a917d384 | pbrook | DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
|
690 | a917d384 | pbrook | s->sfbr = s->msg[0];
|
691 | a917d384 | pbrook | len = s->msg_len; |
692 | a917d384 | pbrook | if (len > s->dbc)
|
693 | a917d384 | pbrook | len = s->dbc; |
694 | a917d384 | pbrook | cpu_physical_memory_write(s->dnad, s->msg, len); |
695 | a917d384 | pbrook | /* Linux drivers rely on the last byte being in the SIDL. */
|
696 | a917d384 | pbrook | s->sidl = s->msg[len - 1];
|
697 | a917d384 | pbrook | s->msg_len -= len; |
698 | a917d384 | pbrook | if (s->msg_len) {
|
699 | a917d384 | pbrook | memmove(s->msg, s->msg + len, s->msg_len); |
700 | 7d8406be | pbrook | } else {
|
701 | 7d8406be | pbrook | /* ??? Check if ATN (not yet implemented) is asserted and maybe
|
702 | 7d8406be | pbrook | switch to PHASE_MO. */
|
703 | a917d384 | pbrook | switch (s->msg_action) {
|
704 | a917d384 | pbrook | case 0: |
705 | a917d384 | pbrook | lsi_set_phase(s, PHASE_CMD); |
706 | a917d384 | pbrook | break;
|
707 | a917d384 | pbrook | case 1: |
708 | a917d384 | pbrook | lsi_disconnect(s); |
709 | a917d384 | pbrook | break;
|
710 | a917d384 | pbrook | case 2: |
711 | a917d384 | pbrook | lsi_set_phase(s, PHASE_DO); |
712 | a917d384 | pbrook | break;
|
713 | a917d384 | pbrook | case 3: |
714 | a917d384 | pbrook | lsi_set_phase(s, PHASE_DI); |
715 | a917d384 | pbrook | break;
|
716 | a917d384 | pbrook | default:
|
717 | a917d384 | pbrook | abort(); |
718 | a917d384 | pbrook | } |
719 | 7d8406be | pbrook | } |
720 | 7d8406be | pbrook | } |
721 | 7d8406be | pbrook | |
722 | a917d384 | pbrook | /* Read the next byte during a MSGOUT phase. */
|
723 | a917d384 | pbrook | static uint8_t lsi_get_msgbyte(LSIState *s)
|
724 | a917d384 | pbrook | { |
725 | a917d384 | pbrook | uint8_t data; |
726 | a917d384 | pbrook | cpu_physical_memory_read(s->dnad, &data, 1);
|
727 | a917d384 | pbrook | s->dnad++; |
728 | a917d384 | pbrook | s->dbc--; |
729 | a917d384 | pbrook | return data;
|
730 | a917d384 | pbrook | } |
731 | a917d384 | pbrook | |
732 | 7d8406be | pbrook | static void lsi_do_msgout(LSIState *s) |
733 | 7d8406be | pbrook | { |
734 | 7d8406be | pbrook | uint8_t msg; |
735 | a917d384 | pbrook | int len;
|
736 | 7d8406be | pbrook | |
737 | 7d8406be | pbrook | DPRINTF("MSG out len=%d\n", s->dbc);
|
738 | a917d384 | pbrook | while (s->dbc) {
|
739 | a917d384 | pbrook | msg = lsi_get_msgbyte(s); |
740 | a917d384 | pbrook | s->sfbr = msg; |
741 | a917d384 | pbrook | |
742 | a917d384 | pbrook | switch (msg) {
|
743 | a917d384 | pbrook | case 0x00: |
744 | a917d384 | pbrook | DPRINTF("MSG: Disconnect\n");
|
745 | a917d384 | pbrook | lsi_disconnect(s); |
746 | a917d384 | pbrook | break;
|
747 | a917d384 | pbrook | case 0x08: |
748 | a917d384 | pbrook | DPRINTF("MSG: No Operation\n");
|
749 | a917d384 | pbrook | lsi_set_phase(s, PHASE_CMD); |
750 | a917d384 | pbrook | break;
|
751 | a917d384 | pbrook | case 0x01: |
752 | a917d384 | pbrook | len = lsi_get_msgbyte(s); |
753 | a917d384 | pbrook | msg = lsi_get_msgbyte(s); |
754 | a917d384 | pbrook | DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
|
755 | a917d384 | pbrook | switch (msg) {
|
756 | a917d384 | pbrook | case 1: |
757 | a917d384 | pbrook | DPRINTF("SDTR (ignored)\n");
|
758 | a917d384 | pbrook | s->dbc -= 2;
|
759 | a917d384 | pbrook | break;
|
760 | a917d384 | pbrook | case 3: |
761 | a917d384 | pbrook | DPRINTF("WDTR (ignored)\n");
|
762 | a917d384 | pbrook | s->dbc -= 1;
|
763 | a917d384 | pbrook | break;
|
764 | a917d384 | pbrook | default:
|
765 | a917d384 | pbrook | goto bad;
|
766 | a917d384 | pbrook | } |
767 | a917d384 | pbrook | break;
|
768 | a917d384 | pbrook | case 0x20: /* SIMPLE queue */ |
769 | a917d384 | pbrook | s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
770 | a917d384 | pbrook | DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff); |
771 | a917d384 | pbrook | break;
|
772 | a917d384 | pbrook | case 0x21: /* HEAD of queue */ |
773 | a917d384 | pbrook | BADF("HEAD queue not implemented\n");
|
774 | a917d384 | pbrook | s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
775 | a917d384 | pbrook | break;
|
776 | a917d384 | pbrook | case 0x22: /* ORDERED queue */ |
777 | a917d384 | pbrook | BADF("ORDERED queue not implemented\n");
|
778 | a917d384 | pbrook | s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
779 | a917d384 | pbrook | break;
|
780 | a917d384 | pbrook | default:
|
781 | a917d384 | pbrook | if ((msg & 0x80) == 0) { |
782 | a917d384 | pbrook | goto bad;
|
783 | a917d384 | pbrook | } |
784 | a917d384 | pbrook | s->current_lun = msg & 7;
|
785 | a917d384 | pbrook | DPRINTF("Select LUN %d\n", s->current_lun);
|
786 | a917d384 | pbrook | lsi_set_phase(s, PHASE_CMD); |
787 | a917d384 | pbrook | break;
|
788 | a917d384 | pbrook | } |
789 | 7d8406be | pbrook | } |
790 | a917d384 | pbrook | return;
|
791 | a917d384 | pbrook | bad:
|
792 | a917d384 | pbrook | BADF("Unimplemented message 0x%02x\n", msg);
|
793 | a917d384 | pbrook | lsi_set_phase(s, PHASE_MI); |
794 | a917d384 | pbrook | lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */ |
795 | a917d384 | pbrook | s->msg_action = 0;
|
796 | 7d8406be | pbrook | } |
797 | 7d8406be | pbrook | |
798 | 7d8406be | pbrook | /* Sign extend a 24-bit value. */
|
799 | 7d8406be | pbrook | static inline int32_t sxt24(int32_t n) |
800 | 7d8406be | pbrook | { |
801 | 7d8406be | pbrook | return (n << 8) >> 8; |
802 | 7d8406be | pbrook | } |
803 | 7d8406be | pbrook | |
804 | 7d8406be | pbrook | static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count) |
805 | 7d8406be | pbrook | { |
806 | 7d8406be | pbrook | int n;
|
807 | 7d8406be | pbrook | uint8_t buf[TARGET_PAGE_SIZE]; |
808 | 7d8406be | pbrook | |
809 | 7d8406be | pbrook | DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
|
810 | 7d8406be | pbrook | while (count) {
|
811 | 7d8406be | pbrook | n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count; |
812 | 7d8406be | pbrook | cpu_physical_memory_read(src, buf, n); |
813 | 7d8406be | pbrook | cpu_physical_memory_write(dest, buf, n); |
814 | 7d8406be | pbrook | src += n; |
815 | 7d8406be | pbrook | dest += n; |
816 | 7d8406be | pbrook | count -= n; |
817 | 7d8406be | pbrook | } |
818 | 7d8406be | pbrook | } |
819 | 7d8406be | pbrook | |
820 | a917d384 | pbrook | static void lsi_wait_reselect(LSIState *s) |
821 | a917d384 | pbrook | { |
822 | a917d384 | pbrook | int i;
|
823 | a917d384 | pbrook | DPRINTF("Wait Reselect\n");
|
824 | a917d384 | pbrook | if (s->current_dma_len)
|
825 | a917d384 | pbrook | BADF("Reselect with pending DMA\n");
|
826 | a917d384 | pbrook | for (i = 0; i < s->active_commands; i++) { |
827 | a917d384 | pbrook | if (s->queue[i].pending) {
|
828 | a917d384 | pbrook | lsi_reselect(s, s->queue[i].tag); |
829 | a917d384 | pbrook | break;
|
830 | a917d384 | pbrook | } |
831 | a917d384 | pbrook | } |
832 | a917d384 | pbrook | if (s->current_dma_len == 0) { |
833 | a917d384 | pbrook | s->waiting = 1;
|
834 | a917d384 | pbrook | } |
835 | a917d384 | pbrook | } |
836 | a917d384 | pbrook | |
837 | 7d8406be | pbrook | static void lsi_execute_script(LSIState *s) |
838 | 7d8406be | pbrook | { |
839 | 7d8406be | pbrook | uint32_t insn; |
840 | 7d8406be | pbrook | uint32_t addr; |
841 | 7d8406be | pbrook | int opcode;
|
842 | 7d8406be | pbrook | |
843 | 7d8406be | pbrook | s->istat1 |= LSI_ISTAT1_SRUN; |
844 | 7d8406be | pbrook | again:
|
845 | 7d8406be | pbrook | insn = read_dword(s, s->dsp); |
846 | 7d8406be | pbrook | addr = read_dword(s, s->dsp + 4);
|
847 | 7d8406be | pbrook | DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
|
848 | 7d8406be | pbrook | s->dsps = addr; |
849 | 7d8406be | pbrook | s->dcmd = insn >> 24;
|
850 | 7d8406be | pbrook | s->dsp += 8;
|
851 | 7d8406be | pbrook | switch (insn >> 30) { |
852 | 7d8406be | pbrook | case 0: /* Block move. */ |
853 | 7d8406be | pbrook | if (s->sist1 & LSI_SIST1_STO) {
|
854 | 7d8406be | pbrook | DPRINTF("Delayed select timeout\n");
|
855 | 7d8406be | pbrook | lsi_stop_script(s); |
856 | 7d8406be | pbrook | break;
|
857 | 7d8406be | pbrook | } |
858 | 7d8406be | pbrook | s->dbc = insn & 0xffffff;
|
859 | 7d8406be | pbrook | s->rbc = s->dbc; |
860 | 7d8406be | pbrook | if (insn & (1 << 29)) { |
861 | 7d8406be | pbrook | /* Indirect addressing. */
|
862 | 7d8406be | pbrook | addr = read_dword(s, addr); |
863 | 7d8406be | pbrook | } else if (insn & (1 << 28)) { |
864 | 7d8406be | pbrook | uint32_t buf[2];
|
865 | 7d8406be | pbrook | int32_t offset; |
866 | 7d8406be | pbrook | /* Table indirect addressing. */
|
867 | 7d8406be | pbrook | offset = sxt24(addr); |
868 | 7d8406be | pbrook | cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
|
869 | 7d8406be | pbrook | s->dbc = cpu_to_le32(buf[0]);
|
870 | 7faa239c | ths | s->rbc = s->dbc; |
871 | 7d8406be | pbrook | addr = cpu_to_le32(buf[1]);
|
872 | 7d8406be | pbrook | } |
873 | 7d8406be | pbrook | if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) { |
874 | 7d8406be | pbrook | DPRINTF("Wrong phase got %d expected %d\n",
|
875 | 7d8406be | pbrook | s->sstat1 & PHASE_MASK, (insn >> 24) & 7); |
876 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
|
877 | 7d8406be | pbrook | break;
|
878 | 7d8406be | pbrook | } |
879 | 7d8406be | pbrook | s->dnad = addr; |
880 | 7faa239c | ths | /* ??? Set ESA. */
|
881 | 7faa239c | ths | s->ia = s->dsp - 8;
|
882 | 7d8406be | pbrook | switch (s->sstat1 & 0x7) { |
883 | 7d8406be | pbrook | case PHASE_DO:
|
884 | a917d384 | pbrook | s->waiting = 2;
|
885 | 7d8406be | pbrook | lsi_do_dma(s, 1);
|
886 | a917d384 | pbrook | if (s->waiting)
|
887 | a917d384 | pbrook | s->waiting = 3;
|
888 | 7d8406be | pbrook | break;
|
889 | 7d8406be | pbrook | case PHASE_DI:
|
890 | a917d384 | pbrook | s->waiting = 2;
|
891 | 7d8406be | pbrook | lsi_do_dma(s, 0);
|
892 | a917d384 | pbrook | if (s->waiting)
|
893 | a917d384 | pbrook | s->waiting = 3;
|
894 | 7d8406be | pbrook | break;
|
895 | 7d8406be | pbrook | case PHASE_CMD:
|
896 | 7d8406be | pbrook | lsi_do_command(s); |
897 | 7d8406be | pbrook | break;
|
898 | 7d8406be | pbrook | case PHASE_ST:
|
899 | 7d8406be | pbrook | lsi_do_status(s); |
900 | 7d8406be | pbrook | break;
|
901 | 7d8406be | pbrook | case PHASE_MO:
|
902 | 7d8406be | pbrook | lsi_do_msgout(s); |
903 | 7d8406be | pbrook | break;
|
904 | 7d8406be | pbrook | case PHASE_MI:
|
905 | 7d8406be | pbrook | lsi_do_msgin(s); |
906 | 7d8406be | pbrook | break;
|
907 | 7d8406be | pbrook | default:
|
908 | 7d8406be | pbrook | BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
|
909 | 7d8406be | pbrook | exit(1);
|
910 | 7d8406be | pbrook | } |
911 | 7d8406be | pbrook | s->dfifo = s->dbc & 0xff;
|
912 | 7d8406be | pbrook | s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3); |
913 | 7d8406be | pbrook | s->sbc = s->dbc; |
914 | 7d8406be | pbrook | s->rbc -= s->dbc; |
915 | 7d8406be | pbrook | s->ua = addr + s->dbc; |
916 | 7d8406be | pbrook | break;
|
917 | 7d8406be | pbrook | |
918 | 7d8406be | pbrook | case 1: /* IO or Read/Write instruction. */ |
919 | 7d8406be | pbrook | opcode = (insn >> 27) & 7; |
920 | 7d8406be | pbrook | if (opcode < 5) { |
921 | 7d8406be | pbrook | uint32_t id; |
922 | 7d8406be | pbrook | |
923 | 7d8406be | pbrook | if (insn & (1 << 25)) { |
924 | 7d8406be | pbrook | id = read_dword(s, s->dsa + sxt24(insn)); |
925 | 7d8406be | pbrook | } else {
|
926 | 7d8406be | pbrook | id = addr; |
927 | 7d8406be | pbrook | } |
928 | 7d8406be | pbrook | id = (id >> 16) & 0xf; |
929 | 7d8406be | pbrook | if (insn & (1 << 26)) { |
930 | 7d8406be | pbrook | addr = s->dsp + sxt24(addr); |
931 | 7d8406be | pbrook | } |
932 | 7d8406be | pbrook | s->dnad = addr; |
933 | 7d8406be | pbrook | switch (opcode) {
|
934 | 7d8406be | pbrook | case 0: /* Select */ |
935 | a917d384 | pbrook | s->sdid = id; |
936 | a917d384 | pbrook | if (s->current_dma_len && (s->ssid & 0xf) == id) { |
937 | a917d384 | pbrook | DPRINTF("Already reselected by target %d\n", id);
|
938 | a917d384 | pbrook | break;
|
939 | a917d384 | pbrook | } |
940 | 7d8406be | pbrook | s->sstat0 |= LSI_SSTAT0_WOA; |
941 | 7d8406be | pbrook | s->scntl1 &= ~LSI_SCNTL1_IARB; |
942 | 7d8406be | pbrook | if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
|
943 | 7d8406be | pbrook | DPRINTF("Selected absent target %d\n", id);
|
944 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
|
945 | 7d8406be | pbrook | lsi_disconnect(s); |
946 | 7d8406be | pbrook | break;
|
947 | 7d8406be | pbrook | } |
948 | 7d8406be | pbrook | DPRINTF("Selected target %d%s\n",
|
949 | 7d8406be | pbrook | id, insn & (1 << 3) ? " ATN" : ""); |
950 | 7d8406be | pbrook | /* ??? Linux drivers compain when this is set. Maybe
|
951 | 7d8406be | pbrook | it only applies in low-level mode (unimplemented).
|
952 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
|
953 | 7d8406be | pbrook | s->current_dev = s->scsi_dev[id]; |
954 | a917d384 | pbrook | s->current_tag = id << 8;
|
955 | 7d8406be | pbrook | s->scntl1 |= LSI_SCNTL1_CON; |
956 | 7d8406be | pbrook | if (insn & (1 << 3)) { |
957 | 7d8406be | pbrook | s->socl |= LSI_SOCL_ATN; |
958 | 7d8406be | pbrook | } |
959 | 7d8406be | pbrook | lsi_set_phase(s, PHASE_MO); |
960 | 7d8406be | pbrook | break;
|
961 | 7d8406be | pbrook | case 1: /* Disconnect */ |
962 | 7d8406be | pbrook | DPRINTF("Wait Disconect\n");
|
963 | 7d8406be | pbrook | s->scntl1 &= ~LSI_SCNTL1_CON; |
964 | 7d8406be | pbrook | break;
|
965 | 7d8406be | pbrook | case 2: /* Wait Reselect */ |
966 | a917d384 | pbrook | lsi_wait_reselect(s); |
967 | 7d8406be | pbrook | break;
|
968 | 7d8406be | pbrook | case 3: /* Set */ |
969 | 7d8406be | pbrook | DPRINTF("Set%s%s%s%s\n",
|
970 | 7d8406be | pbrook | insn & (1 << 3) ? " ATN" : "", |
971 | 7d8406be | pbrook | insn & (1 << 6) ? " ACK" : "", |
972 | 7d8406be | pbrook | insn & (1 << 9) ? " TM" : "", |
973 | 7d8406be | pbrook | insn & (1 << 10) ? " CC" : ""); |
974 | 7d8406be | pbrook | if (insn & (1 << 3)) { |
975 | 7d8406be | pbrook | s->socl |= LSI_SOCL_ATN; |
976 | 7d8406be | pbrook | lsi_set_phase(s, PHASE_MO); |
977 | 7d8406be | pbrook | } |
978 | 7d8406be | pbrook | if (insn & (1 << 9)) { |
979 | 7d8406be | pbrook | BADF("Target mode not implemented\n");
|
980 | 7d8406be | pbrook | exit(1);
|
981 | 7d8406be | pbrook | } |
982 | 7d8406be | pbrook | if (insn & (1 << 10)) |
983 | 7d8406be | pbrook | s->carry = 1;
|
984 | 7d8406be | pbrook | break;
|
985 | 7d8406be | pbrook | case 4: /* Clear */ |
986 | 7d8406be | pbrook | DPRINTF("Clear%s%s%s%s\n",
|
987 | 7d8406be | pbrook | insn & (1 << 3) ? " ATN" : "", |
988 | 7d8406be | pbrook | insn & (1 << 6) ? " ACK" : "", |
989 | 7d8406be | pbrook | insn & (1 << 9) ? " TM" : "", |
990 | 7d8406be | pbrook | insn & (1 << 10) ? " CC" : ""); |
991 | 7d8406be | pbrook | if (insn & (1 << 3)) { |
992 | 7d8406be | pbrook | s->socl &= ~LSI_SOCL_ATN; |
993 | 7d8406be | pbrook | } |
994 | 7d8406be | pbrook | if (insn & (1 << 10)) |
995 | 7d8406be | pbrook | s->carry = 0;
|
996 | 7d8406be | pbrook | break;
|
997 | 7d8406be | pbrook | } |
998 | 7d8406be | pbrook | } else {
|
999 | 7d8406be | pbrook | uint8_t op0; |
1000 | 7d8406be | pbrook | uint8_t op1; |
1001 | 7d8406be | pbrook | uint8_t data8; |
1002 | 7d8406be | pbrook | int reg;
|
1003 | 7d8406be | pbrook | int operator;
|
1004 | 7d8406be | pbrook | #ifdef DEBUG_LSI
|
1005 | 7d8406be | pbrook | static const char *opcode_names[3] = |
1006 | 7d8406be | pbrook | {"Write", "Read", "Read-Modify-Write"}; |
1007 | 7d8406be | pbrook | static const char *operator_names[8] = |
1008 | 7d8406be | pbrook | {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"}; |
1009 | 7d8406be | pbrook | #endif
|
1010 | 7d8406be | pbrook | |
1011 | 7d8406be | pbrook | reg = ((insn >> 16) & 0x7f) | (insn & 0x80); |
1012 | 7d8406be | pbrook | data8 = (insn >> 8) & 0xff; |
1013 | 7d8406be | pbrook | opcode = (insn >> 27) & 7; |
1014 | 7d8406be | pbrook | operator = (insn >> 24) & 7; |
1015 | a917d384 | pbrook | DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
|
1016 | 7d8406be | pbrook | opcode_names[opcode - 5], reg,
|
1017 | a917d384 | pbrook | operator_names[operator], data8, s->sfbr, |
1018 | 7d8406be | pbrook | (insn & (1 << 23)) ? " SFBR" : ""); |
1019 | 7d8406be | pbrook | op0 = op1 = 0;
|
1020 | 7d8406be | pbrook | switch (opcode) {
|
1021 | 7d8406be | pbrook | case 5: /* From SFBR */ |
1022 | 7d8406be | pbrook | op0 = s->sfbr; |
1023 | 7d8406be | pbrook | op1 = data8; |
1024 | 7d8406be | pbrook | break;
|
1025 | 7d8406be | pbrook | case 6: /* To SFBR */ |
1026 | 7d8406be | pbrook | if (operator)
|
1027 | 7d8406be | pbrook | op0 = lsi_reg_readb(s, reg); |
1028 | 7d8406be | pbrook | op1 = data8; |
1029 | 7d8406be | pbrook | break;
|
1030 | 7d8406be | pbrook | case 7: /* Read-modify-write */ |
1031 | 7d8406be | pbrook | if (operator)
|
1032 | 7d8406be | pbrook | op0 = lsi_reg_readb(s, reg); |
1033 | 7d8406be | pbrook | if (insn & (1 << 23)) { |
1034 | 7d8406be | pbrook | op1 = s->sfbr; |
1035 | 7d8406be | pbrook | } else {
|
1036 | 7d8406be | pbrook | op1 = data8; |
1037 | 7d8406be | pbrook | } |
1038 | 7d8406be | pbrook | break;
|
1039 | 7d8406be | pbrook | } |
1040 | 7d8406be | pbrook | |
1041 | 7d8406be | pbrook | switch (operator) {
|
1042 | 7d8406be | pbrook | case 0: /* move */ |
1043 | 7d8406be | pbrook | op0 = op1; |
1044 | 7d8406be | pbrook | break;
|
1045 | 7d8406be | pbrook | case 1: /* Shift left */ |
1046 | 7d8406be | pbrook | op1 = op0 >> 7;
|
1047 | 7d8406be | pbrook | op0 = (op0 << 1) | s->carry;
|
1048 | 7d8406be | pbrook | s->carry = op1; |
1049 | 7d8406be | pbrook | break;
|
1050 | 7d8406be | pbrook | case 2: /* OR */ |
1051 | 7d8406be | pbrook | op0 |= op1; |
1052 | 7d8406be | pbrook | break;
|
1053 | 7d8406be | pbrook | case 3: /* XOR */ |
1054 | dcfb9014 | ths | op0 ^= op1; |
1055 | 7d8406be | pbrook | break;
|
1056 | 7d8406be | pbrook | case 4: /* AND */ |
1057 | 7d8406be | pbrook | op0 &= op1; |
1058 | 7d8406be | pbrook | break;
|
1059 | 7d8406be | pbrook | case 5: /* SHR */ |
1060 | 7d8406be | pbrook | op1 = op0 & 1;
|
1061 | 7d8406be | pbrook | op0 = (op0 >> 1) | (s->carry << 7); |
1062 | 687fa640 | ths | s->carry = op1; |
1063 | 7d8406be | pbrook | break;
|
1064 | 7d8406be | pbrook | case 6: /* ADD */ |
1065 | 7d8406be | pbrook | op0 += op1; |
1066 | 7d8406be | pbrook | s->carry = op0 < op1; |
1067 | 7d8406be | pbrook | break;
|
1068 | 7d8406be | pbrook | case 7: /* ADC */ |
1069 | 7d8406be | pbrook | op0 += op1 + s->carry; |
1070 | 7d8406be | pbrook | if (s->carry)
|
1071 | 7d8406be | pbrook | s->carry = op0 <= op1; |
1072 | 7d8406be | pbrook | else
|
1073 | 7d8406be | pbrook | s->carry = op0 < op1; |
1074 | 7d8406be | pbrook | break;
|
1075 | 7d8406be | pbrook | } |
1076 | 7d8406be | pbrook | |
1077 | 7d8406be | pbrook | switch (opcode) {
|
1078 | 7d8406be | pbrook | case 5: /* From SFBR */ |
1079 | 7d8406be | pbrook | case 7: /* Read-modify-write */ |
1080 | 7d8406be | pbrook | lsi_reg_writeb(s, reg, op0); |
1081 | 7d8406be | pbrook | break;
|
1082 | 7d8406be | pbrook | case 6: /* To SFBR */ |
1083 | 7d8406be | pbrook | s->sfbr = op0; |
1084 | 7d8406be | pbrook | break;
|
1085 | 7d8406be | pbrook | } |
1086 | 7d8406be | pbrook | } |
1087 | 7d8406be | pbrook | break;
|
1088 | 7d8406be | pbrook | |
1089 | 7d8406be | pbrook | case 2: /* Transfer Control. */ |
1090 | 7d8406be | pbrook | { |
1091 | 7d8406be | pbrook | int cond;
|
1092 | 7d8406be | pbrook | int jmp;
|
1093 | 7d8406be | pbrook | |
1094 | 7d8406be | pbrook | if ((insn & 0x002e0000) == 0) { |
1095 | 7d8406be | pbrook | DPRINTF("NOP\n");
|
1096 | 7d8406be | pbrook | break;
|
1097 | 7d8406be | pbrook | } |
1098 | 7d8406be | pbrook | if (s->sist1 & LSI_SIST1_STO) {
|
1099 | 7d8406be | pbrook | DPRINTF("Delayed select timeout\n");
|
1100 | 7d8406be | pbrook | lsi_stop_script(s); |
1101 | 7d8406be | pbrook | break;
|
1102 | 7d8406be | pbrook | } |
1103 | 7d8406be | pbrook | cond = jmp = (insn & (1 << 19)) != 0; |
1104 | 7d8406be | pbrook | if (cond == jmp && (insn & (1 << 21))) { |
1105 | 7d8406be | pbrook | DPRINTF("Compare carry %d\n", s->carry == jmp);
|
1106 | 7d8406be | pbrook | cond = s->carry != 0;
|
1107 | 7d8406be | pbrook | } |
1108 | 7d8406be | pbrook | if (cond == jmp && (insn & (1 << 17))) { |
1109 | 7d8406be | pbrook | DPRINTF("Compare phase %d %c= %d\n",
|
1110 | 7d8406be | pbrook | (s->sstat1 & PHASE_MASK), |
1111 | 7d8406be | pbrook | jmp ? '=' : '!', |
1112 | 7d8406be | pbrook | ((insn >> 24) & 7)); |
1113 | 7d8406be | pbrook | cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7); |
1114 | 7d8406be | pbrook | } |
1115 | 7d8406be | pbrook | if (cond == jmp && (insn & (1 << 18))) { |
1116 | 7d8406be | pbrook | uint8_t mask; |
1117 | 7d8406be | pbrook | |
1118 | 7d8406be | pbrook | mask = (~insn >> 8) & 0xff; |
1119 | 7d8406be | pbrook | DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
|
1120 | 7d8406be | pbrook | s->sfbr, mask, jmp ? '=' : '!', insn & mask); |
1121 | 7d8406be | pbrook | cond = (s->sfbr & mask) == (insn & mask); |
1122 | 7d8406be | pbrook | } |
1123 | 7d8406be | pbrook | if (cond == jmp) {
|
1124 | 7d8406be | pbrook | if (insn & (1 << 23)) { |
1125 | 7d8406be | pbrook | /* Relative address. */
|
1126 | 7d8406be | pbrook | addr = s->dsp + sxt24(addr); |
1127 | 7d8406be | pbrook | } |
1128 | 7d8406be | pbrook | switch ((insn >> 27) & 7) { |
1129 | 7d8406be | pbrook | case 0: /* Jump */ |
1130 | 7d8406be | pbrook | DPRINTF("Jump to 0x%08x\n", addr);
|
1131 | 7d8406be | pbrook | s->dsp = addr; |
1132 | 7d8406be | pbrook | break;
|
1133 | 7d8406be | pbrook | case 1: /* Call */ |
1134 | 7d8406be | pbrook | DPRINTF("Call 0x%08x\n", addr);
|
1135 | 7d8406be | pbrook | s->temp = s->dsp; |
1136 | 7d8406be | pbrook | s->dsp = addr; |
1137 | 7d8406be | pbrook | break;
|
1138 | 7d8406be | pbrook | case 2: /* Return */ |
1139 | 7d8406be | pbrook | DPRINTF("Return to 0x%08x\n", s->temp);
|
1140 | 7d8406be | pbrook | s->dsp = s->temp; |
1141 | 7d8406be | pbrook | break;
|
1142 | 7d8406be | pbrook | case 3: /* Interrupt */ |
1143 | 7d8406be | pbrook | DPRINTF("Interrupt 0x%08x\n", s->dsps);
|
1144 | 7d8406be | pbrook | if ((insn & (1 << 20)) != 0) { |
1145 | 7d8406be | pbrook | s->istat0 |= LSI_ISTAT0_INTF; |
1146 | 7d8406be | pbrook | lsi_update_irq(s); |
1147 | 7d8406be | pbrook | } else {
|
1148 | 7d8406be | pbrook | lsi_script_dma_interrupt(s, LSI_DSTAT_SIR); |
1149 | 7d8406be | pbrook | } |
1150 | 7d8406be | pbrook | break;
|
1151 | 7d8406be | pbrook | default:
|
1152 | 7d8406be | pbrook | DPRINTF("Illegal transfer control\n");
|
1153 | 7d8406be | pbrook | lsi_script_dma_interrupt(s, LSI_DSTAT_IID); |
1154 | 7d8406be | pbrook | break;
|
1155 | 7d8406be | pbrook | } |
1156 | 7d8406be | pbrook | } else {
|
1157 | 7d8406be | pbrook | DPRINTF("Control condition failed\n");
|
1158 | 7d8406be | pbrook | } |
1159 | 7d8406be | pbrook | } |
1160 | 7d8406be | pbrook | break;
|
1161 | 7d8406be | pbrook | |
1162 | 7d8406be | pbrook | case 3: |
1163 | 7d8406be | pbrook | if ((insn & (1 << 29)) == 0) { |
1164 | 7d8406be | pbrook | /* Memory move. */
|
1165 | 7d8406be | pbrook | uint32_t dest; |
1166 | 7d8406be | pbrook | /* ??? The docs imply the destination address is loaded into
|
1167 | 7d8406be | pbrook | the TEMP register. However the Linux drivers rely on
|
1168 | 7d8406be | pbrook | the value being presrved. */
|
1169 | 7d8406be | pbrook | dest = read_dword(s, s->dsp); |
1170 | 7d8406be | pbrook | s->dsp += 4;
|
1171 | 7d8406be | pbrook | lsi_memcpy(s, dest, addr, insn & 0xffffff);
|
1172 | 7d8406be | pbrook | } else {
|
1173 | 7d8406be | pbrook | uint8_t data[7];
|
1174 | 7d8406be | pbrook | int reg;
|
1175 | 7d8406be | pbrook | int n;
|
1176 | 7d8406be | pbrook | int i;
|
1177 | 7d8406be | pbrook | |
1178 | 7d8406be | pbrook | if (insn & (1 << 28)) { |
1179 | 7d8406be | pbrook | addr = s->dsa + sxt24(addr); |
1180 | 7d8406be | pbrook | } |
1181 | 7d8406be | pbrook | n = (insn & 7);
|
1182 | 7d8406be | pbrook | reg = (insn >> 16) & 0xff; |
1183 | 7d8406be | pbrook | if (insn & (1 << 24)) { |
1184 | 7d8406be | pbrook | cpu_physical_memory_read(addr, data, n); |
1185 | a917d384 | pbrook | DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
|
1186 | a917d384 | pbrook | addr, *(int *)data);
|
1187 | 7d8406be | pbrook | for (i = 0; i < n; i++) { |
1188 | 7d8406be | pbrook | lsi_reg_writeb(s, reg + i, data[i]); |
1189 | 7d8406be | pbrook | } |
1190 | 7d8406be | pbrook | } else {
|
1191 | 7d8406be | pbrook | DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
|
1192 | 7d8406be | pbrook | for (i = 0; i < n; i++) { |
1193 | 7d8406be | pbrook | data[i] = lsi_reg_readb(s, reg + i); |
1194 | 7d8406be | pbrook | } |
1195 | 7d8406be | pbrook | cpu_physical_memory_write(addr, data, n); |
1196 | 7d8406be | pbrook | } |
1197 | 7d8406be | pbrook | } |
1198 | 7d8406be | pbrook | } |
1199 | 7d8406be | pbrook | /* ??? Need to avoid infinite loops. */
|
1200 | 7d8406be | pbrook | if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
|
1201 | 7d8406be | pbrook | if (s->dcntl & LSI_DCNTL_SSM) {
|
1202 | 7d8406be | pbrook | lsi_script_dma_interrupt(s, LSI_DSTAT_SSI); |
1203 | 7d8406be | pbrook | } else {
|
1204 | 7d8406be | pbrook | goto again;
|
1205 | 7d8406be | pbrook | } |
1206 | 7d8406be | pbrook | } |
1207 | 7d8406be | pbrook | DPRINTF("SCRIPTS execution stopped\n");
|
1208 | 7d8406be | pbrook | } |
1209 | 7d8406be | pbrook | |
1210 | 7d8406be | pbrook | static uint8_t lsi_reg_readb(LSIState *s, int offset) |
1211 | 7d8406be | pbrook | { |
1212 | 7d8406be | pbrook | uint8_t tmp; |
1213 | 7d8406be | pbrook | #define CASE_GET_REG32(name, addr) \
|
1214 | 7d8406be | pbrook | case addr: return s->name & 0xff; \ |
1215 | 7d8406be | pbrook | case addr + 1: return (s->name >> 8) & 0xff; \ |
1216 | 7d8406be | pbrook | case addr + 2: return (s->name >> 16) & 0xff; \ |
1217 | 7d8406be | pbrook | case addr + 3: return (s->name >> 24) & 0xff; |
1218 | 7d8406be | pbrook | |
1219 | 7d8406be | pbrook | #ifdef DEBUG_LSI_REG
|
1220 | 7d8406be | pbrook | DPRINTF("Read reg %x\n", offset);
|
1221 | 7d8406be | pbrook | #endif
|
1222 | 7d8406be | pbrook | switch (offset) {
|
1223 | 7d8406be | pbrook | case 0x00: /* SCNTL0 */ |
1224 | 7d8406be | pbrook | return s->scntl0;
|
1225 | 7d8406be | pbrook | case 0x01: /* SCNTL1 */ |
1226 | 7d8406be | pbrook | return s->scntl1;
|
1227 | 7d8406be | pbrook | case 0x02: /* SCNTL2 */ |
1228 | 7d8406be | pbrook | return s->scntl2;
|
1229 | 7d8406be | pbrook | case 0x03: /* SCNTL3 */ |
1230 | 7d8406be | pbrook | return s->scntl3;
|
1231 | 7d8406be | pbrook | case 0x04: /* SCID */ |
1232 | 7d8406be | pbrook | return s->scid;
|
1233 | 7d8406be | pbrook | case 0x05: /* SXFER */ |
1234 | 7d8406be | pbrook | return s->sxfer;
|
1235 | 7d8406be | pbrook | case 0x06: /* SDID */ |
1236 | 7d8406be | pbrook | return s->sdid;
|
1237 | 7d8406be | pbrook | case 0x07: /* GPREG0 */ |
1238 | 7d8406be | pbrook | return 0x7f; |
1239 | 985a03b0 | ths | case 0x08: /* Revision ID */ |
1240 | 985a03b0 | ths | return 0x00; |
1241 | a917d384 | pbrook | case 0xa: /* SSID */ |
1242 | a917d384 | pbrook | return s->ssid;
|
1243 | 7d8406be | pbrook | case 0xb: /* SBCL */ |
1244 | 7d8406be | pbrook | /* ??? This is not correct. However it's (hopefully) only
|
1245 | 7d8406be | pbrook | used for diagnostics, so should be ok. */
|
1246 | 7d8406be | pbrook | return 0; |
1247 | 7d8406be | pbrook | case 0xc: /* DSTAT */ |
1248 | 7d8406be | pbrook | tmp = s->dstat | 0x80;
|
1249 | 7d8406be | pbrook | if ((s->istat0 & LSI_ISTAT0_INTF) == 0) |
1250 | 7d8406be | pbrook | s->dstat = 0;
|
1251 | 7d8406be | pbrook | lsi_update_irq(s); |
1252 | 7d8406be | pbrook | return tmp;
|
1253 | 7d8406be | pbrook | case 0x0d: /* SSTAT0 */ |
1254 | 7d8406be | pbrook | return s->sstat0;
|
1255 | 7d8406be | pbrook | case 0x0e: /* SSTAT1 */ |
1256 | 7d8406be | pbrook | return s->sstat1;
|
1257 | 7d8406be | pbrook | case 0x0f: /* SSTAT2 */ |
1258 | 7d8406be | pbrook | return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2; |
1259 | 7d8406be | pbrook | CASE_GET_REG32(dsa, 0x10)
|
1260 | 7d8406be | pbrook | case 0x14: /* ISTAT0 */ |
1261 | 7d8406be | pbrook | return s->istat0;
|
1262 | 7d8406be | pbrook | case 0x16: /* MBOX0 */ |
1263 | 7d8406be | pbrook | return s->mbox0;
|
1264 | 7d8406be | pbrook | case 0x17: /* MBOX1 */ |
1265 | 7d8406be | pbrook | return s->mbox1;
|
1266 | 7d8406be | pbrook | case 0x18: /* CTEST0 */ |
1267 | 7d8406be | pbrook | return 0xff; |
1268 | 7d8406be | pbrook | case 0x19: /* CTEST1 */ |
1269 | 7d8406be | pbrook | return 0; |
1270 | 7d8406be | pbrook | case 0x1a: /* CTEST2 */ |
1271 | 7d8406be | pbrook | tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM; |
1272 | 7d8406be | pbrook | if (s->istat0 & LSI_ISTAT0_SIGP) {
|
1273 | 7d8406be | pbrook | s->istat0 &= ~LSI_ISTAT0_SIGP; |
1274 | 7d8406be | pbrook | tmp |= LSI_CTEST2_SIGP; |
1275 | 7d8406be | pbrook | } |
1276 | 7d8406be | pbrook | return tmp;
|
1277 | 7d8406be | pbrook | case 0x1b: /* CTEST3 */ |
1278 | 7d8406be | pbrook | return s->ctest3;
|
1279 | 7d8406be | pbrook | CASE_GET_REG32(temp, 0x1c)
|
1280 | 7d8406be | pbrook | case 0x20: /* DFIFO */ |
1281 | 7d8406be | pbrook | return 0; |
1282 | 7d8406be | pbrook | case 0x21: /* CTEST4 */ |
1283 | 7d8406be | pbrook | return s->ctest4;
|
1284 | 7d8406be | pbrook | case 0x22: /* CTEST5 */ |
1285 | 7d8406be | pbrook | return s->ctest5;
|
1286 | 985a03b0 | ths | case 0x23: /* CTEST6 */ |
1287 | 985a03b0 | ths | return 0; |
1288 | 7d8406be | pbrook | case 0x24: /* DBC[0:7] */ |
1289 | 7d8406be | pbrook | return s->dbc & 0xff; |
1290 | 7d8406be | pbrook | case 0x25: /* DBC[8:15] */ |
1291 | 7d8406be | pbrook | return (s->dbc >> 8) & 0xff; |
1292 | 7d8406be | pbrook | case 0x26: /* DBC[16->23] */ |
1293 | 7d8406be | pbrook | return (s->dbc >> 16) & 0xff; |
1294 | 7d8406be | pbrook | case 0x27: /* DCMD */ |
1295 | 7d8406be | pbrook | return s->dcmd;
|
1296 | 7d8406be | pbrook | CASE_GET_REG32(dsp, 0x2c)
|
1297 | 7d8406be | pbrook | CASE_GET_REG32(dsps, 0x30)
|
1298 | 7d8406be | pbrook | CASE_GET_REG32(scratch[0], 0x34) |
1299 | 7d8406be | pbrook | case 0x38: /* DMODE */ |
1300 | 7d8406be | pbrook | return s->dmode;
|
1301 | 7d8406be | pbrook | case 0x39: /* DIEN */ |
1302 | 7d8406be | pbrook | return s->dien;
|
1303 | 7d8406be | pbrook | case 0x3b: /* DCNTL */ |
1304 | 7d8406be | pbrook | return s->dcntl;
|
1305 | 7d8406be | pbrook | case 0x40: /* SIEN0 */ |
1306 | 7d8406be | pbrook | return s->sien0;
|
1307 | 7d8406be | pbrook | case 0x41: /* SIEN1 */ |
1308 | 7d8406be | pbrook | return s->sien1;
|
1309 | 7d8406be | pbrook | case 0x42: /* SIST0 */ |
1310 | 7d8406be | pbrook | tmp = s->sist0; |
1311 | 7d8406be | pbrook | s->sist0 = 0;
|
1312 | 7d8406be | pbrook | lsi_update_irq(s); |
1313 | 7d8406be | pbrook | return tmp;
|
1314 | 7d8406be | pbrook | case 0x43: /* SIST1 */ |
1315 | 7d8406be | pbrook | tmp = s->sist1; |
1316 | 7d8406be | pbrook | s->sist1 = 0;
|
1317 | 7d8406be | pbrook | lsi_update_irq(s); |
1318 | 7d8406be | pbrook | return tmp;
|
1319 | 7d8406be | pbrook | case 0x47: /* GPCNTL0 */ |
1320 | 7d8406be | pbrook | return 0x0f; |
1321 | 7d8406be | pbrook | case 0x48: /* STIME0 */ |
1322 | 7d8406be | pbrook | return s->stime0;
|
1323 | 7d8406be | pbrook | case 0x4a: /* RESPID0 */ |
1324 | 7d8406be | pbrook | return s->respid0;
|
1325 | 7d8406be | pbrook | case 0x4b: /* RESPID1 */ |
1326 | 7d8406be | pbrook | return s->respid1;
|
1327 | 7d8406be | pbrook | case 0x4d: /* STEST1 */ |
1328 | 7d8406be | pbrook | return s->stest1;
|
1329 | 7d8406be | pbrook | case 0x4e: /* STEST2 */ |
1330 | 7d8406be | pbrook | return s->stest2;
|
1331 | 7d8406be | pbrook | case 0x4f: /* STEST3 */ |
1332 | 7d8406be | pbrook | return s->stest3;
|
1333 | a917d384 | pbrook | case 0x50: /* SIDL */ |
1334 | a917d384 | pbrook | /* This is needed by the linux drivers. We currently only update it
|
1335 | a917d384 | pbrook | during the MSG IN phase. */
|
1336 | a917d384 | pbrook | return s->sidl;
|
1337 | 7d8406be | pbrook | case 0x52: /* STEST4 */ |
1338 | 7d8406be | pbrook | return 0xe0; |
1339 | 7d8406be | pbrook | case 0x56: /* CCNTL0 */ |
1340 | 7d8406be | pbrook | return s->ccntl0;
|
1341 | 7d8406be | pbrook | case 0x57: /* CCNTL1 */ |
1342 | 7d8406be | pbrook | return s->ccntl1;
|
1343 | a917d384 | pbrook | case 0x58: /* SBDL */ |
1344 | a917d384 | pbrook | /* Some drivers peek at the data bus during the MSG IN phase. */
|
1345 | a917d384 | pbrook | if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
|
1346 | a917d384 | pbrook | return s->msg[0]; |
1347 | a917d384 | pbrook | return 0; |
1348 | a917d384 | pbrook | case 0x59: /* SBDL high */ |
1349 | 7d8406be | pbrook | return 0; |
1350 | 7d8406be | pbrook | CASE_GET_REG32(mmrs, 0xa0)
|
1351 | 7d8406be | pbrook | CASE_GET_REG32(mmws, 0xa4)
|
1352 | 7d8406be | pbrook | CASE_GET_REG32(sfs, 0xa8)
|
1353 | 7d8406be | pbrook | CASE_GET_REG32(drs, 0xac)
|
1354 | 7d8406be | pbrook | CASE_GET_REG32(sbms, 0xb0)
|
1355 | 7d8406be | pbrook | CASE_GET_REG32(dmbs, 0xb4)
|
1356 | 7d8406be | pbrook | CASE_GET_REG32(dnad64, 0xb8)
|
1357 | 7d8406be | pbrook | CASE_GET_REG32(pmjad1, 0xc0)
|
1358 | 7d8406be | pbrook | CASE_GET_REG32(pmjad2, 0xc4)
|
1359 | 7d8406be | pbrook | CASE_GET_REG32(rbc, 0xc8)
|
1360 | 7d8406be | pbrook | CASE_GET_REG32(ua, 0xcc)
|
1361 | 7d8406be | pbrook | CASE_GET_REG32(ia, 0xd4)
|
1362 | 7d8406be | pbrook | CASE_GET_REG32(sbc, 0xd8)
|
1363 | 7d8406be | pbrook | CASE_GET_REG32(csbc, 0xdc)
|
1364 | 7d8406be | pbrook | } |
1365 | 7d8406be | pbrook | if (offset >= 0x5c && offset < 0xa0) { |
1366 | 7d8406be | pbrook | int n;
|
1367 | 7d8406be | pbrook | int shift;
|
1368 | 7d8406be | pbrook | n = (offset - 0x58) >> 2; |
1369 | 7d8406be | pbrook | shift = (offset & 3) * 8; |
1370 | 7d8406be | pbrook | return (s->scratch[n] >> shift) & 0xff; |
1371 | 7d8406be | pbrook | } |
1372 | 7d8406be | pbrook | BADF("readb 0x%x\n", offset);
|
1373 | 7d8406be | pbrook | exit(1);
|
1374 | 7d8406be | pbrook | #undef CASE_GET_REG32
|
1375 | 7d8406be | pbrook | } |
1376 | 7d8406be | pbrook | |
1377 | 7d8406be | pbrook | static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) |
1378 | 7d8406be | pbrook | { |
1379 | 7d8406be | pbrook | #define CASE_SET_REG32(name, addr) \
|
1380 | 7d8406be | pbrook | case addr : s->name &= 0xffffff00; s->name |= val; break; \ |
1381 | 7d8406be | pbrook | case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \ |
1382 | 7d8406be | pbrook | case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \ |
1383 | 7d8406be | pbrook | case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break; |
1384 | 7d8406be | pbrook | |
1385 | 7d8406be | pbrook | #ifdef DEBUG_LSI_REG
|
1386 | 7d8406be | pbrook | DPRINTF("Write reg %x = %02x\n", offset, val);
|
1387 | 7d8406be | pbrook | #endif
|
1388 | 7d8406be | pbrook | switch (offset) {
|
1389 | 7d8406be | pbrook | case 0x00: /* SCNTL0 */ |
1390 | 7d8406be | pbrook | s->scntl0 = val; |
1391 | 7d8406be | pbrook | if (val & LSI_SCNTL0_START) {
|
1392 | 7d8406be | pbrook | BADF("Start sequence not implemented\n");
|
1393 | 7d8406be | pbrook | } |
1394 | 7d8406be | pbrook | break;
|
1395 | 7d8406be | pbrook | case 0x01: /* SCNTL1 */ |
1396 | 7d8406be | pbrook | s->scntl1 = val & ~LSI_SCNTL1_SST; |
1397 | 7d8406be | pbrook | if (val & LSI_SCNTL1_IARB) {
|
1398 | 7d8406be | pbrook | BADF("Immediate Arbritration not implemented\n");
|
1399 | 7d8406be | pbrook | } |
1400 | 7d8406be | pbrook | if (val & LSI_SCNTL1_RST) {
|
1401 | 7d8406be | pbrook | s->sstat0 |= LSI_SSTAT0_RST; |
1402 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
|
1403 | 7d8406be | pbrook | } else {
|
1404 | 7d8406be | pbrook | s->sstat0 &= ~LSI_SSTAT0_RST; |
1405 | 7d8406be | pbrook | } |
1406 | 7d8406be | pbrook | break;
|
1407 | 7d8406be | pbrook | case 0x02: /* SCNTL2 */ |
1408 | 7d8406be | pbrook | val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS); |
1409 | 3d834c78 | ths | s->scntl2 = val; |
1410 | 7d8406be | pbrook | break;
|
1411 | 7d8406be | pbrook | case 0x03: /* SCNTL3 */ |
1412 | 7d8406be | pbrook | s->scntl3 = val; |
1413 | 7d8406be | pbrook | break;
|
1414 | 7d8406be | pbrook | case 0x04: /* SCID */ |
1415 | 7d8406be | pbrook | s->scid = val; |
1416 | 7d8406be | pbrook | break;
|
1417 | 7d8406be | pbrook | case 0x05: /* SXFER */ |
1418 | 7d8406be | pbrook | s->sxfer = val; |
1419 | 7d8406be | pbrook | break;
|
1420 | a917d384 | pbrook | case 0x06: /* SDID */ |
1421 | a917d384 | pbrook | if ((val & 0xf) != (s->ssid & 0xf)) |
1422 | a917d384 | pbrook | BADF("Destination ID does not match SSID\n");
|
1423 | a917d384 | pbrook | s->sdid = val & 0xf;
|
1424 | a917d384 | pbrook | break;
|
1425 | 7d8406be | pbrook | case 0x07: /* GPREG0 */ |
1426 | 7d8406be | pbrook | break;
|
1427 | a917d384 | pbrook | case 0x08: /* SFBR */ |
1428 | a917d384 | pbrook | /* The CPU is not allowed to write to this register. However the
|
1429 | a917d384 | pbrook | SCRIPTS register move instructions are. */
|
1430 | a917d384 | pbrook | s->sfbr = val; |
1431 | a917d384 | pbrook | break;
|
1432 | 7d8406be | pbrook | case 0x0c: case 0x0d: case 0x0e: case 0x0f: |
1433 | 7d8406be | pbrook | /* Linux writes to these readonly registers on startup. */
|
1434 | 7d8406be | pbrook | return;
|
1435 | 7d8406be | pbrook | CASE_SET_REG32(dsa, 0x10)
|
1436 | 7d8406be | pbrook | case 0x14: /* ISTAT0 */ |
1437 | 7d8406be | pbrook | s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0); |
1438 | 7d8406be | pbrook | if (val & LSI_ISTAT0_ABRT) {
|
1439 | 7d8406be | pbrook | lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT); |
1440 | 7d8406be | pbrook | } |
1441 | 7d8406be | pbrook | if (val & LSI_ISTAT0_INTF) {
|
1442 | 7d8406be | pbrook | s->istat0 &= ~LSI_ISTAT0_INTF; |
1443 | 7d8406be | pbrook | lsi_update_irq(s); |
1444 | 7d8406be | pbrook | } |
1445 | 4d611c9a | pbrook | if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) { |
1446 | 7d8406be | pbrook | DPRINTF("Woken by SIGP\n");
|
1447 | 7d8406be | pbrook | s->waiting = 0;
|
1448 | 7d8406be | pbrook | s->dsp = s->dnad; |
1449 | 7d8406be | pbrook | lsi_execute_script(s); |
1450 | 7d8406be | pbrook | } |
1451 | 7d8406be | pbrook | if (val & LSI_ISTAT0_SRST) {
|
1452 | 7d8406be | pbrook | lsi_soft_reset(s); |
1453 | 7d8406be | pbrook | } |
1454 | 92d88ecb | ths | break;
|
1455 | 7d8406be | pbrook | case 0x16: /* MBOX0 */ |
1456 | 7d8406be | pbrook | s->mbox0 = val; |
1457 | 92d88ecb | ths | break;
|
1458 | 7d8406be | pbrook | case 0x17: /* MBOX1 */ |
1459 | 7d8406be | pbrook | s->mbox1 = val; |
1460 | 92d88ecb | ths | break;
|
1461 | 7d8406be | pbrook | case 0x1b: /* CTEST3 */ |
1462 | 7d8406be | pbrook | s->ctest3 = val & 0x0f;
|
1463 | 7d8406be | pbrook | break;
|
1464 | 7d8406be | pbrook | CASE_SET_REG32(temp, 0x1c)
|
1465 | 7d8406be | pbrook | case 0x21: /* CTEST4 */ |
1466 | 7d8406be | pbrook | if (val & 7) { |
1467 | 7d8406be | pbrook | BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
|
1468 | 7d8406be | pbrook | } |
1469 | 7d8406be | pbrook | s->ctest4 = val; |
1470 | 7d8406be | pbrook | break;
|
1471 | 7d8406be | pbrook | case 0x22: /* CTEST5 */ |
1472 | 7d8406be | pbrook | if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
|
1473 | 7d8406be | pbrook | BADF("CTEST5 DMA increment not implemented\n");
|
1474 | 7d8406be | pbrook | } |
1475 | 7d8406be | pbrook | s->ctest5 = val; |
1476 | 7d8406be | pbrook | break;
|
1477 | 3d834c78 | ths | case 0x2c: /* DSP[0:7] */ |
1478 | 7d8406be | pbrook | s->dsp &= 0xffffff00;
|
1479 | 7d8406be | pbrook | s->dsp |= val; |
1480 | 7d8406be | pbrook | break;
|
1481 | 3d834c78 | ths | case 0x2d: /* DSP[8:15] */ |
1482 | 7d8406be | pbrook | s->dsp &= 0xffff00ff;
|
1483 | 7d8406be | pbrook | s->dsp |= val << 8;
|
1484 | 7d8406be | pbrook | break;
|
1485 | 3d834c78 | ths | case 0x2e: /* DSP[16:23] */ |
1486 | 7d8406be | pbrook | s->dsp &= 0xff00ffff;
|
1487 | 7d8406be | pbrook | s->dsp |= val << 16;
|
1488 | 7d8406be | pbrook | break;
|
1489 | 3d834c78 | ths | case 0x2f: /* DSP[24:31] */ |
1490 | 7d8406be | pbrook | s->dsp &= 0x00ffffff;
|
1491 | 7d8406be | pbrook | s->dsp |= val << 24;
|
1492 | 7d8406be | pbrook | if ((s->dmode & LSI_DMODE_MAN) == 0 |
1493 | 7d8406be | pbrook | && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
|
1494 | 7d8406be | pbrook | lsi_execute_script(s); |
1495 | 7d8406be | pbrook | break;
|
1496 | 7d8406be | pbrook | CASE_SET_REG32(dsps, 0x30)
|
1497 | 7d8406be | pbrook | CASE_SET_REG32(scratch[0], 0x34) |
1498 | 7d8406be | pbrook | case 0x38: /* DMODE */ |
1499 | 7d8406be | pbrook | if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
|
1500 | 7d8406be | pbrook | BADF("IO mappings not implemented\n");
|
1501 | 7d8406be | pbrook | } |
1502 | 7d8406be | pbrook | s->dmode = val; |
1503 | 7d8406be | pbrook | break;
|
1504 | 7d8406be | pbrook | case 0x39: /* DIEN */ |
1505 | 7d8406be | pbrook | s->dien = val; |
1506 | 7d8406be | pbrook | lsi_update_irq(s); |
1507 | 7d8406be | pbrook | break;
|
1508 | 7d8406be | pbrook | case 0x3b: /* DCNTL */ |
1509 | 7d8406be | pbrook | s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD); |
1510 | 7d8406be | pbrook | if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0) |
1511 | 7d8406be | pbrook | lsi_execute_script(s); |
1512 | 7d8406be | pbrook | break;
|
1513 | 7d8406be | pbrook | case 0x40: /* SIEN0 */ |
1514 | 7d8406be | pbrook | s->sien0 = val; |
1515 | 7d8406be | pbrook | lsi_update_irq(s); |
1516 | 7d8406be | pbrook | break;
|
1517 | 7d8406be | pbrook | case 0x41: /* SIEN1 */ |
1518 | 7d8406be | pbrook | s->sien1 = val; |
1519 | 7d8406be | pbrook | lsi_update_irq(s); |
1520 | 7d8406be | pbrook | break;
|
1521 | 7d8406be | pbrook | case 0x47: /* GPCNTL0 */ |
1522 | 7d8406be | pbrook | break;
|
1523 | 7d8406be | pbrook | case 0x48: /* STIME0 */ |
1524 | 7d8406be | pbrook | s->stime0 = val; |
1525 | 7d8406be | pbrook | break;
|
1526 | 7d8406be | pbrook | case 0x49: /* STIME1 */ |
1527 | 7d8406be | pbrook | if (val & 0xf) { |
1528 | 7d8406be | pbrook | DPRINTF("General purpose timer not implemented\n");
|
1529 | 7d8406be | pbrook | /* ??? Raising the interrupt immediately seems to be sufficient
|
1530 | 7d8406be | pbrook | to keep the FreeBSD driver happy. */
|
1531 | 7d8406be | pbrook | lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
|
1532 | 7d8406be | pbrook | } |
1533 | 7d8406be | pbrook | break;
|
1534 | 7d8406be | pbrook | case 0x4a: /* RESPID0 */ |
1535 | 7d8406be | pbrook | s->respid0 = val; |
1536 | 7d8406be | pbrook | break;
|
1537 | 7d8406be | pbrook | case 0x4b: /* RESPID1 */ |
1538 | 7d8406be | pbrook | s->respid1 = val; |
1539 | 7d8406be | pbrook | break;
|
1540 | 7d8406be | pbrook | case 0x4d: /* STEST1 */ |
1541 | 7d8406be | pbrook | s->stest1 = val; |
1542 | 7d8406be | pbrook | break;
|
1543 | 7d8406be | pbrook | case 0x4e: /* STEST2 */ |
1544 | 7d8406be | pbrook | if (val & 1) { |
1545 | 7d8406be | pbrook | BADF("Low level mode not implemented\n");
|
1546 | 7d8406be | pbrook | } |
1547 | 7d8406be | pbrook | s->stest2 = val; |
1548 | 7d8406be | pbrook | break;
|
1549 | 7d8406be | pbrook | case 0x4f: /* STEST3 */ |
1550 | 7d8406be | pbrook | if (val & 0x41) { |
1551 | 7d8406be | pbrook | BADF("SCSI FIFO test mode not implemented\n");
|
1552 | 7d8406be | pbrook | } |
1553 | 7d8406be | pbrook | s->stest3 = val; |
1554 | 7d8406be | pbrook | break;
|
1555 | 7d8406be | pbrook | case 0x56: /* CCNTL0 */ |
1556 | 7d8406be | pbrook | s->ccntl0 = val; |
1557 | 7d8406be | pbrook | break;
|
1558 | 7d8406be | pbrook | case 0x57: /* CCNTL1 */ |
1559 | 7d8406be | pbrook | s->ccntl1 = val; |
1560 | 7d8406be | pbrook | break;
|
1561 | 7d8406be | pbrook | CASE_SET_REG32(mmrs, 0xa0)
|
1562 | 7d8406be | pbrook | CASE_SET_REG32(mmws, 0xa4)
|
1563 | 7d8406be | pbrook | CASE_SET_REG32(sfs, 0xa8)
|
1564 | 7d8406be | pbrook | CASE_SET_REG32(drs, 0xac)
|
1565 | 7d8406be | pbrook | CASE_SET_REG32(sbms, 0xb0)
|
1566 | 7d8406be | pbrook | CASE_SET_REG32(dmbs, 0xb4)
|
1567 | 7d8406be | pbrook | CASE_SET_REG32(dnad64, 0xb8)
|
1568 | 7d8406be | pbrook | CASE_SET_REG32(pmjad1, 0xc0)
|
1569 | 7d8406be | pbrook | CASE_SET_REG32(pmjad2, 0xc4)
|
1570 | 7d8406be | pbrook | CASE_SET_REG32(rbc, 0xc8)
|
1571 | 7d8406be | pbrook | CASE_SET_REG32(ua, 0xcc)
|
1572 | 7d8406be | pbrook | CASE_SET_REG32(ia, 0xd4)
|
1573 | 7d8406be | pbrook | CASE_SET_REG32(sbc, 0xd8)
|
1574 | 7d8406be | pbrook | CASE_SET_REG32(csbc, 0xdc)
|
1575 | 7d8406be | pbrook | default:
|
1576 | 7d8406be | pbrook | if (offset >= 0x5c && offset < 0xa0) { |
1577 | 7d8406be | pbrook | int n;
|
1578 | 7d8406be | pbrook | int shift;
|
1579 | 7d8406be | pbrook | n = (offset - 0x58) >> 2; |
1580 | 7d8406be | pbrook | shift = (offset & 3) * 8; |
1581 | 7d8406be | pbrook | s->scratch[n] &= ~(0xff << shift);
|
1582 | 7d8406be | pbrook | s->scratch[n] |= (val & 0xff) << shift;
|
1583 | 7d8406be | pbrook | } else {
|
1584 | 7d8406be | pbrook | BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
|
1585 | 7d8406be | pbrook | } |
1586 | 7d8406be | pbrook | } |
1587 | 7d8406be | pbrook | #undef CASE_SET_REG32
|
1588 | 7d8406be | pbrook | } |
1589 | 7d8406be | pbrook | |
1590 | 7d8406be | pbrook | static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1591 | 7d8406be | pbrook | { |
1592 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1593 | 7d8406be | pbrook | |
1594 | 7d8406be | pbrook | lsi_reg_writeb(s, addr & 0xff, val);
|
1595 | 7d8406be | pbrook | } |
1596 | 7d8406be | pbrook | |
1597 | 7d8406be | pbrook | static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1598 | 7d8406be | pbrook | { |
1599 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1600 | 7d8406be | pbrook | |
1601 | 7d8406be | pbrook | addr &= 0xff;
|
1602 | 7d8406be | pbrook | lsi_reg_writeb(s, addr, val & 0xff);
|
1603 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1604 | 7d8406be | pbrook | } |
1605 | 7d8406be | pbrook | |
1606 | 7d8406be | pbrook | static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1607 | 7d8406be | pbrook | { |
1608 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1609 | 7d8406be | pbrook | |
1610 | 7d8406be | pbrook | addr &= 0xff;
|
1611 | 7d8406be | pbrook | lsi_reg_writeb(s, addr, val & 0xff);
|
1612 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1613 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); |
1614 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); |
1615 | 7d8406be | pbrook | } |
1616 | 7d8406be | pbrook | |
1617 | 7d8406be | pbrook | static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr) |
1618 | 7d8406be | pbrook | { |
1619 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1620 | 7d8406be | pbrook | |
1621 | 7d8406be | pbrook | return lsi_reg_readb(s, addr & 0xff); |
1622 | 7d8406be | pbrook | } |
1623 | 7d8406be | pbrook | |
1624 | 7d8406be | pbrook | static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) |
1625 | 7d8406be | pbrook | { |
1626 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1627 | 7d8406be | pbrook | uint32_t val; |
1628 | 7d8406be | pbrook | |
1629 | 7d8406be | pbrook | addr &= 0xff;
|
1630 | 7d8406be | pbrook | val = lsi_reg_readb(s, addr); |
1631 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 1) << 8; |
1632 | 7d8406be | pbrook | return val;
|
1633 | 7d8406be | pbrook | } |
1634 | 7d8406be | pbrook | |
1635 | 7d8406be | pbrook | static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr) |
1636 | 7d8406be | pbrook | { |
1637 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1638 | 7d8406be | pbrook | uint32_t val; |
1639 | 7d8406be | pbrook | addr &= 0xff;
|
1640 | 7d8406be | pbrook | val = lsi_reg_readb(s, addr); |
1641 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 1) << 8; |
1642 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 2) << 16; |
1643 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 3) << 24; |
1644 | 7d8406be | pbrook | return val;
|
1645 | 7d8406be | pbrook | } |
1646 | 7d8406be | pbrook | |
1647 | 7d8406be | pbrook | static CPUReadMemoryFunc *lsi_mmio_readfn[3] = { |
1648 | 7d8406be | pbrook | lsi_mmio_readb, |
1649 | 7d8406be | pbrook | lsi_mmio_readw, |
1650 | 7d8406be | pbrook | lsi_mmio_readl, |
1651 | 7d8406be | pbrook | }; |
1652 | 7d8406be | pbrook | |
1653 | 7d8406be | pbrook | static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = { |
1654 | 7d8406be | pbrook | lsi_mmio_writeb, |
1655 | 7d8406be | pbrook | lsi_mmio_writew, |
1656 | 7d8406be | pbrook | lsi_mmio_writel, |
1657 | 7d8406be | pbrook | }; |
1658 | 7d8406be | pbrook | |
1659 | 7d8406be | pbrook | static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1660 | 7d8406be | pbrook | { |
1661 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1662 | 7d8406be | pbrook | uint32_t newval; |
1663 | 7d8406be | pbrook | int shift;
|
1664 | 7d8406be | pbrook | |
1665 | 7d8406be | pbrook | addr &= 0x1fff;
|
1666 | 7d8406be | pbrook | newval = s->script_ram[addr >> 2];
|
1667 | 7d8406be | pbrook | shift = (addr & 3) * 8; |
1668 | 7d8406be | pbrook | newval &= ~(0xff << shift);
|
1669 | 7d8406be | pbrook | newval |= val << shift; |
1670 | 7d8406be | pbrook | s->script_ram[addr >> 2] = newval;
|
1671 | 7d8406be | pbrook | } |
1672 | 7d8406be | pbrook | |
1673 | 7d8406be | pbrook | static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1674 | 7d8406be | pbrook | { |
1675 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1676 | 7d8406be | pbrook | uint32_t newval; |
1677 | 7d8406be | pbrook | |
1678 | 7d8406be | pbrook | addr &= 0x1fff;
|
1679 | 7d8406be | pbrook | newval = s->script_ram[addr >> 2];
|
1680 | 7d8406be | pbrook | if (addr & 2) { |
1681 | 7d8406be | pbrook | newval = (newval & 0xffff) | (val << 16); |
1682 | 7d8406be | pbrook | } else {
|
1683 | 7d8406be | pbrook | newval = (newval & 0xffff0000) | val;
|
1684 | 7d8406be | pbrook | } |
1685 | 7d8406be | pbrook | s->script_ram[addr >> 2] = newval;
|
1686 | 7d8406be | pbrook | } |
1687 | 7d8406be | pbrook | |
1688 | 7d8406be | pbrook | |
1689 | 7d8406be | pbrook | static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1690 | 7d8406be | pbrook | { |
1691 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1692 | 7d8406be | pbrook | |
1693 | 7d8406be | pbrook | addr &= 0x1fff;
|
1694 | 7d8406be | pbrook | s->script_ram[addr >> 2] = val;
|
1695 | 7d8406be | pbrook | } |
1696 | 7d8406be | pbrook | |
1697 | 7d8406be | pbrook | static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) |
1698 | 7d8406be | pbrook | { |
1699 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1700 | 7d8406be | pbrook | uint32_t val; |
1701 | 7d8406be | pbrook | |
1702 | 7d8406be | pbrook | addr &= 0x1fff;
|
1703 | 7d8406be | pbrook | val = s->script_ram[addr >> 2];
|
1704 | 7d8406be | pbrook | val >>= (addr & 3) * 8; |
1705 | 7d8406be | pbrook | return val & 0xff; |
1706 | 7d8406be | pbrook | } |
1707 | 7d8406be | pbrook | |
1708 | 7d8406be | pbrook | static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) |
1709 | 7d8406be | pbrook | { |
1710 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1711 | 7d8406be | pbrook | uint32_t val; |
1712 | 7d8406be | pbrook | |
1713 | 7d8406be | pbrook | addr &= 0x1fff;
|
1714 | 7d8406be | pbrook | val = s->script_ram[addr >> 2];
|
1715 | 7d8406be | pbrook | if (addr & 2) |
1716 | 7d8406be | pbrook | val >>= 16;
|
1717 | 7d8406be | pbrook | return le16_to_cpu(val);
|
1718 | 7d8406be | pbrook | } |
1719 | 7d8406be | pbrook | |
1720 | 7d8406be | pbrook | static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr) |
1721 | 7d8406be | pbrook | { |
1722 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1723 | 7d8406be | pbrook | |
1724 | 7d8406be | pbrook | addr &= 0x1fff;
|
1725 | 7d8406be | pbrook | return le32_to_cpu(s->script_ram[addr >> 2]); |
1726 | 7d8406be | pbrook | } |
1727 | 7d8406be | pbrook | |
1728 | 7d8406be | pbrook | static CPUReadMemoryFunc *lsi_ram_readfn[3] = { |
1729 | 7d8406be | pbrook | lsi_ram_readb, |
1730 | 7d8406be | pbrook | lsi_ram_readw, |
1731 | 7d8406be | pbrook | lsi_ram_readl, |
1732 | 7d8406be | pbrook | }; |
1733 | 7d8406be | pbrook | |
1734 | 7d8406be | pbrook | static CPUWriteMemoryFunc *lsi_ram_writefn[3] = { |
1735 | 7d8406be | pbrook | lsi_ram_writeb, |
1736 | 7d8406be | pbrook | lsi_ram_writew, |
1737 | 7d8406be | pbrook | lsi_ram_writel, |
1738 | 7d8406be | pbrook | }; |
1739 | 7d8406be | pbrook | |
1740 | 7d8406be | pbrook | static uint32_t lsi_io_readb(void *opaque, uint32_t addr) |
1741 | 7d8406be | pbrook | { |
1742 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1743 | 7d8406be | pbrook | return lsi_reg_readb(s, addr & 0xff); |
1744 | 7d8406be | pbrook | } |
1745 | 7d8406be | pbrook | |
1746 | 7d8406be | pbrook | static uint32_t lsi_io_readw(void *opaque, uint32_t addr) |
1747 | 7d8406be | pbrook | { |
1748 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1749 | 7d8406be | pbrook | uint32_t val; |
1750 | 7d8406be | pbrook | addr &= 0xff;
|
1751 | 7d8406be | pbrook | val = lsi_reg_readb(s, addr); |
1752 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 1) << 8; |
1753 | 7d8406be | pbrook | return val;
|
1754 | 7d8406be | pbrook | } |
1755 | 7d8406be | pbrook | |
1756 | 7d8406be | pbrook | static uint32_t lsi_io_readl(void *opaque, uint32_t addr) |
1757 | 7d8406be | pbrook | { |
1758 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1759 | 7d8406be | pbrook | uint32_t val; |
1760 | 7d8406be | pbrook | addr &= 0xff;
|
1761 | 7d8406be | pbrook | val = lsi_reg_readb(s, addr); |
1762 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 1) << 8; |
1763 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 2) << 16; |
1764 | 7d8406be | pbrook | val |= lsi_reg_readb(s, addr + 3) << 24; |
1765 | 7d8406be | pbrook | return val;
|
1766 | 7d8406be | pbrook | } |
1767 | 7d8406be | pbrook | |
1768 | 7d8406be | pbrook | static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val) |
1769 | 7d8406be | pbrook | { |
1770 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1771 | 7d8406be | pbrook | lsi_reg_writeb(s, addr & 0xff, val);
|
1772 | 7d8406be | pbrook | } |
1773 | 7d8406be | pbrook | |
1774 | 7d8406be | pbrook | static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val) |
1775 | 7d8406be | pbrook | { |
1776 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1777 | 7d8406be | pbrook | addr &= 0xff;
|
1778 | 7d8406be | pbrook | lsi_reg_writeb(s, addr, val & 0xff);
|
1779 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1780 | 7d8406be | pbrook | } |
1781 | 7d8406be | pbrook | |
1782 | 7d8406be | pbrook | static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val) |
1783 | 7d8406be | pbrook | { |
1784 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1785 | 7d8406be | pbrook | addr &= 0xff;
|
1786 | 7d8406be | pbrook | lsi_reg_writeb(s, addr, val & 0xff);
|
1787 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1788 | 7d8406be | pbrook | lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); |
1789 | dcfb9014 | ths | lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); |
1790 | 7d8406be | pbrook | } |
1791 | 7d8406be | pbrook | |
1792 | 5fafdf24 | ths | static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num, |
1793 | 7d8406be | pbrook | uint32_t addr, uint32_t size, int type)
|
1794 | 7d8406be | pbrook | { |
1795 | 7d8406be | pbrook | LSIState *s = (LSIState *)pci_dev; |
1796 | 7d8406be | pbrook | |
1797 | 7d8406be | pbrook | DPRINTF("Mapping IO at %08x\n", addr);
|
1798 | 7d8406be | pbrook | |
1799 | 7d8406be | pbrook | register_ioport_write(addr, 256, 1, lsi_io_writeb, s); |
1800 | 7d8406be | pbrook | register_ioport_read(addr, 256, 1, lsi_io_readb, s); |
1801 | 7d8406be | pbrook | register_ioport_write(addr, 256, 2, lsi_io_writew, s); |
1802 | 7d8406be | pbrook | register_ioport_read(addr, 256, 2, lsi_io_readw, s); |
1803 | 7d8406be | pbrook | register_ioport_write(addr, 256, 4, lsi_io_writel, s); |
1804 | 7d8406be | pbrook | register_ioport_read(addr, 256, 4, lsi_io_readl, s); |
1805 | 7d8406be | pbrook | } |
1806 | 7d8406be | pbrook | |
1807 | 5fafdf24 | ths | static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num, |
1808 | 7d8406be | pbrook | uint32_t addr, uint32_t size, int type)
|
1809 | 7d8406be | pbrook | { |
1810 | 7d8406be | pbrook | LSIState *s = (LSIState *)pci_dev; |
1811 | 7d8406be | pbrook | |
1812 | 7d8406be | pbrook | DPRINTF("Mapping ram at %08x\n", addr);
|
1813 | 7d8406be | pbrook | s->script_ram_base = addr; |
1814 | 7d8406be | pbrook | cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr); |
1815 | 7d8406be | pbrook | } |
1816 | 7d8406be | pbrook | |
1817 | 5fafdf24 | ths | static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
1818 | 7d8406be | pbrook | uint32_t addr, uint32_t size, int type)
|
1819 | 7d8406be | pbrook | { |
1820 | 7d8406be | pbrook | LSIState *s = (LSIState *)pci_dev; |
1821 | 7d8406be | pbrook | |
1822 | 7d8406be | pbrook | DPRINTF("Mapping registers at %08x\n", addr);
|
1823 | 7d8406be | pbrook | cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr); |
1824 | 7d8406be | pbrook | } |
1825 | 7d8406be | pbrook | |
1826 | 7d8406be | pbrook | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
1827 | 7d8406be | pbrook | { |
1828 | 7d8406be | pbrook | LSIState *s = (LSIState *)opaque; |
1829 | 7d8406be | pbrook | |
1830 | 7d8406be | pbrook | if (id < 0) { |
1831 | 7d8406be | pbrook | for (id = 0; id < LSI_MAX_DEVS; id++) { |
1832 | 7d8406be | pbrook | if (s->scsi_dev[id] == NULL) |
1833 | 7d8406be | pbrook | break;
|
1834 | 7d8406be | pbrook | } |
1835 | 7d8406be | pbrook | } |
1836 | 7d8406be | pbrook | if (id >= LSI_MAX_DEVS) {
|
1837 | 7d8406be | pbrook | BADF("Bad Device ID %d\n", id);
|
1838 | 7d8406be | pbrook | return;
|
1839 | 7d8406be | pbrook | } |
1840 | 7d8406be | pbrook | if (s->scsi_dev[id]) {
|
1841 | 7d8406be | pbrook | DPRINTF("Destroying device %d\n", id);
|
1842 | 8ccc2ace | ths | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
1843 | 7d8406be | pbrook | } |
1844 | 7d8406be | pbrook | DPRINTF("Attaching block device %d\n", id);
|
1845 | 985a03b0 | ths | s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
|
1846 | 985a03b0 | ths | if (s->scsi_dev[id] == NULL) |
1847 | 985a03b0 | ths | s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
|
1848 | 7d8406be | pbrook | } |
1849 | 7d8406be | pbrook | |
1850 | 7d8406be | pbrook | void *lsi_scsi_init(PCIBus *bus, int devfn) |
1851 | 7d8406be | pbrook | { |
1852 | 7d8406be | pbrook | LSIState *s; |
1853 | 7d8406be | pbrook | |
1854 | 7d8406be | pbrook | s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
|
1855 | 7d8406be | pbrook | sizeof(*s), devfn, NULL, NULL); |
1856 | 7d8406be | pbrook | if (s == NULL) { |
1857 | 7d8406be | pbrook | fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
|
1858 | 7d8406be | pbrook | return NULL; |
1859 | 7d8406be | pbrook | } |
1860 | 7d8406be | pbrook | |
1861 | 7d8406be | pbrook | s->pci_dev.config[0x00] = 0x00; |
1862 | 7d8406be | pbrook | s->pci_dev.config[0x01] = 0x10; |
1863 | 7d8406be | pbrook | s->pci_dev.config[0x02] = 0x12; |
1864 | 7d8406be | pbrook | s->pci_dev.config[0x03] = 0x00; |
1865 | 7d8406be | pbrook | s->pci_dev.config[0x0b] = 0x01; |
1866 | 7d8406be | pbrook | s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ |
1867 | 7d8406be | pbrook | |
1868 | 7d8406be | pbrook | s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
|
1869 | 7d8406be | pbrook | lsi_mmio_writefn, s); |
1870 | 7d8406be | pbrook | s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
|
1871 | 7d8406be | pbrook | lsi_ram_writefn, s); |
1872 | 7d8406be | pbrook | |
1873 | 7d8406be | pbrook | pci_register_io_region((struct PCIDevice *)s, 0, 256, |
1874 | 7d8406be | pbrook | PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc); |
1875 | 7d8406be | pbrook | pci_register_io_region((struct PCIDevice *)s, 1, 0x400, |
1876 | 7d8406be | pbrook | PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc); |
1877 | 7d8406be | pbrook | pci_register_io_region((struct PCIDevice *)s, 2, 0x2000, |
1878 | 7d8406be | pbrook | PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc); |
1879 | a917d384 | pbrook | s->queue = qemu_malloc(sizeof(lsi_queue));
|
1880 | a917d384 | pbrook | s->queue_len = 1;
|
1881 | a917d384 | pbrook | s->active_commands = 0;
|
1882 | 7d8406be | pbrook | |
1883 | 7d8406be | pbrook | lsi_soft_reset(s); |
1884 | 7d8406be | pbrook | |
1885 | 7d8406be | pbrook | return s;
|
1886 | 7d8406be | pbrook | } |