root / hw / stellaris_enet.c @ 47e4ca5a
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/*
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* Luminary Micro Stellaris Ethernet Controller
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "arm-misc.h" |
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#include "net.h" |
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#include <zlib.h> |
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//#define DEBUG_STELLARIS_ENET 1
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#ifdef DEBUG_STELLARIS_ENET
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#define DPRINTF(fmt, args...) \
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do { printf("stellaris_enet: " fmt , ##args); } while (0) |
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args); exit(1);} while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while(0) |
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args);} while (0) |
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#endif
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#define SE_INT_RX 0x01 |
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#define SE_INT_TXER 0x02 |
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#define SE_INT_TXEMP 0x04 |
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#define SE_INT_FOV 0x08 |
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#define SE_INT_RXER 0x10 |
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#define SE_INT_MD 0x20 |
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#define SE_INT_PHY 0x40 |
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#define SE_RCTL_RXEN 0x01 |
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#define SE_RCTL_AMUL 0x02 |
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#define SE_RCTL_PRMS 0x04 |
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#define SE_RCTL_BADCRC 0x08 |
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#define SE_RCTL_RSTFIFO 0x10 |
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#define SE_TCTL_TXEN 0x01 |
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#define SE_TCTL_PADEN 0x02 |
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#define SE_TCTL_CRC 0x04 |
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#define SE_TCTL_DUPLEX 0x08 |
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typedef struct { |
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uint32_t base; |
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uint32_t ris; |
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uint32_t im; |
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uint32_t rctl; |
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uint32_t tctl; |
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uint32_t thr; |
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uint32_t mctl; |
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uint32_t mdv; |
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uint32_t mtxd; |
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uint32_t mrxd; |
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uint32_t np; |
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int tx_frame_len;
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int tx_fifo_len;
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uint8_t tx_fifo[2048];
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/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
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We implement a full 31 packet fifo. */
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struct {
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uint8_t data[2048];
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int len;
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} rx[31];
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uint8_t *rx_fifo; |
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int rx_fifo_len;
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int next_packet;
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VLANClientState *vc; |
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qemu_irq irq; |
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uint8_t macaddr[6];
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} stellaris_enet_state; |
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static void stellaris_enet_update(stellaris_enet_state *s) |
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{ |
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qemu_set_irq(s->irq, (s->ris & s->im) != 0);
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} |
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/* TODO: Implement MAC address filtering. */
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static void stellaris_enet_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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stellaris_enet_state *s = (stellaris_enet_state *)opaque; |
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int n;
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uint8_t *p; |
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uint32_t crc; |
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if ((s->rctl & SE_RCTL_RXEN) == 0) |
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return;
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if (s->np >= 31) { |
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DPRINTF("Packet dropped\n");
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return;
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} |
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DPRINTF("Received packet len=%d\n", size);
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n = s->next_packet + s->np; |
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if (n >= 31) |
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n -= 31;
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s->np++; |
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s->rx[n].len = size + 6;
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p = s->rx[n].data; |
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*(p++) = (size + 6);
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*(p++) = (size + 6) >> 8; |
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memcpy (p, buf, size); |
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p += size; |
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crc = crc32(~0, buf, size);
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*(p++) = crc; |
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*(p++) = crc >> 8;
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*(p++) = crc >> 16;
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*(p++) = crc >> 24;
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/* Clear the remaining bytes in the last word. */
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if ((size & 3) != 2) { |
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memset(p, 0, (6 - size) & 3); |
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} |
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s->ris |= SE_INT_RX; |
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stellaris_enet_update(s); |
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} |
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static int stellaris_enet_can_receive(void *opaque) |
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{ |
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stellaris_enet_state *s = (stellaris_enet_state *)opaque; |
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if ((s->rctl & SE_RCTL_RXEN) == 0) |
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return 1; |
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return (s->np < 31); |
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} |
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static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset) |
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{ |
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stellaris_enet_state *s = (stellaris_enet_state *)opaque; |
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uint32_t val; |
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offset -= s->base; |
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switch (offset) {
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case 0x00: /* RIS */ |
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DPRINTF("IRQ status %02x\n", s->ris);
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return s->ris;
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case 0x04: /* IM */ |
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return s->im;
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case 0x08: /* RCTL */ |
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return s->rctl;
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case 0x0c: /* TCTL */ |
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return s->tctl;
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case 0x10: /* DATA */ |
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if (s->rx_fifo_len == 0) { |
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if (s->np == 0) { |
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BADF("RX underflow\n");
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return 0; |
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} |
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s->rx_fifo_len = s->rx[s->next_packet].len; |
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s->rx_fifo = s->rx[s->next_packet].data; |
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DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
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} |
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val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16) |
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| (s->rx_fifo[3] << 24); |
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s->rx_fifo += 4;
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s->rx_fifo_len -= 4;
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if (s->rx_fifo_len <= 0) { |
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s->rx_fifo_len = 0;
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s->next_packet++; |
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if (s->next_packet >= 31) |
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s->next_packet = 0;
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s->np--; |
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DPRINTF("RX done np=%d\n", s->np);
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} |
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return val;
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case 0x14: /* IA0 */ |
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return s->macaddr[0] | (s->macaddr[1] << 8) |
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| (s->macaddr[2] << 16) | (s->macaddr[3] << 24); |
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case 0x18: /* IA1 */ |
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return s->macaddr[4] | (s->macaddr[5] << 8); |
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case 0x1c: /* THR */ |
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return s->thr;
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case 0x20: /* MCTL */ |
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return s->mctl;
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case 0x24: /* MDV */ |
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return s->mdv;
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case 0x28: /* MADD */ |
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return 0; |
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case 0x2c: /* MTXD */ |
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return s->mtxd;
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case 0x30: /* MRXD */ |
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return s->mrxd;
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case 0x34: /* NP */ |
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return s->np;
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case 0x38: /* TR */ |
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return 0; |
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case 0x3c: /* Undocuented: Timestamp? */ |
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return 0; |
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default:
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cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset %x\n",
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(int)offset);
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return 0; |
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} |
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} |
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static void stellaris_enet_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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stellaris_enet_state *s = (stellaris_enet_state *)opaque; |
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offset -= s->base; |
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switch (offset) {
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case 0x00: /* IACK */ |
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s->ris &= ~value; |
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DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
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stellaris_enet_update(s); |
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/* Clearing TXER also resets the TX fifo. */
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if (value & SE_INT_TXER)
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s->tx_frame_len = -1;
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break;
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case 0x04: /* IM */ |
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DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
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s->im = value; |
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stellaris_enet_update(s); |
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break;
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case 0x08: /* RCTL */ |
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s->rctl = value; |
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if (value & SE_RCTL_RSTFIFO) {
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s->rx_fifo_len = 0;
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s->np = 0;
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stellaris_enet_update(s); |
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} |
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break;
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case 0x0c: /* TCTL */ |
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s->tctl = value; |
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break;
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case 0x10: /* DATA */ |
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if (s->tx_frame_len == -1) { |
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s->tx_frame_len = value & 0xffff;
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if (s->tx_frame_len > 2032) { |
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DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
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s->tx_frame_len = 0;
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s->ris |= SE_INT_TXER; |
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stellaris_enet_update(s); |
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} else {
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DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
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/* The value written does not include the ethernet header. */
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s->tx_frame_len += 14;
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if ((s->tctl & SE_TCTL_CRC) == 0) |
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s->tx_frame_len += 4;
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s->tx_fifo_len = 0;
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s->tx_fifo[s->tx_fifo_len++] = value >> 16;
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s->tx_fifo[s->tx_fifo_len++] = value >> 24;
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} |
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} else {
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s->tx_fifo[s->tx_fifo_len++] = value; |
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s->tx_fifo[s->tx_fifo_len++] = value >> 8;
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s->tx_fifo[s->tx_fifo_len++] = value >> 16;
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s->tx_fifo[s->tx_fifo_len++] = value >> 24;
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if (s->tx_fifo_len >= s->tx_frame_len) {
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/* We don't implement explicit CRC, so just chop it off. */
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if ((s->tctl & SE_TCTL_CRC) == 0) |
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s->tx_frame_len -= 4;
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if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) { |
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memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len); |
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s->tx_fifo_len = 60;
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} |
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qemu_send_packet(s->vc, s->tx_fifo, s->tx_frame_len); |
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s->tx_frame_len = -1;
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s->ris |= SE_INT_TXEMP; |
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stellaris_enet_update(s); |
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DPRINTF("Done TX\n");
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} |
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} |
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break;
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case 0x14: /* IA0 */ |
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s->macaddr[0] = value;
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s->macaddr[1] = value >> 8; |
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s->macaddr[2] = value >> 16; |
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s->macaddr[3] = value >> 24; |
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break;
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case 0x18: /* IA1 */ |
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s->macaddr[4] = value;
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s->macaddr[5] = value >> 8; |
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break;
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case 0x1c: /* THR */ |
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s->thr = value; |
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break;
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case 0x20: /* MCTL */ |
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s->mctl = value; |
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break;
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case 0x24: /* MDV */ |
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s->mdv = value; |
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break;
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case 0x28: /* MADD */ |
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/* ignored. */
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break;
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case 0x2c: /* MTXD */ |
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s->mtxd = value & 0xff;
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break;
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case 0x30: /* MRXD */ |
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case 0x34: /* NP */ |
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case 0x38: /* TR */ |
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/* Ignored. */
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case 0x3c: /* Undocuented: Timestamp? */ |
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/* Ignored. */
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break;
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default:
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cpu_abort (cpu_single_env, "stellaris_enet_write: Bad offset %x\n",
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(int)offset);
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} |
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} |
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static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
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stellaris_enet_read, |
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stellaris_enet_read, |
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stellaris_enet_read |
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}; |
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static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
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stellaris_enet_write, |
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stellaris_enet_write, |
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stellaris_enet_write |
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}; |
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static void stellaris_enet_reset(stellaris_enet_state *s) |
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{ |
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s->mdv = 0x80;
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s->rctl = SE_RCTL_BADCRC; |
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s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP |
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| SE_INT_TXER | SE_INT_RX; |
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s->thr = 0x3f;
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s->tx_frame_len = -1;
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} |
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void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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{ |
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stellaris_enet_state *s; |
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int iomemtype;
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s = (stellaris_enet_state *)qemu_mallocz(sizeof(stellaris_enet_state));
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iomemtype = cpu_register_io_memory(0, stellaris_enet_readfn,
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stellaris_enet_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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s->base = base; |
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s->irq = irq; |
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memcpy(s->macaddr, nd->macaddr, 6);
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if (nd->vlan)
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s->vc = qemu_new_vlan_client(nd->vlan, stellaris_enet_receive, |
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stellaris_enet_can_receive, s); |
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stellaris_enet_reset(s); |
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} |