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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* XXX */ |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | 7a3f1944 | bellard | #include "cpu-defs.h" |
17 | 7a3f1944 | bellard | |
18 | 7a0e1f41 | bellard | #include "softfloat.h" |
19 | 7a0e1f41 | bellard | |
20 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
21 | 1fddef4b | bellard | |
22 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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23 | 7a3f1944 | bellard | |
24 | cf495bcf | bellard | /* trap definitions */
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25 | 3475187d | bellard | #ifndef TARGET_SPARC64
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26 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
27 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
28 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
29 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
30 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
31 | cf495bcf | bellard | #define TT_WIN_UNF 0x06 |
32 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
33 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
34 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
35 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
36 | cf495bcf | bellard | #define TT_TRAP 0x80 |
37 | 3475187d | bellard | #else
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38 | 3475187d | bellard | #define TT_TFAULT 0x08 |
39 | 83469015 | bellard | #define TT_TMISS 0x09 |
40 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
41 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
42 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
43 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
44 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
45 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
46 | 3475187d | bellard | #define TT_DFAULT 0x30 |
47 | 83469015 | bellard | #define TT_DMISS 0x31 |
48 | 83469015 | bellard | #define TT_DPROT 0x32 |
49 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
50 | 3475187d | bellard | #define TT_EXTINT 0x40 |
51 | 3475187d | bellard | #define TT_SPILL 0x80 |
52 | 3475187d | bellard | #define TT_FILL 0xc0 |
53 | 3475187d | bellard | #define TT_WOTHER 0x10 |
54 | 3475187d | bellard | #define TT_TRAP 0x100 |
55 | 3475187d | bellard | #endif
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56 | 7a3f1944 | bellard | |
57 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
58 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
59 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
60 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
61 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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62 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
63 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
64 | e8af50a3 | bellard | #define PSR_S (1<<7) |
65 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
66 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
67 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
68 | e8af50a3 | bellard | |
69 | e8af50a3 | bellard | /* Trap base register */
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70 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
71 | e8af50a3 | bellard | |
72 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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73 | 83469015 | bellard | #define PS_IG (1<<11) |
74 | 83469015 | bellard | #define PS_MG (1<<10) |
75 | 83469015 | bellard | #define PS_RED (1<<5) |
76 | 3475187d | bellard | #define PS_PEF (1<<4) |
77 | 3475187d | bellard | #define PS_AM (1<<3) |
78 | 3475187d | bellard | #define PS_PRIV (1<<2) |
79 | 3475187d | bellard | #define PS_IE (1<<1) |
80 | 83469015 | bellard | #define PS_AG (1<<0) |
81 | 3475187d | bellard | #endif
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82 | 3475187d | bellard | |
83 | e8af50a3 | bellard | /* Fcc */
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84 | e8af50a3 | bellard | #define FSR_RD1 (1<<31) |
85 | e8af50a3 | bellard | #define FSR_RD0 (1<<30) |
86 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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87 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
88 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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89 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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90 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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91 | e8af50a3 | bellard | |
92 | e8af50a3 | bellard | #define FSR_NVM (1<<27) |
93 | e8af50a3 | bellard | #define FSR_OFM (1<<26) |
94 | e8af50a3 | bellard | #define FSR_UFM (1<<25) |
95 | e8af50a3 | bellard | #define FSR_DZM (1<<24) |
96 | e8af50a3 | bellard | #define FSR_NXM (1<<23) |
97 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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98 | e8af50a3 | bellard | |
99 | e8af50a3 | bellard | #define FSR_NVA (1<<9) |
100 | e8af50a3 | bellard | #define FSR_OFA (1<<8) |
101 | e8af50a3 | bellard | #define FSR_UFA (1<<7) |
102 | e8af50a3 | bellard | #define FSR_DZA (1<<6) |
103 | e8af50a3 | bellard | #define FSR_NXA (1<<5) |
104 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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105 | e8af50a3 | bellard | |
106 | e8af50a3 | bellard | #define FSR_NVC (1<<4) |
107 | e8af50a3 | bellard | #define FSR_OFC (1<<3) |
108 | e8af50a3 | bellard | #define FSR_UFC (1<<2) |
109 | e8af50a3 | bellard | #define FSR_DZC (1<<1) |
110 | e8af50a3 | bellard | #define FSR_NXC (1<<0) |
111 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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112 | e8af50a3 | bellard | |
113 | e8af50a3 | bellard | #define FSR_FTT2 (1<<16) |
114 | e8af50a3 | bellard | #define FSR_FTT1 (1<<15) |
115 | e8af50a3 | bellard | #define FSR_FTT0 (1<<14) |
116 | e8af50a3 | bellard | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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117 | e80cfcfc | bellard | #define FSR_FTT_IEEE_EXCP (1 << 14) |
118 | e80cfcfc | bellard | #define FSR_FTT_UNIMPFPOP (3 << 14) |
119 | e80cfcfc | bellard | #define FSR_FTT_INVAL_FPR (6 << 14) |
120 | e8af50a3 | bellard | |
121 | e8af50a3 | bellard | #define FSR_FCC1 (1<<11) |
122 | e8af50a3 | bellard | #define FSR_FCC0 (1<<10) |
123 | e8af50a3 | bellard | |
124 | e8af50a3 | bellard | /* MMU */
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125 | e8af50a3 | bellard | #define MMU_E (1<<0) |
126 | e8af50a3 | bellard | #define MMU_NF (1<<1) |
127 | e8af50a3 | bellard | |
128 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
129 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
130 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
131 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
132 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
133 | e8af50a3 | bellard | |
134 | e8af50a3 | bellard | #define PG_ACCESSED_BIT 5 |
135 | e8af50a3 | bellard | #define PG_MODIFIED_BIT 6 |
136 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
137 | e8af50a3 | bellard | |
138 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
139 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
140 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
141 | e8af50a3 | bellard | |
142 | 1d6e34fd | bellard | /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
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143 | 1d6e34fd | bellard | #define NWINDOWS 8 |
144 | cf495bcf | bellard | |
145 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
146 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
147 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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148 | 65ce8c2f | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
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149 | af7bf89b | bellard | target_ulong pc; /* program counter */
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150 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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151 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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152 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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153 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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154 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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155 | cf495bcf | bellard | from PSR) */
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156 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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157 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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158 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
159 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
160 | e8af50a3 | bellard | int psret; /* enable traps */ |
161 | 3475187d | bellard | uint32_t psrpil; /* interrupt level */
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162 | e80cfcfc | bellard | int psref; /* enable fpu */ |
163 | cf495bcf | bellard | jmp_buf jmp_env; |
164 | cf495bcf | bellard | int user_mode_only;
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165 | cf495bcf | bellard | int exception_index;
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166 | cf495bcf | bellard | int interrupt_index;
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167 | cf495bcf | bellard | int interrupt_request;
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168 | ba3c64fb | bellard | int halted;
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169 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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170 | af7bf89b | bellard | target_ulong regbase[NWINDOWS * 16 + 8]; |
171 | d720b93d | bellard | |
172 | a316d335 | bellard | CPU_COMMON |
173 | a316d335 | bellard | |
174 | e8af50a3 | bellard | /* MMU regs */
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175 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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176 | 3475187d | bellard | uint64_t lsu; |
177 | 3475187d | bellard | #define DMMU_E 0x8 |
178 | 3475187d | bellard | #define IMMU_E 0x4 |
179 | 3475187d | bellard | uint64_t immuregs[16];
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180 | 3475187d | bellard | uint64_t dmmuregs[16];
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181 | 3475187d | bellard | uint64_t itlb_tag[64];
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182 | 3475187d | bellard | uint64_t itlb_tte[64];
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183 | 3475187d | bellard | uint64_t dtlb_tag[64];
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184 | 3475187d | bellard | uint64_t dtlb_tte[64];
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185 | 3475187d | bellard | #else
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186 | e8af50a3 | bellard | uint32_t mmuregs[16];
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187 | 3475187d | bellard | #endif
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188 | e8af50a3 | bellard | /* temporary float registers */
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189 | 65ce8c2f | bellard | float32 ft0, ft1; |
190 | 65ce8c2f | bellard | float64 dt0, dt1; |
191 | 7a0e1f41 | bellard | float_status fp_status; |
192 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
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193 | 3475187d | bellard | #define MAXTL 4 |
194 | 3475187d | bellard | uint64_t t0, t1, t2; |
195 | 3475187d | bellard | uint64_t tpc[MAXTL]; |
196 | 3475187d | bellard | uint64_t tnpc[MAXTL]; |
197 | 3475187d | bellard | uint64_t tstate[MAXTL]; |
198 | 3475187d | bellard | uint32_t tt[MAXTL]; |
199 | 3475187d | bellard | uint32_t xcc; /* Extended integer condition codes */
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200 | 3475187d | bellard | uint32_t asi; |
201 | 3475187d | bellard | uint32_t pstate; |
202 | 3475187d | bellard | uint32_t tl; |
203 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
204 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
205 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
206 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
207 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
208 | 3475187d | bellard | uint64_t version; |
209 | 3475187d | bellard | uint64_t fprs; |
210 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
211 | 3475187d | bellard | #endif
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212 | 3475187d | bellard | #if !defined(TARGET_SPARC64) && !defined(reg_T2)
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213 | 3475187d | bellard | target_ulong t2; |
214 | af7bf89b | bellard | #endif
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215 | 7a3f1944 | bellard | } CPUSPARCState; |
216 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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217 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
218 | 3475187d | bellard | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
219 | 3475187d | bellard | env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ |
220 | 3475187d | bellard | } while (0) |
221 | 3475187d | bellard | #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) |
222 | 3475187d | bellard | #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ |
223 | 3475187d | bellard | env->fsr = _tmp & 0x3fcfc1c3ffULL; \
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224 | 3475187d | bellard | } while (0) |
225 | 3475187d | bellard | // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
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226 | 3475187d | bellard | #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \ |
227 | 3475187d | bellard | (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1)) |
228 | 3475187d | bellard | #else
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229 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr)
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230 | 3475187d | bellard | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
231 | 3475187d | bellard | env->fsr = _tmp & 0xcfc1ffff; \
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232 | 3475187d | bellard | } while (0) |
233 | 3475187d | bellard | #endif
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234 | 7a3f1944 | bellard | |
235 | 7a3f1944 | bellard | CPUSPARCState *cpu_sparc_init(void);
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236 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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237 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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238 | 7a3f1944 | bellard | |
239 | b4ff5987 | bellard | /* Fake impl 0, version 4 */
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240 | af7bf89b | bellard | #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \ |
241 | b4ff5987 | bellard | (env->psref? PSR_EF : 0) | \
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242 | b4ff5987 | bellard | (env->psrpil << 8) | \
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243 | b4ff5987 | bellard | (env->psrs? PSR_S : 0) | \
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244 | afc7df11 | bellard | (env->psrps? PSR_PS : 0) | \
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245 | b4ff5987 | bellard | (env->psret? PSR_ET : 0) | env->cwp)
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246 | b4ff5987 | bellard | |
247 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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248 | b4ff5987 | bellard | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
249 | b4ff5987 | bellard | #endif
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250 | b4ff5987 | bellard | |
251 | b4ff5987 | bellard | #define PUT_PSR(env, val) do { int _tmp = val; \ |
252 | af7bf89b | bellard | env->psr = _tmp & PSR_ICC; \ |
253 | b4ff5987 | bellard | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
254 | b4ff5987 | bellard | env->psrpil = (_tmp & PSR_PIL) >> 8; \
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255 | b4ff5987 | bellard | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
256 | b4ff5987 | bellard | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
257 | b4ff5987 | bellard | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
258 | b4ff5987 | bellard | cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
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259 | b4ff5987 | bellard | } while (0) |
260 | b4ff5987 | bellard | |
261 | 3475187d | bellard | #ifdef TARGET_SPARC64
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262 | 3475187d | bellard | #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC)) |
263 | 3475187d | bellard | #define PUT_CCR(env, val) do { int _tmp = val; \ |
264 | 3475187d | bellard | env->xcc = _tmp >> 4; \
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265 | 3475187d | bellard | env->psr = (_tmp & 0xf) << 20; \ |
266 | 3475187d | bellard | } while (0) |
267 | 3475187d | bellard | #endif
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268 | 3475187d | bellard | |
269 | 7a3f1944 | bellard | struct siginfo;
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270 | 7a3f1944 | bellard | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); |
271 | 7a3f1944 | bellard | |
272 | 7a3f1944 | bellard | #include "cpu-all.h" |
273 | 7a3f1944 | bellard | |
274 | 7a3f1944 | bellard | #endif |