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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC micro operations
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 7a3f1944 | bellard | |
6 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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7 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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8 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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9 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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10 | 7a3f1944 | bellard | |
11 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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12 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 7a3f1944 | bellard | Lesser General Public License for more details.
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15 | 7a3f1944 | bellard | |
16 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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17 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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18 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7a3f1944 | bellard | */
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20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #include "exec.h" |
22 | 7a3f1944 | bellard | |
23 | cf495bcf | bellard | /*XXX*/
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24 | 7a3f1944 | bellard | #define REGNAME g0
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25 | 7a3f1944 | bellard | #define REG (env->gregs[0]) |
26 | 7a3f1944 | bellard | #include "op_template.h" |
27 | 7a3f1944 | bellard | #define REGNAME g1
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28 | 7a3f1944 | bellard | #define REG (env->gregs[1]) |
29 | 7a3f1944 | bellard | #include "op_template.h" |
30 | 7a3f1944 | bellard | #define REGNAME g2
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31 | 7a3f1944 | bellard | #define REG (env->gregs[2]) |
32 | 7a3f1944 | bellard | #include "op_template.h" |
33 | 7a3f1944 | bellard | #define REGNAME g3
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34 | 7a3f1944 | bellard | #define REG (env->gregs[3]) |
35 | 7a3f1944 | bellard | #include "op_template.h" |
36 | 7a3f1944 | bellard | #define REGNAME g4
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37 | 7a3f1944 | bellard | #define REG (env->gregs[4]) |
38 | 7a3f1944 | bellard | #include "op_template.h" |
39 | 7a3f1944 | bellard | #define REGNAME g5
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40 | 7a3f1944 | bellard | #define REG (env->gregs[5]) |
41 | 7a3f1944 | bellard | #include "op_template.h" |
42 | 7a3f1944 | bellard | #define REGNAME g6
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43 | 7a3f1944 | bellard | #define REG (env->gregs[6]) |
44 | 7a3f1944 | bellard | #include "op_template.h" |
45 | 7a3f1944 | bellard | #define REGNAME g7
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46 | 7a3f1944 | bellard | #define REG (env->gregs[7]) |
47 | 7a3f1944 | bellard | #include "op_template.h" |
48 | 7a3f1944 | bellard | #define REGNAME i0
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49 | 3475187d | bellard | #define REG (REGWPTR[16]) |
50 | 7a3f1944 | bellard | #include "op_template.h" |
51 | 7a3f1944 | bellard | #define REGNAME i1
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52 | 3475187d | bellard | #define REG (REGWPTR[17]) |
53 | 7a3f1944 | bellard | #include "op_template.h" |
54 | 7a3f1944 | bellard | #define REGNAME i2
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55 | 3475187d | bellard | #define REG (REGWPTR[18]) |
56 | 7a3f1944 | bellard | #include "op_template.h" |
57 | 7a3f1944 | bellard | #define REGNAME i3
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58 | 3475187d | bellard | #define REG (REGWPTR[19]) |
59 | 7a3f1944 | bellard | #include "op_template.h" |
60 | 7a3f1944 | bellard | #define REGNAME i4
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61 | 3475187d | bellard | #define REG (REGWPTR[20]) |
62 | 7a3f1944 | bellard | #include "op_template.h" |
63 | 7a3f1944 | bellard | #define REGNAME i5
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64 | 3475187d | bellard | #define REG (REGWPTR[21]) |
65 | 7a3f1944 | bellard | #include "op_template.h" |
66 | 7a3f1944 | bellard | #define REGNAME i6
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67 | 3475187d | bellard | #define REG (REGWPTR[22]) |
68 | 7a3f1944 | bellard | #include "op_template.h" |
69 | 7a3f1944 | bellard | #define REGNAME i7
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70 | 3475187d | bellard | #define REG (REGWPTR[23]) |
71 | 7a3f1944 | bellard | #include "op_template.h" |
72 | 7a3f1944 | bellard | #define REGNAME l0
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73 | 3475187d | bellard | #define REG (REGWPTR[8]) |
74 | 7a3f1944 | bellard | #include "op_template.h" |
75 | 7a3f1944 | bellard | #define REGNAME l1
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76 | 3475187d | bellard | #define REG (REGWPTR[9]) |
77 | 7a3f1944 | bellard | #include "op_template.h" |
78 | 7a3f1944 | bellard | #define REGNAME l2
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79 | 3475187d | bellard | #define REG (REGWPTR[10]) |
80 | 7a3f1944 | bellard | #include "op_template.h" |
81 | 7a3f1944 | bellard | #define REGNAME l3
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82 | 3475187d | bellard | #define REG (REGWPTR[11]) |
83 | 7a3f1944 | bellard | #include "op_template.h" |
84 | 7a3f1944 | bellard | #define REGNAME l4
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85 | 3475187d | bellard | #define REG (REGWPTR[12]) |
86 | 7a3f1944 | bellard | #include "op_template.h" |
87 | 7a3f1944 | bellard | #define REGNAME l5
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88 | 3475187d | bellard | #define REG (REGWPTR[13]) |
89 | 7a3f1944 | bellard | #include "op_template.h" |
90 | 7a3f1944 | bellard | #define REGNAME l6
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91 | 3475187d | bellard | #define REG (REGWPTR[14]) |
92 | 7a3f1944 | bellard | #include "op_template.h" |
93 | 7a3f1944 | bellard | #define REGNAME l7
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94 | 3475187d | bellard | #define REG (REGWPTR[15]) |
95 | 7a3f1944 | bellard | #include "op_template.h" |
96 | 7a3f1944 | bellard | #define REGNAME o0
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97 | 3475187d | bellard | #define REG (REGWPTR[0]) |
98 | 7a3f1944 | bellard | #include "op_template.h" |
99 | 7a3f1944 | bellard | #define REGNAME o1
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100 | 3475187d | bellard | #define REG (REGWPTR[1]) |
101 | 7a3f1944 | bellard | #include "op_template.h" |
102 | 7a3f1944 | bellard | #define REGNAME o2
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103 | 3475187d | bellard | #define REG (REGWPTR[2]) |
104 | 7a3f1944 | bellard | #include "op_template.h" |
105 | 7a3f1944 | bellard | #define REGNAME o3
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106 | 3475187d | bellard | #define REG (REGWPTR[3]) |
107 | 7a3f1944 | bellard | #include "op_template.h" |
108 | 7a3f1944 | bellard | #define REGNAME o4
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109 | 3475187d | bellard | #define REG (REGWPTR[4]) |
110 | 7a3f1944 | bellard | #include "op_template.h" |
111 | 7a3f1944 | bellard | #define REGNAME o5
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112 | 3475187d | bellard | #define REG (REGWPTR[5]) |
113 | 7a3f1944 | bellard | #include "op_template.h" |
114 | 7a3f1944 | bellard | #define REGNAME o6
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115 | 3475187d | bellard | #define REG (REGWPTR[6]) |
116 | 7a3f1944 | bellard | #include "op_template.h" |
117 | 7a3f1944 | bellard | #define REGNAME o7
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118 | 3475187d | bellard | #define REG (REGWPTR[7]) |
119 | 7a3f1944 | bellard | #include "op_template.h" |
120 | e8af50a3 | bellard | |
121 | e8af50a3 | bellard | #define REGNAME f0
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122 | e8af50a3 | bellard | #define REG (env->fpr[0]) |
123 | e8af50a3 | bellard | #include "fop_template.h" |
124 | e8af50a3 | bellard | #define REGNAME f1
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125 | e8af50a3 | bellard | #define REG (env->fpr[1]) |
126 | e8af50a3 | bellard | #include "fop_template.h" |
127 | e8af50a3 | bellard | #define REGNAME f2
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128 | e8af50a3 | bellard | #define REG (env->fpr[2]) |
129 | e8af50a3 | bellard | #include "fop_template.h" |
130 | e8af50a3 | bellard | #define REGNAME f3
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131 | e8af50a3 | bellard | #define REG (env->fpr[3]) |
132 | e8af50a3 | bellard | #include "fop_template.h" |
133 | e8af50a3 | bellard | #define REGNAME f4
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134 | e8af50a3 | bellard | #define REG (env->fpr[4]) |
135 | e8af50a3 | bellard | #include "fop_template.h" |
136 | e8af50a3 | bellard | #define REGNAME f5
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137 | e8af50a3 | bellard | #define REG (env->fpr[5]) |
138 | e8af50a3 | bellard | #include "fop_template.h" |
139 | e8af50a3 | bellard | #define REGNAME f6
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140 | e8af50a3 | bellard | #define REG (env->fpr[6]) |
141 | e8af50a3 | bellard | #include "fop_template.h" |
142 | e8af50a3 | bellard | #define REGNAME f7
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143 | e8af50a3 | bellard | #define REG (env->fpr[7]) |
144 | e8af50a3 | bellard | #include "fop_template.h" |
145 | e8af50a3 | bellard | #define REGNAME f8
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146 | e8af50a3 | bellard | #define REG (env->fpr[8]) |
147 | e8af50a3 | bellard | #include "fop_template.h" |
148 | e8af50a3 | bellard | #define REGNAME f9
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149 | e8af50a3 | bellard | #define REG (env->fpr[9]) |
150 | e8af50a3 | bellard | #include "fop_template.h" |
151 | e8af50a3 | bellard | #define REGNAME f10
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152 | e8af50a3 | bellard | #define REG (env->fpr[10]) |
153 | e8af50a3 | bellard | #include "fop_template.h" |
154 | e8af50a3 | bellard | #define REGNAME f11
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155 | e8af50a3 | bellard | #define REG (env->fpr[11]) |
156 | e8af50a3 | bellard | #include "fop_template.h" |
157 | e8af50a3 | bellard | #define REGNAME f12
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158 | e8af50a3 | bellard | #define REG (env->fpr[12]) |
159 | e8af50a3 | bellard | #include "fop_template.h" |
160 | e8af50a3 | bellard | #define REGNAME f13
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161 | e8af50a3 | bellard | #define REG (env->fpr[13]) |
162 | e8af50a3 | bellard | #include "fop_template.h" |
163 | e8af50a3 | bellard | #define REGNAME f14
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164 | e8af50a3 | bellard | #define REG (env->fpr[14]) |
165 | e8af50a3 | bellard | #include "fop_template.h" |
166 | e8af50a3 | bellard | #define REGNAME f15
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167 | e8af50a3 | bellard | #define REG (env->fpr[15]) |
168 | e8af50a3 | bellard | #include "fop_template.h" |
169 | e8af50a3 | bellard | #define REGNAME f16
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170 | e8af50a3 | bellard | #define REG (env->fpr[16]) |
171 | e8af50a3 | bellard | #include "fop_template.h" |
172 | e8af50a3 | bellard | #define REGNAME f17
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173 | e8af50a3 | bellard | #define REG (env->fpr[17]) |
174 | e8af50a3 | bellard | #include "fop_template.h" |
175 | e8af50a3 | bellard | #define REGNAME f18
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176 | e8af50a3 | bellard | #define REG (env->fpr[18]) |
177 | e8af50a3 | bellard | #include "fop_template.h" |
178 | e8af50a3 | bellard | #define REGNAME f19
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179 | e8af50a3 | bellard | #define REG (env->fpr[19]) |
180 | e8af50a3 | bellard | #include "fop_template.h" |
181 | e8af50a3 | bellard | #define REGNAME f20
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182 | e8af50a3 | bellard | #define REG (env->fpr[20]) |
183 | e8af50a3 | bellard | #include "fop_template.h" |
184 | e8af50a3 | bellard | #define REGNAME f21
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185 | e8af50a3 | bellard | #define REG (env->fpr[21]) |
186 | e8af50a3 | bellard | #include "fop_template.h" |
187 | e8af50a3 | bellard | #define REGNAME f22
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188 | e8af50a3 | bellard | #define REG (env->fpr[22]) |
189 | e8af50a3 | bellard | #include "fop_template.h" |
190 | e8af50a3 | bellard | #define REGNAME f23
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191 | e8af50a3 | bellard | #define REG (env->fpr[23]) |
192 | e8af50a3 | bellard | #include "fop_template.h" |
193 | e8af50a3 | bellard | #define REGNAME f24
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194 | e8af50a3 | bellard | #define REG (env->fpr[24]) |
195 | e8af50a3 | bellard | #include "fop_template.h" |
196 | e8af50a3 | bellard | #define REGNAME f25
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197 | e8af50a3 | bellard | #define REG (env->fpr[25]) |
198 | e8af50a3 | bellard | #include "fop_template.h" |
199 | e8af50a3 | bellard | #define REGNAME f26
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200 | e8af50a3 | bellard | #define REG (env->fpr[26]) |
201 | e8af50a3 | bellard | #include "fop_template.h" |
202 | e8af50a3 | bellard | #define REGNAME f27
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203 | e8af50a3 | bellard | #define REG (env->fpr[27]) |
204 | e8af50a3 | bellard | #include "fop_template.h" |
205 | e8af50a3 | bellard | #define REGNAME f28
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206 | e8af50a3 | bellard | #define REG (env->fpr[28]) |
207 | e8af50a3 | bellard | #include "fop_template.h" |
208 | e8af50a3 | bellard | #define REGNAME f29
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209 | e8af50a3 | bellard | #define REG (env->fpr[29]) |
210 | e8af50a3 | bellard | #include "fop_template.h" |
211 | e8af50a3 | bellard | #define REGNAME f30
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212 | e8af50a3 | bellard | #define REG (env->fpr[30]) |
213 | e8af50a3 | bellard | #include "fop_template.h" |
214 | e8af50a3 | bellard | #define REGNAME f31
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215 | e8af50a3 | bellard | #define REG (env->fpr[31]) |
216 | e8af50a3 | bellard | #include "fop_template.h" |
217 | e8af50a3 | bellard | |
218 | 3475187d | bellard | #ifdef TARGET_SPARC64
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219 | 3475187d | bellard | #define REGNAME f32
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220 | 3475187d | bellard | #define REG (env->fpr[32]) |
221 | 3475187d | bellard | #include "fop_template.h" |
222 | 3475187d | bellard | #define REGNAME f34
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223 | 3475187d | bellard | #define REG (env->fpr[34]) |
224 | 3475187d | bellard | #include "fop_template.h" |
225 | 3475187d | bellard | #define REGNAME f36
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226 | 3475187d | bellard | #define REG (env->fpr[36]) |
227 | 3475187d | bellard | #include "fop_template.h" |
228 | 3475187d | bellard | #define REGNAME f38
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229 | 3475187d | bellard | #define REG (env->fpr[38]) |
230 | 3475187d | bellard | #include "fop_template.h" |
231 | 3475187d | bellard | #define REGNAME f40
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232 | 3475187d | bellard | #define REG (env->fpr[40]) |
233 | 3475187d | bellard | #include "fop_template.h" |
234 | 3475187d | bellard | #define REGNAME f42
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235 | 3475187d | bellard | #define REG (env->fpr[42]) |
236 | 3475187d | bellard | #include "fop_template.h" |
237 | 3475187d | bellard | #define REGNAME f44
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238 | 3475187d | bellard | #define REG (env->fpr[44]) |
239 | 3475187d | bellard | #include "fop_template.h" |
240 | 3475187d | bellard | #define REGNAME f46
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241 | 3475187d | bellard | #define REG (env->fpr[46]) |
242 | 3475187d | bellard | #include "fop_template.h" |
243 | 3475187d | bellard | #define REGNAME f48
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244 | 3475187d | bellard | #define REG (env->fpr[47]) |
245 | 3475187d | bellard | #include "fop_template.h" |
246 | 3475187d | bellard | #define REGNAME f50
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247 | 3475187d | bellard | #define REG (env->fpr[50]) |
248 | 3475187d | bellard | #include "fop_template.h" |
249 | 3475187d | bellard | #define REGNAME f52
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250 | 3475187d | bellard | #define REG (env->fpr[52]) |
251 | 3475187d | bellard | #include "fop_template.h" |
252 | 3475187d | bellard | #define REGNAME f54
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253 | 3475187d | bellard | #define REG (env->fpr[54]) |
254 | 3475187d | bellard | #include "fop_template.h" |
255 | 3475187d | bellard | #define REGNAME f56
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256 | 3475187d | bellard | #define REG (env->fpr[56]) |
257 | 3475187d | bellard | #include "fop_template.h" |
258 | 3475187d | bellard | #define REGNAME f58
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259 | 3475187d | bellard | #define REG (env->fpr[58]) |
260 | 3475187d | bellard | #include "fop_template.h" |
261 | 3475187d | bellard | #define REGNAME f60
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262 | 3475187d | bellard | #define REG (env->fpr[60]) |
263 | 3475187d | bellard | #include "fop_template.h" |
264 | 3475187d | bellard | #define REGNAME f62
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265 | 3475187d | bellard | #define REG (env->fpr[62]) |
266 | 3475187d | bellard | #include "fop_template.h" |
267 | 3475187d | bellard | #endif
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268 | 3475187d | bellard | |
269 | 3475187d | bellard | #ifdef TARGET_SPARC64
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270 | 3475187d | bellard | #ifdef WORDS_BIGENDIAN
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271 | 3475187d | bellard | typedef union UREG64 { |
272 | 3475187d | bellard | struct { uint16_t v3, v2, v1, v0; } w;
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273 | 3475187d | bellard | struct { uint32_t v1, v0; } l;
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274 | 3475187d | bellard | uint64_t q; |
275 | 3475187d | bellard | } UREG64; |
276 | 3475187d | bellard | #else
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277 | 3475187d | bellard | typedef union UREG64 { |
278 | 3475187d | bellard | struct { uint16_t v0, v1, v2, v3; } w;
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279 | 3475187d | bellard | struct { uint32_t v0, v1; } l;
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280 | 3475187d | bellard | uint64_t q; |
281 | 3475187d | bellard | } UREG64; |
282 | 3475187d | bellard | #endif
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283 | 3475187d | bellard | |
284 | 3475187d | bellard | #define PARAMQ1 \
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285 | 3475187d | bellard | ({\ |
286 | 3475187d | bellard | UREG64 __p;\ |
287 | 3475187d | bellard | __p.l.v1 = PARAM1;\ |
288 | 3475187d | bellard | __p.l.v0 = PARAM2;\ |
289 | 3475187d | bellard | __p.q;\ |
290 | 3475187d | bellard | }) |
291 | 3475187d | bellard | |
292 | 3475187d | bellard | void OPPROTO op_movq_T0_im64(void) |
293 | 3475187d | bellard | { |
294 | 3475187d | bellard | T0 = PARAMQ1; |
295 | 3475187d | bellard | } |
296 | 3475187d | bellard | |
297 | 3475187d | bellard | void OPPROTO op_movq_T1_im64(void) |
298 | 3475187d | bellard | { |
299 | 3475187d | bellard | T1 = PARAMQ1; |
300 | 3475187d | bellard | } |
301 | 3475187d | bellard | |
302 | 3475187d | bellard | #define XFLAG_SET(x) ((env->xcc&x)?1:0) |
303 | 3475187d | bellard | |
304 | 3475187d | bellard | #else
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305 | 7a3f1944 | bellard | #define EIP (env->pc)
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306 | 3475187d | bellard | #endif
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307 | 7a3f1944 | bellard | |
308 | af7bf89b | bellard | #define FLAG_SET(x) ((env->psr&x)?1:0) |
309 | cf495bcf | bellard | |
310 | 7a3f1944 | bellard | void OPPROTO op_movl_T0_0(void) |
311 | 7a3f1944 | bellard | { |
312 | cf495bcf | bellard | T0 = 0;
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313 | 7a3f1944 | bellard | } |
314 | 7a3f1944 | bellard | |
315 | 7a3f1944 | bellard | void OPPROTO op_movl_T0_im(void) |
316 | 7a3f1944 | bellard | { |
317 | 3475187d | bellard | T0 = (uint32_t)PARAM1; |
318 | 7a3f1944 | bellard | } |
319 | 7a3f1944 | bellard | |
320 | 7a3f1944 | bellard | void OPPROTO op_movl_T1_im(void) |
321 | 7a3f1944 | bellard | { |
322 | 3475187d | bellard | T1 = (uint32_t)PARAM1; |
323 | 7a3f1944 | bellard | } |
324 | 7a3f1944 | bellard | |
325 | 7a3f1944 | bellard | void OPPROTO op_movl_T2_im(void) |
326 | 7a3f1944 | bellard | { |
327 | 3475187d | bellard | T2 = (uint32_t)PARAM1; |
328 | 3475187d | bellard | } |
329 | 3475187d | bellard | |
330 | 3475187d | bellard | void OPPROTO op_movl_T0_sim(void) |
331 | 3475187d | bellard | { |
332 | 3475187d | bellard | T0 = (int32_t)PARAM1; |
333 | 3475187d | bellard | } |
334 | 3475187d | bellard | |
335 | 3475187d | bellard | void OPPROTO op_movl_T1_sim(void) |
336 | 3475187d | bellard | { |
337 | 3475187d | bellard | T1 = (int32_t)PARAM1; |
338 | 3475187d | bellard | } |
339 | 3475187d | bellard | |
340 | 3475187d | bellard | void OPPROTO op_movl_T2_sim(void) |
341 | 3475187d | bellard | { |
342 | 3475187d | bellard | T2 = (int32_t)PARAM1; |
343 | 3475187d | bellard | } |
344 | 3475187d | bellard | |
345 | 3475187d | bellard | void OPPROTO op_movl_T0_env(void) |
346 | 3475187d | bellard | { |
347 | 3475187d | bellard | T0 = *(uint32_t *)((char *)env + PARAM1);
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348 | 3475187d | bellard | } |
349 | 3475187d | bellard | |
350 | 3475187d | bellard | void OPPROTO op_movl_env_T0(void) |
351 | 3475187d | bellard | { |
352 | 3475187d | bellard | *(uint32_t *)((char *)env + PARAM1) = T0;
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353 | 3475187d | bellard | } |
354 | 3475187d | bellard | |
355 | 3475187d | bellard | void OPPROTO op_movtl_T0_env(void) |
356 | 3475187d | bellard | { |
357 | 3475187d | bellard | T0 = *(target_ulong *)((char *)env + PARAM1);
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358 | 3475187d | bellard | } |
359 | 3475187d | bellard | |
360 | 3475187d | bellard | void OPPROTO op_movtl_env_T0(void) |
361 | 3475187d | bellard | { |
362 | 3475187d | bellard | *(target_ulong *)((char *)env + PARAM1) = T0;
|
363 | 7a3f1944 | bellard | } |
364 | 7a3f1944 | bellard | |
365 | af7bf89b | bellard | void OPPROTO op_add_T1_T0(void) |
366 | 7a3f1944 | bellard | { |
367 | af7bf89b | bellard | T0 += T1; |
368 | 7a3f1944 | bellard | } |
369 | 7a3f1944 | bellard | |
370 | af7bf89b | bellard | void OPPROTO op_add_T1_T0_cc(void) |
371 | 7a3f1944 | bellard | { |
372 | af7bf89b | bellard | target_ulong src1; |
373 | 7a3f1944 | bellard | |
374 | af7bf89b | bellard | src1 = T0; |
375 | af7bf89b | bellard | T0 += T1; |
376 | af7bf89b | bellard | env->psr = 0;
|
377 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
378 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
379 | 3475187d | bellard | env->psr |= PSR_ZERO; |
380 | 3475187d | bellard | if ((int32_t) T0 < 0) |
381 | 3475187d | bellard | env->psr |= PSR_NEG; |
382 | bb3911a6 | bellard | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
383 | 3475187d | bellard | env->psr |= PSR_CARRY; |
384 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
385 | 3475187d | bellard | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
386 | 3475187d | bellard | env->psr |= PSR_OVF; |
387 | 3475187d | bellard | |
388 | 3475187d | bellard | env->xcc = 0;
|
389 | 3475187d | bellard | if (!T0)
|
390 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
391 | 3475187d | bellard | if ((int64_t) T0 < 0) |
392 | 3475187d | bellard | env->xcc |= PSR_NEG; |
393 | 3475187d | bellard | if (T0 < src1)
|
394 | 3475187d | bellard | env->xcc |= PSR_CARRY; |
395 | 3475187d | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) |
396 | 3475187d | bellard | env->xcc |= PSR_OVF; |
397 | 3475187d | bellard | #else
|
398 | af7bf89b | bellard | if (!T0)
|
399 | af7bf89b | bellard | env->psr |= PSR_ZERO; |
400 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
401 | af7bf89b | bellard | env->psr |= PSR_NEG; |
402 | af7bf89b | bellard | if (T0 < src1)
|
403 | af7bf89b | bellard | env->psr |= PSR_CARRY; |
404 | af7bf89b | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
405 | af7bf89b | bellard | env->psr |= PSR_OVF; |
406 | 3475187d | bellard | #endif
|
407 | af7bf89b | bellard | FORCE_RET(); |
408 | 7a3f1944 | bellard | } |
409 | 7a3f1944 | bellard | |
410 | af7bf89b | bellard | void OPPROTO op_addx_T1_T0(void) |
411 | 7a3f1944 | bellard | { |
412 | af7bf89b | bellard | T0 += T1 + FLAG_SET(PSR_CARRY); |
413 | 7a3f1944 | bellard | } |
414 | 7a3f1944 | bellard | |
415 | af7bf89b | bellard | void OPPROTO op_addx_T1_T0_cc(void) |
416 | 7a3f1944 | bellard | { |
417 | af7bf89b | bellard | target_ulong src1; |
418 | cf495bcf | bellard | src1 = T0; |
419 | b854608e | bellard | if (FLAG_SET(PSR_CARRY))
|
420 | b854608e | bellard | { |
421 | b854608e | bellard | T0 += T1 + 1;
|
422 | b854608e | bellard | env->psr = 0;
|
423 | b854608e | bellard | #ifdef TARGET_SPARC64
|
424 | b854608e | bellard | if ((T0 & 0xffffffff) <= (src1 & 0xffffffff)) |
425 | b854608e | bellard | env->psr |= PSR_CARRY; |
426 | b854608e | bellard | env->xcc = 0;
|
427 | b854608e | bellard | if (T0 <= src1)
|
428 | b854608e | bellard | env->xcc |= PSR_CARRY; |
429 | b854608e | bellard | #else
|
430 | b854608e | bellard | if (T0 <= src1)
|
431 | b854608e | bellard | env->psr |= PSR_CARRY; |
432 | b854608e | bellard | #endif
|
433 | b854608e | bellard | } |
434 | b854608e | bellard | else
|
435 | b854608e | bellard | { |
436 | b854608e | bellard | T0 += T1; |
437 | b854608e | bellard | env->psr = 0;
|
438 | b854608e | bellard | #ifdef TARGET_SPARC64
|
439 | b854608e | bellard | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
440 | b854608e | bellard | env->psr |= PSR_CARRY; |
441 | b854608e | bellard | env->xcc = 0;
|
442 | b854608e | bellard | if (T0 < src1)
|
443 | b854608e | bellard | env->xcc |= PSR_CARRY; |
444 | b854608e | bellard | #else
|
445 | b854608e | bellard | if (T0 < src1)
|
446 | b854608e | bellard | env->psr |= PSR_CARRY; |
447 | b854608e | bellard | #endif
|
448 | b854608e | bellard | } |
449 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
450 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
451 | 3475187d | bellard | env->psr |= PSR_ZERO; |
452 | 3475187d | bellard | if ((int32_t) T0 < 0) |
453 | 3475187d | bellard | env->psr |= PSR_NEG; |
454 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
455 | 3475187d | bellard | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
456 | 3475187d | bellard | env->psr |= PSR_OVF; |
457 | 3475187d | bellard | |
458 | 3475187d | bellard | if (!T0)
|
459 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
460 | 3475187d | bellard | if ((int64_t) T0 < 0) |
461 | 3475187d | bellard | env->xcc |= PSR_NEG; |
462 | 3475187d | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) |
463 | 3475187d | bellard | env->xcc |= PSR_OVF; |
464 | 3475187d | bellard | #else
|
465 | cf495bcf | bellard | if (!T0)
|
466 | cf495bcf | bellard | env->psr |= PSR_ZERO; |
467 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
468 | cf495bcf | bellard | env->psr |= PSR_NEG; |
469 | cf495bcf | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
470 | cf495bcf | bellard | env->psr |= PSR_OVF; |
471 | 3475187d | bellard | #endif
|
472 | cf495bcf | bellard | FORCE_RET(); |
473 | 7a3f1944 | bellard | } |
474 | 7a3f1944 | bellard | |
475 | cf495bcf | bellard | void OPPROTO op_sub_T1_T0(void) |
476 | 7a3f1944 | bellard | { |
477 | cf495bcf | bellard | T0 -= T1; |
478 | 7a3f1944 | bellard | } |
479 | 7a3f1944 | bellard | |
480 | cf495bcf | bellard | void OPPROTO op_sub_T1_T0_cc(void) |
481 | 7a3f1944 | bellard | { |
482 | af7bf89b | bellard | target_ulong src1; |
483 | cf495bcf | bellard | |
484 | cf495bcf | bellard | src1 = T0; |
485 | cf495bcf | bellard | T0 -= T1; |
486 | cf495bcf | bellard | env->psr = 0;
|
487 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
488 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
489 | 3475187d | bellard | env->psr |= PSR_ZERO; |
490 | 3475187d | bellard | if ((int32_t) T0 < 0) |
491 | 3475187d | bellard | env->psr |= PSR_NEG; |
492 | 83469015 | bellard | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
493 | 3475187d | bellard | env->psr |= PSR_CARRY; |
494 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
495 | 3475187d | bellard | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
496 | 3475187d | bellard | env->psr |= PSR_OVF; |
497 | 3475187d | bellard | |
498 | 3475187d | bellard | env->xcc = 0;
|
499 | 3475187d | bellard | if (!T0)
|
500 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
501 | 3475187d | bellard | if ((int64_t) T0 < 0) |
502 | 3475187d | bellard | env->xcc |= PSR_NEG; |
503 | bb3911a6 | bellard | if (src1 < T1)
|
504 | 3475187d | bellard | env->xcc |= PSR_CARRY; |
505 | 3475187d | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) |
506 | 3475187d | bellard | env->xcc |= PSR_OVF; |
507 | 3475187d | bellard | #else
|
508 | cf495bcf | bellard | if (!T0)
|
509 | cf495bcf | bellard | env->psr |= PSR_ZERO; |
510 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
511 | cf495bcf | bellard | env->psr |= PSR_NEG; |
512 | cf495bcf | bellard | if (src1 < T1)
|
513 | cf495bcf | bellard | env->psr |= PSR_CARRY; |
514 | cf495bcf | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
515 | cf495bcf | bellard | env->psr |= PSR_OVF; |
516 | 3475187d | bellard | #endif
|
517 | af7bf89b | bellard | FORCE_RET(); |
518 | af7bf89b | bellard | } |
519 | af7bf89b | bellard | |
520 | af7bf89b | bellard | void OPPROTO op_subx_T1_T0(void) |
521 | af7bf89b | bellard | { |
522 | af7bf89b | bellard | T0 -= T1 + FLAG_SET(PSR_CARRY); |
523 | af7bf89b | bellard | } |
524 | af7bf89b | bellard | |
525 | af7bf89b | bellard | void OPPROTO op_subx_T1_T0_cc(void) |
526 | af7bf89b | bellard | { |
527 | af7bf89b | bellard | target_ulong src1; |
528 | af7bf89b | bellard | src1 = T0; |
529 | b854608e | bellard | if (FLAG_SET(PSR_CARRY))
|
530 | b854608e | bellard | { |
531 | b854608e | bellard | T0 -= T1 + 1;
|
532 | b854608e | bellard | env->psr = 0;
|
533 | b854608e | bellard | #ifdef TARGET_SPARC64
|
534 | b854608e | bellard | if ((src1 & 0xffffffff) <= (T1 & 0xffffffff)) |
535 | b854608e | bellard | env->psr |= PSR_CARRY; |
536 | b854608e | bellard | env->xcc = 0;
|
537 | b854608e | bellard | if (src1 <= T1)
|
538 | b854608e | bellard | env->xcc |= PSR_CARRY; |
539 | b854608e | bellard | #else
|
540 | b854608e | bellard | if (src1 <= T1)
|
541 | b854608e | bellard | env->psr |= PSR_CARRY; |
542 | b854608e | bellard | #endif
|
543 | b854608e | bellard | } |
544 | b854608e | bellard | else
|
545 | b854608e | bellard | { |
546 | b854608e | bellard | T0 -= T1; |
547 | b854608e | bellard | env->psr = 0;
|
548 | b854608e | bellard | #ifdef TARGET_SPARC64
|
549 | b854608e | bellard | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
550 | b854608e | bellard | env->psr |= PSR_CARRY; |
551 | b854608e | bellard | env->xcc = 0;
|
552 | b854608e | bellard | if (src1 < T1)
|
553 | b854608e | bellard | env->xcc |= PSR_CARRY; |
554 | b854608e | bellard | #else
|
555 | b854608e | bellard | if (src1 < T1)
|
556 | b854608e | bellard | env->psr |= PSR_CARRY; |
557 | b854608e | bellard | #endif
|
558 | b854608e | bellard | } |
559 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
560 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
561 | 3475187d | bellard | env->psr |= PSR_ZERO; |
562 | 3475187d | bellard | if ((int32_t) T0 < 0) |
563 | 3475187d | bellard | env->psr |= PSR_NEG; |
564 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
565 | 3475187d | bellard | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
566 | 3475187d | bellard | env->psr |= PSR_OVF; |
567 | 3475187d | bellard | |
568 | 3475187d | bellard | if (!T0)
|
569 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
570 | 3475187d | bellard | if ((int64_t) T0 < 0) |
571 | 3475187d | bellard | env->xcc |= PSR_NEG; |
572 | 3475187d | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) |
573 | 3475187d | bellard | env->xcc |= PSR_OVF; |
574 | 3475187d | bellard | #else
|
575 | af7bf89b | bellard | if (!T0)
|
576 | af7bf89b | bellard | env->psr |= PSR_ZERO; |
577 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
578 | af7bf89b | bellard | env->psr |= PSR_NEG; |
579 | af7bf89b | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
580 | af7bf89b | bellard | env->psr |= PSR_OVF; |
581 | 3475187d | bellard | #endif
|
582 | cf495bcf | bellard | FORCE_RET(); |
583 | 7a3f1944 | bellard | } |
584 | 7a3f1944 | bellard | |
585 | cf495bcf | bellard | void OPPROTO op_and_T1_T0(void) |
586 | 7a3f1944 | bellard | { |
587 | cf495bcf | bellard | T0 &= T1; |
588 | 7a3f1944 | bellard | } |
589 | 7a3f1944 | bellard | |
590 | cf495bcf | bellard | void OPPROTO op_or_T1_T0(void) |
591 | 7a3f1944 | bellard | { |
592 | cf495bcf | bellard | T0 |= T1; |
593 | 7a3f1944 | bellard | } |
594 | 7a3f1944 | bellard | |
595 | cf495bcf | bellard | void OPPROTO op_xor_T1_T0(void) |
596 | 7a3f1944 | bellard | { |
597 | cf495bcf | bellard | T0 ^= T1; |
598 | 7a3f1944 | bellard | } |
599 | 7a3f1944 | bellard | |
600 | cf495bcf | bellard | void OPPROTO op_andn_T1_T0(void) |
601 | 7a3f1944 | bellard | { |
602 | cf495bcf | bellard | T0 &= ~T1; |
603 | 7a3f1944 | bellard | } |
604 | 7a3f1944 | bellard | |
605 | cf495bcf | bellard | void OPPROTO op_orn_T1_T0(void) |
606 | 7a3f1944 | bellard | { |
607 | cf495bcf | bellard | T0 |= ~T1; |
608 | 7a3f1944 | bellard | } |
609 | 7a3f1944 | bellard | |
610 | cf495bcf | bellard | void OPPROTO op_xnor_T1_T0(void) |
611 | 7a3f1944 | bellard | { |
612 | cf495bcf | bellard | T0 ^= ~T1; |
613 | 7a3f1944 | bellard | } |
614 | 7a3f1944 | bellard | |
615 | cf495bcf | bellard | void OPPROTO op_umul_T1_T0(void) |
616 | 7a3f1944 | bellard | { |
617 | cf495bcf | bellard | uint64_t res; |
618 | af7bf89b | bellard | res = (uint64_t) T0 * (uint64_t) T1; |
619 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
620 | 83469015 | bellard | T0 = res; |
621 | 83469015 | bellard | #else
|
622 | cf495bcf | bellard | T0 = res & 0xffffffff;
|
623 | 83469015 | bellard | #endif
|
624 | cf495bcf | bellard | env->y = res >> 32;
|
625 | 7a3f1944 | bellard | } |
626 | 7a3f1944 | bellard | |
627 | cf495bcf | bellard | void OPPROTO op_smul_T1_T0(void) |
628 | 7a3f1944 | bellard | { |
629 | cf495bcf | bellard | uint64_t res; |
630 | cf495bcf | bellard | res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1); |
631 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
632 | 83469015 | bellard | T0 = res; |
633 | 83469015 | bellard | #else
|
634 | cf495bcf | bellard | T0 = res & 0xffffffff;
|
635 | 83469015 | bellard | #endif
|
636 | cf495bcf | bellard | env->y = res >> 32;
|
637 | 7a3f1944 | bellard | } |
638 | 7a3f1944 | bellard | |
639 | cf495bcf | bellard | void OPPROTO op_mulscc_T1_T0(void) |
640 | 7a3f1944 | bellard | { |
641 | af7bf89b | bellard | unsigned int b1, N, V, b2; |
642 | af7bf89b | bellard | target_ulong src1; |
643 | af7bf89b | bellard | |
644 | 4e8b5da2 | bellard | N = FLAG_SET(PSR_NEG); |
645 | cf495bcf | bellard | V = FLAG_SET(PSR_OVF); |
646 | 4e8b5da2 | bellard | b1 = N ^ V; |
647 | cf495bcf | bellard | b2 = T0 & 1;
|
648 | cf495bcf | bellard | T0 = (b1 << 31) | (T0 >> 1); |
649 | cf495bcf | bellard | if (!(env->y & 1)) |
650 | cf495bcf | bellard | T1 = 0;
|
651 | cf495bcf | bellard | /* do addition and update flags */
|
652 | cf495bcf | bellard | src1 = T0; |
653 | cf495bcf | bellard | T0 += T1; |
654 | cf495bcf | bellard | env->psr = 0;
|
655 | cf495bcf | bellard | if (!T0)
|
656 | cf495bcf | bellard | env->psr |= PSR_ZERO; |
657 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
658 | cf495bcf | bellard | env->psr |= PSR_NEG; |
659 | cf495bcf | bellard | if (T0 < src1)
|
660 | cf495bcf | bellard | env->psr |= PSR_CARRY; |
661 | cf495bcf | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
662 | cf495bcf | bellard | env->psr |= PSR_OVF; |
663 | cf495bcf | bellard | env->y = (b2 << 31) | (env->y >> 1); |
664 | cf495bcf | bellard | FORCE_RET(); |
665 | cf495bcf | bellard | } |
666 | cf495bcf | bellard | |
667 | cf495bcf | bellard | void OPPROTO op_udiv_T1_T0(void) |
668 | cf495bcf | bellard | { |
669 | cf495bcf | bellard | uint64_t x0; |
670 | cf495bcf | bellard | uint32_t x1; |
671 | cf495bcf | bellard | |
672 | cf495bcf | bellard | x0 = T0 | ((uint64_t) (env->y) << 32);
|
673 | cf495bcf | bellard | x1 = T1; |
674 | cf495bcf | bellard | x0 = x0 / x1; |
675 | cf495bcf | bellard | if (x0 > 0xffffffff) { |
676 | cf495bcf | bellard | T0 = 0xffffffff;
|
677 | cf495bcf | bellard | T1 = 1;
|
678 | cf495bcf | bellard | } else {
|
679 | cf495bcf | bellard | T0 = x0; |
680 | cf495bcf | bellard | T1 = 0;
|
681 | cf495bcf | bellard | } |
682 | cf495bcf | bellard | FORCE_RET(); |
683 | 7a3f1944 | bellard | } |
684 | 7a3f1944 | bellard | |
685 | cf495bcf | bellard | void OPPROTO op_sdiv_T1_T0(void) |
686 | 7a3f1944 | bellard | { |
687 | cf495bcf | bellard | int64_t x0; |
688 | cf495bcf | bellard | int32_t x1; |
689 | cf495bcf | bellard | |
690 | af7bf89b | bellard | x0 = T0 | ((int64_t) (env->y) << 32);
|
691 | cf495bcf | bellard | x1 = T1; |
692 | cf495bcf | bellard | x0 = x0 / x1; |
693 | cf495bcf | bellard | if ((int32_t) x0 != x0) {
|
694 | af7bf89b | bellard | T0 = x0 < 0? 0x80000000: 0x7fffffff; |
695 | cf495bcf | bellard | T1 = 1;
|
696 | cf495bcf | bellard | } else {
|
697 | cf495bcf | bellard | T0 = x0; |
698 | cf495bcf | bellard | T1 = 0;
|
699 | cf495bcf | bellard | } |
700 | cf495bcf | bellard | FORCE_RET(); |
701 | 7a3f1944 | bellard | } |
702 | 7a3f1944 | bellard | |
703 | cf495bcf | bellard | void OPPROTO op_div_cc(void) |
704 | 7a3f1944 | bellard | { |
705 | cf495bcf | bellard | env->psr = 0;
|
706 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
707 | 3475187d | bellard | if (!T0)
|
708 | 3475187d | bellard | env->psr |= PSR_ZERO; |
709 | 3475187d | bellard | if ((int32_t) T0 < 0) |
710 | 3475187d | bellard | env->psr |= PSR_NEG; |
711 | 3475187d | bellard | if (T1)
|
712 | 3475187d | bellard | env->psr |= PSR_OVF; |
713 | 3475187d | bellard | |
714 | 3475187d | bellard | env->xcc = 0;
|
715 | 3475187d | bellard | if (!T0)
|
716 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
717 | 3475187d | bellard | if ((int64_t) T0 < 0) |
718 | 3475187d | bellard | env->xcc |= PSR_NEG; |
719 | 3475187d | bellard | #else
|
720 | cf495bcf | bellard | if (!T0)
|
721 | cf495bcf | bellard | env->psr |= PSR_ZERO; |
722 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
723 | cf495bcf | bellard | env->psr |= PSR_NEG; |
724 | cf495bcf | bellard | if (T1)
|
725 | cf495bcf | bellard | env->psr |= PSR_OVF; |
726 | 3475187d | bellard | #endif
|
727 | cf495bcf | bellard | FORCE_RET(); |
728 | 7a3f1944 | bellard | } |
729 | 7a3f1944 | bellard | |
730 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
731 | 3475187d | bellard | void OPPROTO op_mulx_T1_T0(void) |
732 | 3475187d | bellard | { |
733 | 3475187d | bellard | T0 *= T1; |
734 | 3475187d | bellard | FORCE_RET(); |
735 | 3475187d | bellard | } |
736 | 3475187d | bellard | |
737 | 3475187d | bellard | void OPPROTO op_udivx_T1_T0(void) |
738 | 3475187d | bellard | { |
739 | 3475187d | bellard | T0 /= T1; |
740 | 3475187d | bellard | FORCE_RET(); |
741 | 3475187d | bellard | } |
742 | 3475187d | bellard | |
743 | 3475187d | bellard | void OPPROTO op_sdivx_T1_T0(void) |
744 | 3475187d | bellard | { |
745 | 3475187d | bellard | if (T0 == INT64_MIN && T1 == -1) |
746 | 3475187d | bellard | T0 = INT64_MIN; |
747 | 3475187d | bellard | else
|
748 | 3475187d | bellard | T0 /= (target_long) T1; |
749 | 3475187d | bellard | FORCE_RET(); |
750 | 3475187d | bellard | } |
751 | 3475187d | bellard | #endif
|
752 | 3475187d | bellard | |
753 | cf495bcf | bellard | void OPPROTO op_logic_T0_cc(void) |
754 | 7a3f1944 | bellard | { |
755 | cf495bcf | bellard | env->psr = 0;
|
756 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
757 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
758 | 3475187d | bellard | env->psr |= PSR_ZERO; |
759 | 3475187d | bellard | if ((int32_t) T0 < 0) |
760 | 3475187d | bellard | env->psr |= PSR_NEG; |
761 | 3475187d | bellard | |
762 | 3475187d | bellard | env->xcc = 0;
|
763 | 3475187d | bellard | if (!T0)
|
764 | 3475187d | bellard | env->xcc |= PSR_ZERO; |
765 | 3475187d | bellard | if ((int64_t) T0 < 0) |
766 | 3475187d | bellard | env->xcc |= PSR_NEG; |
767 | 3475187d | bellard | #else
|
768 | cf495bcf | bellard | if (!T0)
|
769 | cf495bcf | bellard | env->psr |= PSR_ZERO; |
770 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
771 | cf495bcf | bellard | env->psr |= PSR_NEG; |
772 | 3475187d | bellard | #endif
|
773 | cf495bcf | bellard | FORCE_RET(); |
774 | 7a3f1944 | bellard | } |
775 | 7a3f1944 | bellard | |
776 | cf495bcf | bellard | void OPPROTO op_sll(void) |
777 | 7a3f1944 | bellard | { |
778 | cf495bcf | bellard | T0 <<= T1; |
779 | 7a3f1944 | bellard | } |
780 | 7a3f1944 | bellard | |
781 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
782 | 3475187d | bellard | void OPPROTO op_srl(void) |
783 | 3475187d | bellard | { |
784 | 3475187d | bellard | T0 = (T0 & 0xffffffff) >> T1;
|
785 | 3475187d | bellard | } |
786 | 3475187d | bellard | |
787 | 3475187d | bellard | void OPPROTO op_srlx(void) |
788 | 3475187d | bellard | { |
789 | 3475187d | bellard | T0 >>= T1; |
790 | 3475187d | bellard | } |
791 | 3475187d | bellard | |
792 | 3475187d | bellard | void OPPROTO op_sra(void) |
793 | 3475187d | bellard | { |
794 | 3475187d | bellard | T0 = ((int32_t) (T0 & 0xffffffff)) >> T1;
|
795 | 3475187d | bellard | } |
796 | 3475187d | bellard | |
797 | 3475187d | bellard | void OPPROTO op_srax(void) |
798 | 3475187d | bellard | { |
799 | 3475187d | bellard | T0 = ((int64_t) T0) >> T1; |
800 | 3475187d | bellard | } |
801 | 3475187d | bellard | #else
|
802 | cf495bcf | bellard | void OPPROTO op_srl(void) |
803 | 7a3f1944 | bellard | { |
804 | cf495bcf | bellard | T0 >>= T1; |
805 | 7a3f1944 | bellard | } |
806 | 7a3f1944 | bellard | |
807 | cf495bcf | bellard | void OPPROTO op_sra(void) |
808 | 7a3f1944 | bellard | { |
809 | cf495bcf | bellard | T0 = ((int32_t) T0) >> T1; |
810 | 7a3f1944 | bellard | } |
811 | 3475187d | bellard | #endif
|
812 | 7a3f1944 | bellard | |
813 | e8af50a3 | bellard | /* Load and store */
|
814 | e8af50a3 | bellard | #define MEMSUFFIX _raw
|
815 | e8af50a3 | bellard | #include "op_mem.h" |
816 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
817 | e8af50a3 | bellard | #define MEMSUFFIX _user
|
818 | e8af50a3 | bellard | #include "op_mem.h" |
819 | e8af50a3 | bellard | |
820 | e8af50a3 | bellard | #define MEMSUFFIX _kernel
|
821 | e8af50a3 | bellard | #include "op_mem.h" |
822 | e8af50a3 | bellard | #endif
|
823 | e8af50a3 | bellard | |
824 | e8af50a3 | bellard | void OPPROTO op_ldfsr(void) |
825 | e8af50a3 | bellard | { |
826 | 3475187d | bellard | PUT_FSR32(env, *((uint32_t *) &FT0)); |
827 | 8d5f07fa | bellard | helper_ldfsr(); |
828 | e8af50a3 | bellard | } |
829 | e8af50a3 | bellard | |
830 | e8af50a3 | bellard | void OPPROTO op_stfsr(void) |
831 | e8af50a3 | bellard | { |
832 | 3475187d | bellard | *((uint32_t *) &FT0) = GET_FSR32(env); |
833 | e8af50a3 | bellard | } |
834 | e8af50a3 | bellard | |
835 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
836 | 3475187d | bellard | void OPPROTO op_rdpsr(void) |
837 | 7a3f1944 | bellard | { |
838 | 3475187d | bellard | do_rdpsr(); |
839 | 7a3f1944 | bellard | } |
840 | 7a3f1944 | bellard | |
841 | 3475187d | bellard | void OPPROTO op_wrpsr(void) |
842 | 7a3f1944 | bellard | { |
843 | 3475187d | bellard | do_wrpsr(); |
844 | 3475187d | bellard | FORCE_RET(); |
845 | 7a3f1944 | bellard | } |
846 | 7a3f1944 | bellard | |
847 | 3475187d | bellard | void OPPROTO op_rett(void) |
848 | cf495bcf | bellard | { |
849 | 3475187d | bellard | helper_rett(); |
850 | 3475187d | bellard | FORCE_RET(); |
851 | e8af50a3 | bellard | } |
852 | e8af50a3 | bellard | |
853 | 3475187d | bellard | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
854 | 3475187d | bellard | handling ? */
|
855 | 3475187d | bellard | void OPPROTO op_save(void) |
856 | e8af50a3 | bellard | { |
857 | 3475187d | bellard | uint32_t cwp; |
858 | 3475187d | bellard | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
859 | 3475187d | bellard | if (env->wim & (1 << cwp)) { |
860 | 3475187d | bellard | raise_exception(TT_WIN_OVF); |
861 | 3475187d | bellard | } |
862 | 3475187d | bellard | set_cwp(cwp); |
863 | e8af50a3 | bellard | FORCE_RET(); |
864 | e8af50a3 | bellard | } |
865 | e8af50a3 | bellard | |
866 | 3475187d | bellard | void OPPROTO op_restore(void) |
867 | e8af50a3 | bellard | { |
868 | 3475187d | bellard | uint32_t cwp; |
869 | 3475187d | bellard | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
870 | 3475187d | bellard | if (env->wim & (1 << cwp)) { |
871 | 3475187d | bellard | raise_exception(TT_WIN_UNF); |
872 | 3475187d | bellard | } |
873 | 3475187d | bellard | set_cwp(cwp); |
874 | 3475187d | bellard | FORCE_RET(); |
875 | 3475187d | bellard | } |
876 | 3475187d | bellard | #else
|
877 | 3475187d | bellard | void OPPROTO op_rdccr(void) |
878 | 3475187d | bellard | { |
879 | 3475187d | bellard | T0 = GET_CCR(env); |
880 | e8af50a3 | bellard | } |
881 | e8af50a3 | bellard | |
882 | 3475187d | bellard | void OPPROTO op_wrccr(void) |
883 | e8af50a3 | bellard | { |
884 | 3475187d | bellard | PUT_CCR(env, T0); |
885 | e8af50a3 | bellard | } |
886 | e8af50a3 | bellard | |
887 | 3475187d | bellard | void OPPROTO op_rdtick(void) |
888 | e8af50a3 | bellard | { |
889 | 3475187d | bellard | T0 = 0; // XXX read cycle counter and bit 31 |
890 | e8af50a3 | bellard | } |
891 | cf495bcf | bellard | |
892 | 3475187d | bellard | void OPPROTO op_wrtick(void) |
893 | 7a3f1944 | bellard | { |
894 | 3475187d | bellard | // XXX write cycle counter and bit 31
|
895 | 7a3f1944 | bellard | } |
896 | 7a3f1944 | bellard | |
897 | 3475187d | bellard | void OPPROTO op_rdtpc(void) |
898 | cf495bcf | bellard | { |
899 | 3475187d | bellard | T0 = env->tpc[env->tl]; |
900 | 3475187d | bellard | } |
901 | 3475187d | bellard | |
902 | 3475187d | bellard | void OPPROTO op_wrtpc(void) |
903 | 3475187d | bellard | { |
904 | 3475187d | bellard | env->tpc[env->tl] = T0; |
905 | 3475187d | bellard | } |
906 | 3475187d | bellard | |
907 | 3475187d | bellard | void OPPROTO op_rdtnpc(void) |
908 | 3475187d | bellard | { |
909 | 3475187d | bellard | T0 = env->tnpc[env->tl]; |
910 | 3475187d | bellard | } |
911 | 3475187d | bellard | |
912 | 3475187d | bellard | void OPPROTO op_wrtnpc(void) |
913 | 3475187d | bellard | { |
914 | 3475187d | bellard | env->tnpc[env->tl] = T0; |
915 | 3475187d | bellard | } |
916 | 3475187d | bellard | |
917 | 3475187d | bellard | void OPPROTO op_rdtstate(void) |
918 | 3475187d | bellard | { |
919 | 3475187d | bellard | T0 = env->tstate[env->tl]; |
920 | 3475187d | bellard | } |
921 | 3475187d | bellard | |
922 | 3475187d | bellard | void OPPROTO op_wrtstate(void) |
923 | 3475187d | bellard | { |
924 | 3475187d | bellard | env->tstate[env->tl] = T0; |
925 | 3475187d | bellard | } |
926 | 3475187d | bellard | |
927 | 3475187d | bellard | void OPPROTO op_rdtt(void) |
928 | 3475187d | bellard | { |
929 | 3475187d | bellard | T0 = env->tt[env->tl]; |
930 | 3475187d | bellard | } |
931 | 3475187d | bellard | |
932 | 3475187d | bellard | void OPPROTO op_wrtt(void) |
933 | 3475187d | bellard | { |
934 | 3475187d | bellard | env->tt[env->tl] = T0; |
935 | 3475187d | bellard | } |
936 | 3475187d | bellard | |
937 | 3475187d | bellard | void OPPROTO op_rdpstate(void) |
938 | 3475187d | bellard | { |
939 | 3475187d | bellard | T0 = env->pstate; |
940 | 3475187d | bellard | } |
941 | 3475187d | bellard | |
942 | 3475187d | bellard | void OPPROTO op_wrpstate(void) |
943 | 3475187d | bellard | { |
944 | 83469015 | bellard | do_wrpstate(); |
945 | 3475187d | bellard | } |
946 | 3475187d | bellard | |
947 | 3475187d | bellard | // CWP handling is reversed in V9, but we still use the V8 register
|
948 | 3475187d | bellard | // order.
|
949 | 3475187d | bellard | void OPPROTO op_rdcwp(void) |
950 | 3475187d | bellard | { |
951 | 3475187d | bellard | T0 = NWINDOWS - 1 - env->cwp;
|
952 | 3475187d | bellard | } |
953 | 3475187d | bellard | |
954 | 3475187d | bellard | void OPPROTO op_wrcwp(void) |
955 | 3475187d | bellard | { |
956 | 3475187d | bellard | env->cwp = NWINDOWS - 1 - T0;
|
957 | cf495bcf | bellard | } |
958 | 7a3f1944 | bellard | |
959 | cf495bcf | bellard | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
960 | cf495bcf | bellard | handling ? */
|
961 | cf495bcf | bellard | void OPPROTO op_save(void) |
962 | 7a3f1944 | bellard | { |
963 | af7bf89b | bellard | uint32_t cwp; |
964 | cf495bcf | bellard | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
965 | 3475187d | bellard | if (env->cansave == 0) { |
966 | 3475187d | bellard | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
967 | 3475187d | bellard | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
968 | 3475187d | bellard | ((env->wstate & 0x7) << 2))); |
969 | 3475187d | bellard | } else {
|
970 | 3475187d | bellard | if (env->cleanwin - env->canrestore == 0) { |
971 | 3475187d | bellard | // XXX Clean windows without trap
|
972 | 3475187d | bellard | raise_exception(TT_CLRWIN); |
973 | 3475187d | bellard | } else {
|
974 | 3475187d | bellard | env->cansave--; |
975 | 3475187d | bellard | env->canrestore++; |
976 | 3475187d | bellard | set_cwp(cwp); |
977 | 3475187d | bellard | } |
978 | cf495bcf | bellard | } |
979 | cf495bcf | bellard | FORCE_RET(); |
980 | 7a3f1944 | bellard | } |
981 | 7a3f1944 | bellard | |
982 | cf495bcf | bellard | void OPPROTO op_restore(void) |
983 | 7a3f1944 | bellard | { |
984 | af7bf89b | bellard | uint32_t cwp; |
985 | cf495bcf | bellard | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
986 | 3475187d | bellard | if (env->canrestore == 0) { |
987 | 3475187d | bellard | raise_exception(TT_FILL | (env->otherwin != 0 ?
|
988 | 3475187d | bellard | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
989 | 3475187d | bellard | ((env->wstate & 0x7) << 2))); |
990 | 3475187d | bellard | } else {
|
991 | 3475187d | bellard | env->cansave++; |
992 | 3475187d | bellard | env->canrestore--; |
993 | 3475187d | bellard | set_cwp(cwp); |
994 | cf495bcf | bellard | } |
995 | cf495bcf | bellard | FORCE_RET(); |
996 | 7a3f1944 | bellard | } |
997 | 3475187d | bellard | #endif
|
998 | 7a3f1944 | bellard | |
999 | cf495bcf | bellard | void OPPROTO op_exception(void) |
1000 | 7a3f1944 | bellard | { |
1001 | cf495bcf | bellard | env->exception_index = PARAM1; |
1002 | cf495bcf | bellard | cpu_loop_exit(); |
1003 | 7a3f1944 | bellard | } |
1004 | 7a3f1944 | bellard | |
1005 | cf495bcf | bellard | void OPPROTO op_trap_T0(void) |
1006 | 7a3f1944 | bellard | { |
1007 | cf495bcf | bellard | env->exception_index = TT_TRAP + (T0 & 0x7f);
|
1008 | cf495bcf | bellard | cpu_loop_exit(); |
1009 | 7a3f1944 | bellard | } |
1010 | 7a3f1944 | bellard | |
1011 | cf495bcf | bellard | void OPPROTO op_trapcc_T0(void) |
1012 | 7a3f1944 | bellard | { |
1013 | cf495bcf | bellard | if (T2) {
|
1014 | cf495bcf | bellard | env->exception_index = TT_TRAP + (T0 & 0x7f);
|
1015 | cf495bcf | bellard | cpu_loop_exit(); |
1016 | cf495bcf | bellard | } |
1017 | cf495bcf | bellard | FORCE_RET(); |
1018 | 7a3f1944 | bellard | } |
1019 | 7a3f1944 | bellard | |
1020 | e80cfcfc | bellard | void OPPROTO op_trap_ifnofpu(void) |
1021 | e80cfcfc | bellard | { |
1022 | e80cfcfc | bellard | if (!env->psref) {
|
1023 | e80cfcfc | bellard | env->exception_index = TT_NFPU_INSN; |
1024 | e80cfcfc | bellard | cpu_loop_exit(); |
1025 | e80cfcfc | bellard | } |
1026 | e80cfcfc | bellard | FORCE_RET(); |
1027 | e80cfcfc | bellard | } |
1028 | e80cfcfc | bellard | |
1029 | e80cfcfc | bellard | void OPPROTO op_fpexception_im(void) |
1030 | e8af50a3 | bellard | { |
1031 | e80cfcfc | bellard | env->exception_index = TT_FP_EXCP; |
1032 | e80cfcfc | bellard | env->fsr &= ~FSR_FTT_MASK; |
1033 | e80cfcfc | bellard | env->fsr |= PARAM1; |
1034 | e8af50a3 | bellard | cpu_loop_exit(); |
1035 | e80cfcfc | bellard | FORCE_RET(); |
1036 | e80cfcfc | bellard | } |
1037 | e80cfcfc | bellard | |
1038 | e80cfcfc | bellard | void OPPROTO op_debug(void) |
1039 | e80cfcfc | bellard | { |
1040 | e80cfcfc | bellard | helper_debug(); |
1041 | e8af50a3 | bellard | } |
1042 | e8af50a3 | bellard | |
1043 | cf495bcf | bellard | void OPPROTO op_exit_tb(void) |
1044 | 7a3f1944 | bellard | { |
1045 | cf495bcf | bellard | EXIT_TB(); |
1046 | 7a3f1944 | bellard | } |
1047 | 7a3f1944 | bellard | |
1048 | 3475187d | bellard | void OPPROTO op_eval_ba(void) |
1049 | 3475187d | bellard | { |
1050 | 3475187d | bellard | T2 = 1;
|
1051 | 3475187d | bellard | } |
1052 | 3475187d | bellard | |
1053 | cf495bcf | bellard | void OPPROTO op_eval_be(void) |
1054 | 7a3f1944 | bellard | { |
1055 | af7bf89b | bellard | T2 = FLAG_SET(PSR_ZERO); |
1056 | 7a3f1944 | bellard | } |
1057 | 7a3f1944 | bellard | |
1058 | cf495bcf | bellard | void OPPROTO op_eval_ble(void) |
1059 | 7a3f1944 | bellard | { |
1060 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
1061 | 612b477d | bellard | |
1062 | cf495bcf | bellard | T2 = Z | (N ^ V); |
1063 | 7a3f1944 | bellard | } |
1064 | 7a3f1944 | bellard | |
1065 | cf495bcf | bellard | void OPPROTO op_eval_bl(void) |
1066 | 7a3f1944 | bellard | { |
1067 | af7bf89b | bellard | target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
1068 | 612b477d | bellard | |
1069 | cf495bcf | bellard | T2 = N ^ V; |
1070 | 7a3f1944 | bellard | } |
1071 | 7a3f1944 | bellard | |
1072 | cf495bcf | bellard | void OPPROTO op_eval_bleu(void) |
1073 | 7a3f1944 | bellard | { |
1074 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY); |
1075 | 612b477d | bellard | |
1076 | cf495bcf | bellard | T2 = C | Z; |
1077 | 7a3f1944 | bellard | } |
1078 | 7a3f1944 | bellard | |
1079 | cf495bcf | bellard | void OPPROTO op_eval_bcs(void) |
1080 | 7a3f1944 | bellard | { |
1081 | af7bf89b | bellard | T2 = FLAG_SET(PSR_CARRY); |
1082 | 7a3f1944 | bellard | } |
1083 | 7a3f1944 | bellard | |
1084 | cf495bcf | bellard | void OPPROTO op_eval_bvs(void) |
1085 | 7a3f1944 | bellard | { |
1086 | af7bf89b | bellard | T2 = FLAG_SET(PSR_OVF); |
1087 | 7a3f1944 | bellard | } |
1088 | 7a3f1944 | bellard | |
1089 | 3475187d | bellard | void OPPROTO op_eval_bn(void) |
1090 | 3475187d | bellard | { |
1091 | 3475187d | bellard | T2 = 0;
|
1092 | 3475187d | bellard | } |
1093 | 3475187d | bellard | |
1094 | cf495bcf | bellard | void OPPROTO op_eval_bneg(void) |
1095 | 7a3f1944 | bellard | { |
1096 | af7bf89b | bellard | T2 = FLAG_SET(PSR_NEG); |
1097 | 7a3f1944 | bellard | } |
1098 | 7a3f1944 | bellard | |
1099 | cf495bcf | bellard | void OPPROTO op_eval_bne(void) |
1100 | 7a3f1944 | bellard | { |
1101 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_ZERO); |
1102 | 7a3f1944 | bellard | } |
1103 | 7a3f1944 | bellard | |
1104 | cf495bcf | bellard | void OPPROTO op_eval_bg(void) |
1105 | 7a3f1944 | bellard | { |
1106 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
1107 | 612b477d | bellard | |
1108 | cf495bcf | bellard | T2 = !(Z | (N ^ V)); |
1109 | 7a3f1944 | bellard | } |
1110 | 7a3f1944 | bellard | |
1111 | cf495bcf | bellard | void OPPROTO op_eval_bge(void) |
1112 | 7a3f1944 | bellard | { |
1113 | af7bf89b | bellard | target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
1114 | 612b477d | bellard | |
1115 | cf495bcf | bellard | T2 = !(N ^ V); |
1116 | 7a3f1944 | bellard | } |
1117 | 7a3f1944 | bellard | |
1118 | cf495bcf | bellard | void OPPROTO op_eval_bgu(void) |
1119 | 7a3f1944 | bellard | { |
1120 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY); |
1121 | 612b477d | bellard | |
1122 | cf495bcf | bellard | T2 = !(C | Z); |
1123 | 7a3f1944 | bellard | } |
1124 | 7a3f1944 | bellard | |
1125 | cf495bcf | bellard | void OPPROTO op_eval_bcc(void) |
1126 | 7a3f1944 | bellard | { |
1127 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_CARRY); |
1128 | 7a3f1944 | bellard | } |
1129 | 7a3f1944 | bellard | |
1130 | cf495bcf | bellard | void OPPROTO op_eval_bpos(void) |
1131 | cf495bcf | bellard | { |
1132 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_NEG); |
1133 | cf495bcf | bellard | } |
1134 | cf495bcf | bellard | |
1135 | cf495bcf | bellard | void OPPROTO op_eval_bvc(void) |
1136 | cf495bcf | bellard | { |
1137 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_OVF); |
1138 | cf495bcf | bellard | } |
1139 | cf495bcf | bellard | |
1140 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1141 | 3475187d | bellard | void OPPROTO op_eval_xbe(void) |
1142 | 3475187d | bellard | { |
1143 | 3475187d | bellard | T2 = XFLAG_SET(PSR_ZERO); |
1144 | 3475187d | bellard | } |
1145 | e8af50a3 | bellard | |
1146 | 3475187d | bellard | void OPPROTO op_eval_xble(void) |
1147 | e8af50a3 | bellard | { |
1148 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
1149 | 3475187d | bellard | |
1150 | 3475187d | bellard | T2 = Z | (N ^ V); |
1151 | e8af50a3 | bellard | } |
1152 | e8af50a3 | bellard | |
1153 | 3475187d | bellard | void OPPROTO op_eval_xbl(void) |
1154 | e8af50a3 | bellard | { |
1155 | 3475187d | bellard | target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
1156 | 3475187d | bellard | |
1157 | 3475187d | bellard | T2 = N ^ V; |
1158 | e8af50a3 | bellard | } |
1159 | e8af50a3 | bellard | |
1160 | 3475187d | bellard | void OPPROTO op_eval_xbleu(void) |
1161 | e8af50a3 | bellard | { |
1162 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); |
1163 | 3475187d | bellard | |
1164 | 3475187d | bellard | T2 = C | Z; |
1165 | e8af50a3 | bellard | } |
1166 | e8af50a3 | bellard | |
1167 | 3475187d | bellard | void OPPROTO op_eval_xbcs(void) |
1168 | e8af50a3 | bellard | { |
1169 | 3475187d | bellard | T2 = XFLAG_SET(PSR_CARRY); |
1170 | e8af50a3 | bellard | } |
1171 | e8af50a3 | bellard | |
1172 | 3475187d | bellard | void OPPROTO op_eval_xbvs(void) |
1173 | e8af50a3 | bellard | { |
1174 | 3475187d | bellard | T2 = XFLAG_SET(PSR_OVF); |
1175 | e8af50a3 | bellard | } |
1176 | e8af50a3 | bellard | |
1177 | 3475187d | bellard | void OPPROTO op_eval_xbneg(void) |
1178 | e8af50a3 | bellard | { |
1179 | 3475187d | bellard | T2 = XFLAG_SET(PSR_NEG); |
1180 | e8af50a3 | bellard | } |
1181 | e8af50a3 | bellard | |
1182 | 3475187d | bellard | void OPPROTO op_eval_xbne(void) |
1183 | e8af50a3 | bellard | { |
1184 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_ZERO); |
1185 | e8af50a3 | bellard | } |
1186 | e8af50a3 | bellard | |
1187 | 3475187d | bellard | void OPPROTO op_eval_xbg(void) |
1188 | e8af50a3 | bellard | { |
1189 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
1190 | 3475187d | bellard | |
1191 | 3475187d | bellard | T2 = !(Z | (N ^ V)); |
1192 | e8af50a3 | bellard | } |
1193 | e8af50a3 | bellard | |
1194 | 3475187d | bellard | void OPPROTO op_eval_xbge(void) |
1195 | e8af50a3 | bellard | { |
1196 | 3475187d | bellard | target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
1197 | 3475187d | bellard | |
1198 | 3475187d | bellard | T2 = !(N ^ V); |
1199 | 3475187d | bellard | } |
1200 | 3475187d | bellard | |
1201 | 3475187d | bellard | void OPPROTO op_eval_xbgu(void) |
1202 | 3475187d | bellard | { |
1203 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); |
1204 | 3475187d | bellard | |
1205 | 3475187d | bellard | T2 = !(C | Z); |
1206 | 3475187d | bellard | } |
1207 | 3475187d | bellard | |
1208 | 3475187d | bellard | void OPPROTO op_eval_xbcc(void) |
1209 | 3475187d | bellard | { |
1210 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_CARRY); |
1211 | 3475187d | bellard | } |
1212 | 3475187d | bellard | |
1213 | 3475187d | bellard | void OPPROTO op_eval_xbpos(void) |
1214 | 3475187d | bellard | { |
1215 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_NEG); |
1216 | 3475187d | bellard | } |
1217 | 3475187d | bellard | |
1218 | 3475187d | bellard | void OPPROTO op_eval_xbvc(void) |
1219 | 3475187d | bellard | { |
1220 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_OVF); |
1221 | 3475187d | bellard | } |
1222 | 3475187d | bellard | #endif
|
1223 | 3475187d | bellard | |
1224 | 3475187d | bellard | #define FCC
|
1225 | 3475187d | bellard | #define FFLAG_SET(x) (env->fsr & x? 1: 0) |
1226 | 3475187d | bellard | #include "fbranch_template.h" |
1227 | 3475187d | bellard | |
1228 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1229 | 3475187d | bellard | #define FCC _fcc1
|
1230 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0) |
1231 | 3475187d | bellard | #include "fbranch_template.h" |
1232 | 3475187d | bellard | #define FCC _fcc2
|
1233 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0) |
1234 | 3475187d | bellard | #include "fbranch_template.h" |
1235 | 3475187d | bellard | #define FCC _fcc3
|
1236 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0) |
1237 | 3475187d | bellard | #include "fbranch_template.h" |
1238 | 3475187d | bellard | #endif
|
1239 | 3475187d | bellard | |
1240 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1241 | 3475187d | bellard | void OPPROTO op_eval_brz(void) |
1242 | 3475187d | bellard | { |
1243 | 83469015 | bellard | T2 = (T0 == 0);
|
1244 | e8af50a3 | bellard | } |
1245 | e8af50a3 | bellard | |
1246 | 3475187d | bellard | void OPPROTO op_eval_brnz(void) |
1247 | e8af50a3 | bellard | { |
1248 | 83469015 | bellard | T2 = (T0 != 0);
|
1249 | e8af50a3 | bellard | } |
1250 | e8af50a3 | bellard | |
1251 | 3475187d | bellard | void OPPROTO op_eval_brlz(void) |
1252 | e8af50a3 | bellard | { |
1253 | 3475187d | bellard | T2 = ((int64_t)T0 < 0);
|
1254 | e8af50a3 | bellard | } |
1255 | e8af50a3 | bellard | |
1256 | 3475187d | bellard | void OPPROTO op_eval_brlez(void) |
1257 | e8af50a3 | bellard | { |
1258 | 3475187d | bellard | T2 = ((int64_t)T0 <= 0);
|
1259 | e8af50a3 | bellard | } |
1260 | e8af50a3 | bellard | |
1261 | 3475187d | bellard | void OPPROTO op_eval_brgz(void) |
1262 | e8af50a3 | bellard | { |
1263 | 3475187d | bellard | T2 = ((int64_t)T0 > 0);
|
1264 | e8af50a3 | bellard | } |
1265 | e8af50a3 | bellard | |
1266 | 3475187d | bellard | void OPPROTO op_eval_brgez(void) |
1267 | e8af50a3 | bellard | { |
1268 | 3475187d | bellard | T2 = ((int64_t)T0 >= 0);
|
1269 | e8af50a3 | bellard | } |
1270 | e8af50a3 | bellard | |
1271 | 3475187d | bellard | void OPPROTO op_jmp_im64(void) |
1272 | 3475187d | bellard | { |
1273 | 3475187d | bellard | env->pc = PARAMQ1; |
1274 | 3475187d | bellard | } |
1275 | 3475187d | bellard | |
1276 | 3475187d | bellard | void OPPROTO op_movq_npc_im64(void) |
1277 | 3475187d | bellard | { |
1278 | 3475187d | bellard | env->npc = PARAMQ1; |
1279 | 3475187d | bellard | } |
1280 | 3475187d | bellard | #endif
|
1281 | 3475187d | bellard | |
1282 | cf495bcf | bellard | void OPPROTO op_jmp_im(void) |
1283 | cf495bcf | bellard | { |
1284 | 3475187d | bellard | env->pc = (uint32_t)PARAM1; |
1285 | cf495bcf | bellard | } |
1286 | cf495bcf | bellard | |
1287 | cf495bcf | bellard | void OPPROTO op_movl_npc_im(void) |
1288 | cf495bcf | bellard | { |
1289 | 3475187d | bellard | env->npc = (uint32_t)PARAM1; |
1290 | cf495bcf | bellard | } |
1291 | 7a3f1944 | bellard | |
1292 | cf495bcf | bellard | void OPPROTO op_movl_npc_T0(void) |
1293 | 7a3f1944 | bellard | { |
1294 | cf495bcf | bellard | env->npc = T0; |
1295 | 7a3f1944 | bellard | } |
1296 | 7a3f1944 | bellard | |
1297 | 0bee699e | bellard | void OPPROTO op_mov_pc_npc(void) |
1298 | 0bee699e | bellard | { |
1299 | 0bee699e | bellard | env->pc = env->npc; |
1300 | 0bee699e | bellard | } |
1301 | 0bee699e | bellard | |
1302 | cf495bcf | bellard | void OPPROTO op_next_insn(void) |
1303 | 7a3f1944 | bellard | { |
1304 | cf495bcf | bellard | env->pc = env->npc; |
1305 | cf495bcf | bellard | env->npc = env->npc + 4;
|
1306 | 7a3f1944 | bellard | } |
1307 | 7a3f1944 | bellard | |
1308 | 83469015 | bellard | void OPPROTO op_goto_tb0(void) |
1309 | 72cbca10 | bellard | { |
1310 | 83469015 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
1311 | 72cbca10 | bellard | } |
1312 | 72cbca10 | bellard | |
1313 | 83469015 | bellard | void OPPROTO op_goto_tb1(void) |
1314 | 7a3f1944 | bellard | { |
1315 | 83469015 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
1316 | 72cbca10 | bellard | } |
1317 | 72cbca10 | bellard | |
1318 | 83469015 | bellard | void OPPROTO op_jmp_label(void) |
1319 | 72cbca10 | bellard | { |
1320 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
1321 | 83469015 | bellard | } |
1322 | 83469015 | bellard | |
1323 | 83469015 | bellard | void OPPROTO op_jnz_T2_label(void) |
1324 | 83469015 | bellard | { |
1325 | 83469015 | bellard | if (T2)
|
1326 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
1327 | cf495bcf | bellard | FORCE_RET(); |
1328 | 7a3f1944 | bellard | } |
1329 | 7a3f1944 | bellard | |
1330 | 83469015 | bellard | void OPPROTO op_jz_T2_label(void) |
1331 | 7a3f1944 | bellard | { |
1332 | 83469015 | bellard | if (!T2)
|
1333 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
1334 | cf495bcf | bellard | FORCE_RET(); |
1335 | 7a3f1944 | bellard | } |
1336 | 72cbca10 | bellard | |
1337 | 658138bc | bellard | void OPPROTO op_flush_T0(void) |
1338 | 658138bc | bellard | { |
1339 | 658138bc | bellard | helper_flush(T0); |
1340 | 658138bc | bellard | } |
1341 | e8af50a3 | bellard | |
1342 | 65ce8c2f | bellard | #define F_OP(name, p) void OPPROTO op_f##name##p(void) |
1343 | 65ce8c2f | bellard | |
1344 | 65ce8c2f | bellard | #define F_BINOP(name) \
|
1345 | 65ce8c2f | bellard | F_OP(name, s) \ |
1346 | 65ce8c2f | bellard | { \ |
1347 | 65ce8c2f | bellard | FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \ |
1348 | 65ce8c2f | bellard | } \ |
1349 | 65ce8c2f | bellard | F_OP(name, d) \ |
1350 | 65ce8c2f | bellard | { \ |
1351 | 65ce8c2f | bellard | DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ |
1352 | 65ce8c2f | bellard | } |
1353 | e8af50a3 | bellard | |
1354 | 65ce8c2f | bellard | F_BINOP(add); |
1355 | 65ce8c2f | bellard | F_BINOP(sub); |
1356 | 65ce8c2f | bellard | F_BINOP(mul); |
1357 | 65ce8c2f | bellard | F_BINOP(div); |
1358 | 65ce8c2f | bellard | #undef F_BINOP
|
1359 | e8af50a3 | bellard | |
1360 | e8af50a3 | bellard | void OPPROTO op_fsmuld(void) |
1361 | e8af50a3 | bellard | { |
1362 | 65ce8c2f | bellard | DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status), |
1363 | 65ce8c2f | bellard | float32_to_float64(FT1, &env->fp_status), |
1364 | 65ce8c2f | bellard | &env->fp_status); |
1365 | e8af50a3 | bellard | } |
1366 | e8af50a3 | bellard | |
1367 | 65ce8c2f | bellard | #define F_HELPER(name) \
|
1368 | 65ce8c2f | bellard | F_OP(name, s) \ |
1369 | 65ce8c2f | bellard | { \ |
1370 | 65ce8c2f | bellard | do_f##name##s(); \ |
1371 | 65ce8c2f | bellard | } \ |
1372 | 65ce8c2f | bellard | F_OP(name, d) \ |
1373 | 65ce8c2f | bellard | { \ |
1374 | 65ce8c2f | bellard | do_f##name##d(); \ |
1375 | 65ce8c2f | bellard | } |
1376 | e8af50a3 | bellard | |
1377 | 65ce8c2f | bellard | F_HELPER(sqrt); |
1378 | e8af50a3 | bellard | |
1379 | 65ce8c2f | bellard | F_OP(neg, s) |
1380 | e8af50a3 | bellard | { |
1381 | 65ce8c2f | bellard | FT0 = float32_chs(FT1); |
1382 | e8af50a3 | bellard | } |
1383 | e8af50a3 | bellard | |
1384 | 65ce8c2f | bellard | F_OP(abs, s) |
1385 | e8af50a3 | bellard | { |
1386 | 65ce8c2f | bellard | do_fabss(); |
1387 | e8af50a3 | bellard | } |
1388 | e8af50a3 | bellard | |
1389 | 65ce8c2f | bellard | F_HELPER(cmp); |
1390 | e8af50a3 | bellard | |
1391 | 65ce8c2f | bellard | #ifdef TARGET_SPARC64
|
1392 | 65ce8c2f | bellard | F_OP(neg, d) |
1393 | e8af50a3 | bellard | { |
1394 | 65ce8c2f | bellard | DT0 = float64_chs(DT1); |
1395 | e8af50a3 | bellard | } |
1396 | e8af50a3 | bellard | |
1397 | 65ce8c2f | bellard | F_OP(abs, d) |
1398 | e8af50a3 | bellard | { |
1399 | 65ce8c2f | bellard | do_fabsd(); |
1400 | e8af50a3 | bellard | } |
1401 | e8af50a3 | bellard | |
1402 | 3475187d | bellard | void OPPROTO op_fcmps_fcc1(void) |
1403 | 3475187d | bellard | { |
1404 | 3475187d | bellard | do_fcmps_fcc1(); |
1405 | 3475187d | bellard | } |
1406 | 3475187d | bellard | |
1407 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc1(void) |
1408 | 3475187d | bellard | { |
1409 | 3475187d | bellard | do_fcmpd_fcc1(); |
1410 | 3475187d | bellard | } |
1411 | 3475187d | bellard | |
1412 | 3475187d | bellard | void OPPROTO op_fcmps_fcc2(void) |
1413 | 3475187d | bellard | { |
1414 | 3475187d | bellard | do_fcmps_fcc2(); |
1415 | 3475187d | bellard | } |
1416 | 3475187d | bellard | |
1417 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc2(void) |
1418 | 3475187d | bellard | { |
1419 | 3475187d | bellard | do_fcmpd_fcc2(); |
1420 | 3475187d | bellard | } |
1421 | 3475187d | bellard | |
1422 | 3475187d | bellard | void OPPROTO op_fcmps_fcc3(void) |
1423 | 3475187d | bellard | { |
1424 | 3475187d | bellard | do_fcmps_fcc3(); |
1425 | 3475187d | bellard | } |
1426 | 3475187d | bellard | |
1427 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc3(void) |
1428 | 3475187d | bellard | { |
1429 | 3475187d | bellard | do_fcmpd_fcc3(); |
1430 | 3475187d | bellard | } |
1431 | 3475187d | bellard | #endif
|
1432 | 3475187d | bellard | |
1433 | 65ce8c2f | bellard | /* Integer to float conversion. */
|
1434 | a0c4cb4a | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
|
1435 | 65ce8c2f | bellard | F_HELPER(ito); |
1436 | a0c4cb4a | bellard | #else
|
1437 | 65ce8c2f | bellard | F_OP(ito, s) |
1438 | a0c4cb4a | bellard | { |
1439 | 65ce8c2f | bellard | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
1440 | e8af50a3 | bellard | } |
1441 | e8af50a3 | bellard | |
1442 | 65ce8c2f | bellard | F_OP(ito, d) |
1443 | e8af50a3 | bellard | { |
1444 | 65ce8c2f | bellard | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
1445 | e8af50a3 | bellard | } |
1446 | 3475187d | bellard | |
1447 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1448 | 65ce8c2f | bellard | F_OP(xto, s) |
1449 | 3475187d | bellard | { |
1450 | 65ce8c2f | bellard | FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
1451 | 3475187d | bellard | } |
1452 | 3475187d | bellard | |
1453 | 65ce8c2f | bellard | F_OP(xto, d) |
1454 | 3475187d | bellard | { |
1455 | 65ce8c2f | bellard | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
1456 | 3475187d | bellard | } |
1457 | 3475187d | bellard | #endif
|
1458 | a0c4cb4a | bellard | #endif
|
1459 | 65ce8c2f | bellard | #undef F_HELPER
|
1460 | a0c4cb4a | bellard | |
1461 | 65ce8c2f | bellard | /* floating point conversion */
|
1462 | a0c4cb4a | bellard | void OPPROTO op_fdtos(void) |
1463 | a0c4cb4a | bellard | { |
1464 | 65ce8c2f | bellard | FT0 = float64_to_float32(DT1, &env->fp_status); |
1465 | a0c4cb4a | bellard | } |
1466 | e8af50a3 | bellard | |
1467 | e8af50a3 | bellard | void OPPROTO op_fstod(void) |
1468 | e8af50a3 | bellard | { |
1469 | 65ce8c2f | bellard | DT0 = float32_to_float64(FT1, &env->fp_status); |
1470 | e8af50a3 | bellard | } |
1471 | e8af50a3 | bellard | |
1472 | 65ce8c2f | bellard | /* Float to integer conversion. */
|
1473 | e8af50a3 | bellard | void OPPROTO op_fstoi(void) |
1474 | e8af50a3 | bellard | { |
1475 | 65ce8c2f | bellard | *((int32_t *)&FT0) = float32_to_int32(FT1, &env->fp_status); |
1476 | e8af50a3 | bellard | } |
1477 | e8af50a3 | bellard | |
1478 | e8af50a3 | bellard | void OPPROTO op_fdtoi(void) |
1479 | e8af50a3 | bellard | { |
1480 | 65ce8c2f | bellard | *((int32_t *)&FT0) = float64_to_int32(DT1, &env->fp_status); |
1481 | e8af50a3 | bellard | } |
1482 | e8af50a3 | bellard | |
1483 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1484 | 3475187d | bellard | void OPPROTO op_fstox(void) |
1485 | 3475187d | bellard | { |
1486 | 65ce8c2f | bellard | *((int64_t *)&DT0) = float32_to_int64(FT1, &env->fp_status); |
1487 | 3475187d | bellard | } |
1488 | 3475187d | bellard | |
1489 | 3475187d | bellard | void OPPROTO op_fdtox(void) |
1490 | 3475187d | bellard | { |
1491 | 65ce8c2f | bellard | *((int64_t *)&DT0) = float64_to_int64(DT1, &env->fp_status); |
1492 | 3475187d | bellard | } |
1493 | 3475187d | bellard | |
1494 | 3475187d | bellard | void OPPROTO op_fmovs_cc(void) |
1495 | 3475187d | bellard | { |
1496 | 3475187d | bellard | if (T2)
|
1497 | 3475187d | bellard | FT0 = FT1; |
1498 | 3475187d | bellard | } |
1499 | 3475187d | bellard | |
1500 | 3475187d | bellard | void OPPROTO op_fmovd_cc(void) |
1501 | 3475187d | bellard | { |
1502 | 3475187d | bellard | if (T2)
|
1503 | 3475187d | bellard | DT0 = DT1; |
1504 | 3475187d | bellard | } |
1505 | 3475187d | bellard | |
1506 | 3475187d | bellard | void OPPROTO op_mov_cc(void) |
1507 | 3475187d | bellard | { |
1508 | 3475187d | bellard | if (T2)
|
1509 | 3475187d | bellard | T0 = T1; |
1510 | 3475187d | bellard | } |
1511 | 3475187d | bellard | |
1512 | 3475187d | bellard | void OPPROTO op_flushw(void) |
1513 | 3475187d | bellard | { |
1514 | 3475187d | bellard | if (env->cansave != NWINDOWS - 2) { |
1515 | 3475187d | bellard | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
1516 | 3475187d | bellard | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
1517 | 3475187d | bellard | ((env->wstate & 0x7) << 2))); |
1518 | 3475187d | bellard | } |
1519 | 3475187d | bellard | } |
1520 | 3475187d | bellard | |
1521 | 3475187d | bellard | void OPPROTO op_saved(void) |
1522 | 3475187d | bellard | { |
1523 | 3475187d | bellard | env->cansave++; |
1524 | 3475187d | bellard | if (env->otherwin == 0) |
1525 | 3475187d | bellard | env->canrestore--; |
1526 | 3475187d | bellard | } |
1527 | 3475187d | bellard | |
1528 | 3475187d | bellard | void OPPROTO op_restored(void) |
1529 | 3475187d | bellard | { |
1530 | 3475187d | bellard | env->canrestore++; |
1531 | 3475187d | bellard | if (env->cleanwin < NWINDOWS - 1) |
1532 | 3475187d | bellard | env->cleanwin++; |
1533 | 3475187d | bellard | if (env->otherwin == 0) |
1534 | 3475187d | bellard | env->cansave--; |
1535 | 3475187d | bellard | else
|
1536 | 3475187d | bellard | env->otherwin--; |
1537 | 3475187d | bellard | } |
1538 | 3475187d | bellard | |
1539 | 3475187d | bellard | void OPPROTO op_popc(void) |
1540 | 3475187d | bellard | { |
1541 | 3475187d | bellard | do_popc(); |
1542 | 3475187d | bellard | } |
1543 | 3475187d | bellard | |
1544 | 3475187d | bellard | void OPPROTO op_done(void) |
1545 | 3475187d | bellard | { |
1546 | 83469015 | bellard | do_done(); |
1547 | 3475187d | bellard | } |
1548 | 3475187d | bellard | |
1549 | 3475187d | bellard | void OPPROTO op_retry(void) |
1550 | 3475187d | bellard | { |
1551 | 83469015 | bellard | do_retry(); |
1552 | 3475187d | bellard | } |
1553 | 3475187d | bellard | |
1554 | 3475187d | bellard | void OPPROTO op_sir(void) |
1555 | 3475187d | bellard | { |
1556 | 3475187d | bellard | // XXX
|
1557 | 3475187d | bellard | |
1558 | 3475187d | bellard | } |
1559 | 3475187d | bellard | |
1560 | 3475187d | bellard | void OPPROTO op_ld_asi_reg()
|
1561 | 3475187d | bellard | { |
1562 | 3475187d | bellard | T0 += PARAM1; |
1563 | 3475187d | bellard | helper_ld_asi(env->asi, PARAM2, PARAM3); |
1564 | 3475187d | bellard | } |
1565 | 3475187d | bellard | |
1566 | 3475187d | bellard | void OPPROTO op_st_asi_reg()
|
1567 | 3475187d | bellard | { |
1568 | 3475187d | bellard | T0 += PARAM1; |
1569 | 3475187d | bellard | helper_st_asi(env->asi, PARAM2, PARAM3); |
1570 | 3475187d | bellard | } |
1571 | 3475187d | bellard | #endif
|
1572 | 3475187d | bellard | |
1573 | e8af50a3 | bellard | void OPPROTO op_ld_asi()
|
1574 | e8af50a3 | bellard | { |
1575 | e8af50a3 | bellard | helper_ld_asi(PARAM1, PARAM2, PARAM3); |
1576 | e8af50a3 | bellard | } |
1577 | e8af50a3 | bellard | |
1578 | e8af50a3 | bellard | void OPPROTO op_st_asi()
|
1579 | e8af50a3 | bellard | { |
1580 | e8af50a3 | bellard | helper_st_asi(PARAM1, PARAM2, PARAM3); |
1581 | e8af50a3 | bellard | } |