root / target-mips / op_helper.c @ 483dcf53
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 6af0bf9c | bellard | #include "exec.h" |
21 | 6af0bf9c | bellard | |
22 | 6af0bf9c | bellard | #define MIPS_DEBUG_DISAS
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23 | 6af0bf9c | bellard | |
24 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
25 | 4ad40f36 | bellard | |
26 | 6af0bf9c | bellard | /*****************************************************************************/
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27 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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28 | 6af0bf9c | bellard | void cpu_loop_exit(void) |
29 | 6af0bf9c | bellard | { |
30 | 6af0bf9c | bellard | longjmp(env->jmp_env, 1);
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31 | 6af0bf9c | bellard | } |
32 | 6af0bf9c | bellard | |
33 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
34 | 6af0bf9c | bellard | { |
35 | 6af0bf9c | bellard | #if 1 |
36 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
37 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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38 | 6af0bf9c | bellard | #endif
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39 | 6af0bf9c | bellard | env->exception_index = exception; |
40 | 6af0bf9c | bellard | env->error_code = error_code; |
41 | 6af0bf9c | bellard | T0 = 0;
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42 | 6af0bf9c | bellard | cpu_loop_exit(); |
43 | 6af0bf9c | bellard | } |
44 | 6af0bf9c | bellard | |
45 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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46 | 6af0bf9c | bellard | { |
47 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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48 | 6af0bf9c | bellard | } |
49 | 6af0bf9c | bellard | |
50 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
51 | 4ad40f36 | bellard | { |
52 | 4ad40f36 | bellard | TranslationBlock *tb; |
53 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
54 | 4ad40f36 | bellard | |
55 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
56 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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57 | 4ad40f36 | bellard | } |
58 | 4ad40f36 | bellard | |
59 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception)
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60 | 4ad40f36 | bellard | { |
61 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
62 | 4ad40f36 | bellard | do_raise_exception_err (exception, 0);
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63 | 4ad40f36 | bellard | } |
64 | 4ad40f36 | bellard | |
65 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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66 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
67 | 6af0bf9c | bellard | #undef MEMSUFFIX
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68 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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69 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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70 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
71 | 6af0bf9c | bellard | #undef MEMSUFFIX
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72 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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73 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
74 | 6af0bf9c | bellard | #undef MEMSUFFIX
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75 | 6af0bf9c | bellard | #endif
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76 | 6af0bf9c | bellard | |
77 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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78 | 6af0bf9c | bellard | #if (HOST_LONG_BITS == 32) |
79 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
80 | 6af0bf9c | bellard | { |
81 | 6af0bf9c | bellard | return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; |
82 | 6af0bf9c | bellard | } |
83 | 6af0bf9c | bellard | |
84 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
85 | 6af0bf9c | bellard | { |
86 | 6af0bf9c | bellard | env->LO = HILO & 0xFFFFFFFF;
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87 | 6af0bf9c | bellard | env->HI = HILO >> 32;
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88 | 6af0bf9c | bellard | } |
89 | 6af0bf9c | bellard | |
90 | 6af0bf9c | bellard | void do_mult (void) |
91 | 6af0bf9c | bellard | { |
92 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
93 | 6af0bf9c | bellard | } |
94 | 6af0bf9c | bellard | |
95 | 6af0bf9c | bellard | void do_multu (void) |
96 | 6af0bf9c | bellard | { |
97 | 6af0bf9c | bellard | set_HILO((uint64_t)T0 * (uint64_t)T1); |
98 | 6af0bf9c | bellard | } |
99 | 6af0bf9c | bellard | |
100 | 6af0bf9c | bellard | void do_madd (void) |
101 | 6af0bf9c | bellard | { |
102 | 6af0bf9c | bellard | int64_t tmp; |
103 | 6af0bf9c | bellard | |
104 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
105 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
106 | 6af0bf9c | bellard | } |
107 | 6af0bf9c | bellard | |
108 | 6af0bf9c | bellard | void do_maddu (void) |
109 | 6af0bf9c | bellard | { |
110 | 6af0bf9c | bellard | uint64_t tmp; |
111 | 6af0bf9c | bellard | |
112 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
113 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
114 | 6af0bf9c | bellard | } |
115 | 6af0bf9c | bellard | |
116 | 6af0bf9c | bellard | void do_msub (void) |
117 | 6af0bf9c | bellard | { |
118 | 6af0bf9c | bellard | int64_t tmp; |
119 | 6af0bf9c | bellard | |
120 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
121 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
122 | 6af0bf9c | bellard | } |
123 | 6af0bf9c | bellard | |
124 | 6af0bf9c | bellard | void do_msubu (void) |
125 | 6af0bf9c | bellard | { |
126 | 6af0bf9c | bellard | uint64_t tmp; |
127 | 6af0bf9c | bellard | |
128 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
129 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
130 | 6af0bf9c | bellard | } |
131 | 6af0bf9c | bellard | #endif
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132 | 6af0bf9c | bellard | |
133 | 048f6b4d | bellard | #if defined(CONFIG_USER_ONLY)
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134 | 048f6b4d | bellard | void do_mfc0 (int reg, int sel) |
135 | 048f6b4d | bellard | { |
136 | 048f6b4d | bellard | cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel);
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137 | 048f6b4d | bellard | } |
138 | 048f6b4d | bellard | void do_mtc0 (int reg, int sel) |
139 | 048f6b4d | bellard | { |
140 | 048f6b4d | bellard | cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel);
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141 | 048f6b4d | bellard | } |
142 | 048f6b4d | bellard | |
143 | 048f6b4d | bellard | void do_tlbwi (void) |
144 | 048f6b4d | bellard | { |
145 | 048f6b4d | bellard | cpu_abort(env, "tlbwi\n");
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146 | 048f6b4d | bellard | } |
147 | 048f6b4d | bellard | |
148 | 048f6b4d | bellard | void do_tlbwr (void) |
149 | 048f6b4d | bellard | { |
150 | 048f6b4d | bellard | cpu_abort(env, "tlbwr\n");
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151 | 048f6b4d | bellard | } |
152 | 048f6b4d | bellard | |
153 | 048f6b4d | bellard | void do_tlbp (void) |
154 | 048f6b4d | bellard | { |
155 | 048f6b4d | bellard | cpu_abort(env, "tlbp\n");
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156 | 048f6b4d | bellard | } |
157 | 048f6b4d | bellard | |
158 | 048f6b4d | bellard | void do_tlbr (void) |
159 | 048f6b4d | bellard | { |
160 | 048f6b4d | bellard | cpu_abort(env, "tlbr\n");
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161 | 048f6b4d | bellard | } |
162 | 048f6b4d | bellard | #else
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163 | 048f6b4d | bellard | |
164 | 6af0bf9c | bellard | /* CP0 helpers */
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165 | 6af0bf9c | bellard | void do_mfc0 (int reg, int sel) |
166 | 6af0bf9c | bellard | { |
167 | 6af0bf9c | bellard | const unsigned char *rn; |
168 | 6af0bf9c | bellard | |
169 | 6af0bf9c | bellard | if (sel != 0 && reg != 16 && reg != 28) { |
170 | 6af0bf9c | bellard | rn = "invalid";
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171 | 6af0bf9c | bellard | goto print;
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172 | 6af0bf9c | bellard | } |
173 | 6af0bf9c | bellard | switch (reg) {
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174 | 6af0bf9c | bellard | case 0: |
175 | 6af0bf9c | bellard | T0 = env->CP0_index; |
176 | 6af0bf9c | bellard | rn = "Index";
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177 | 6af0bf9c | bellard | break;
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178 | 6af0bf9c | bellard | case 1: |
179 | 6af0bf9c | bellard | T0 = cpu_mips_get_random(env); |
180 | 6af0bf9c | bellard | rn = "Random";
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181 | 6af0bf9c | bellard | break;
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182 | 6af0bf9c | bellard | case 2: |
183 | 6af0bf9c | bellard | T0 = env->CP0_EntryLo0; |
184 | 6af0bf9c | bellard | rn = "EntryLo0";
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185 | 6af0bf9c | bellard | break;
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186 | 6af0bf9c | bellard | case 3: |
187 | 6af0bf9c | bellard | T0 = env->CP0_EntryLo1; |
188 | 6af0bf9c | bellard | rn = "EntryLo1";
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189 | 6af0bf9c | bellard | break;
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190 | 6af0bf9c | bellard | case 4: |
191 | 6af0bf9c | bellard | T0 = env->CP0_Context; |
192 | 6af0bf9c | bellard | rn = "Context";
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193 | 6af0bf9c | bellard | break;
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194 | 6af0bf9c | bellard | case 5: |
195 | 6af0bf9c | bellard | T0 = env->CP0_PageMask; |
196 | 6af0bf9c | bellard | rn = "PageMask";
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197 | 6af0bf9c | bellard | break;
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198 | 6af0bf9c | bellard | case 6: |
199 | 6af0bf9c | bellard | T0 = env->CP0_Wired; |
200 | 6af0bf9c | bellard | rn = "Wired";
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201 | 6af0bf9c | bellard | break;
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202 | 6af0bf9c | bellard | case 8: |
203 | 6af0bf9c | bellard | T0 = env->CP0_BadVAddr; |
204 | 6af0bf9c | bellard | rn = "BadVaddr";
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205 | 6af0bf9c | bellard | break;
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206 | 6af0bf9c | bellard | case 9: |
207 | 6af0bf9c | bellard | T0 = cpu_mips_get_count(env); |
208 | 6af0bf9c | bellard | rn = "Count";
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209 | 6af0bf9c | bellard | break;
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210 | 6af0bf9c | bellard | case 10: |
211 | 6af0bf9c | bellard | T0 = env->CP0_EntryHi; |
212 | 6af0bf9c | bellard | rn = "EntryHi";
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213 | 6af0bf9c | bellard | break;
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214 | 6af0bf9c | bellard | case 11: |
215 | 6af0bf9c | bellard | T0 = env->CP0_Compare; |
216 | 6af0bf9c | bellard | rn = "Compare";
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217 | 6af0bf9c | bellard | break;
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218 | 6af0bf9c | bellard | case 12: |
219 | 6af0bf9c | bellard | T0 = env->CP0_Status; |
220 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_UM)
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221 | 90b37806 | bellard | T0 |= (1 << CP0St_UM);
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222 | 6af0bf9c | bellard | rn = "Status";
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223 | 6af0bf9c | bellard | break;
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224 | 6af0bf9c | bellard | case 13: |
225 | 6af0bf9c | bellard | T0 = env->CP0_Cause; |
226 | 6af0bf9c | bellard | rn = "Cause";
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227 | 6af0bf9c | bellard | break;
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228 | 6af0bf9c | bellard | case 14: |
229 | 6af0bf9c | bellard | T0 = env->CP0_EPC; |
230 | 6af0bf9c | bellard | rn = "EPC";
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231 | 6af0bf9c | bellard | break;
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232 | 6af0bf9c | bellard | case 15: |
233 | 6af0bf9c | bellard | T0 = env->CP0_PRid; |
234 | 6af0bf9c | bellard | rn = "PRid";
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235 | 6af0bf9c | bellard | break;
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236 | 6af0bf9c | bellard | case 16: |
237 | 6af0bf9c | bellard | switch (sel) {
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238 | 6af0bf9c | bellard | case 0: |
239 | 6af0bf9c | bellard | T0 = env->CP0_Config0; |
240 | 6af0bf9c | bellard | rn = "Config";
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241 | 6af0bf9c | bellard | break;
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242 | 6af0bf9c | bellard | case 1: |
243 | 6af0bf9c | bellard | T0 = env->CP0_Config1; |
244 | 6af0bf9c | bellard | rn = "Config1";
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245 | 6af0bf9c | bellard | break;
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246 | 6af0bf9c | bellard | default:
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247 | 6af0bf9c | bellard | rn = "Unknown config register";
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248 | 6af0bf9c | bellard | break;
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249 | 6af0bf9c | bellard | } |
250 | 6af0bf9c | bellard | break;
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251 | 6af0bf9c | bellard | case 17: |
252 | 6af0bf9c | bellard | T0 = env->CP0_LLAddr >> 4;
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253 | 6af0bf9c | bellard | rn = "LLAddr";
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254 | 6af0bf9c | bellard | break;
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255 | 6af0bf9c | bellard | case 18: |
256 | 6af0bf9c | bellard | T0 = env->CP0_WatchLo; |
257 | 6af0bf9c | bellard | rn = "WatchLo";
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258 | 6af0bf9c | bellard | break;
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259 | 6af0bf9c | bellard | case 19: |
260 | 6af0bf9c | bellard | T0 = env->CP0_WatchHi; |
261 | 6af0bf9c | bellard | rn = "WatchHi";
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262 | 6af0bf9c | bellard | break;
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263 | 6af0bf9c | bellard | case 23: |
264 | 6af0bf9c | bellard | T0 = env->CP0_Debug; |
265 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_DM)
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266 | 6af0bf9c | bellard | T0 |= 1 << CP0DB_DM;
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267 | 6af0bf9c | bellard | rn = "Debug";
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268 | 6af0bf9c | bellard | break;
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269 | 6af0bf9c | bellard | case 24: |
270 | 6af0bf9c | bellard | T0 = env->CP0_DEPC; |
271 | 6af0bf9c | bellard | rn = "DEPC";
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272 | 6af0bf9c | bellard | break;
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273 | 6af0bf9c | bellard | case 28: |
274 | 6af0bf9c | bellard | switch (sel) {
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275 | 6af0bf9c | bellard | case 0: |
276 | 6af0bf9c | bellard | T0 = env->CP0_TagLo; |
277 | 6af0bf9c | bellard | rn = "TagLo";
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278 | 6af0bf9c | bellard | break;
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279 | 6af0bf9c | bellard | case 1: |
280 | 6af0bf9c | bellard | T0 = env->CP0_DataLo; |
281 | 6af0bf9c | bellard | rn = "DataLo";
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282 | 6af0bf9c | bellard | break;
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283 | 6af0bf9c | bellard | default:
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284 | 6af0bf9c | bellard | rn = "unknown sel";
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285 | 6af0bf9c | bellard | break;
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286 | 6af0bf9c | bellard | } |
287 | 6af0bf9c | bellard | break;
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288 | 6af0bf9c | bellard | case 30: |
289 | 6af0bf9c | bellard | T0 = env->CP0_ErrorEPC; |
290 | 6af0bf9c | bellard | rn = "ErrorEPC";
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291 | 6af0bf9c | bellard | break;
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292 | 6af0bf9c | bellard | case 31: |
293 | 6af0bf9c | bellard | T0 = env->CP0_DESAVE; |
294 | 6af0bf9c | bellard | rn = "DESAVE";
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295 | 6af0bf9c | bellard | break;
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296 | 6af0bf9c | bellard | default:
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297 | 6af0bf9c | bellard | rn = "unknown";
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298 | 6af0bf9c | bellard | break;
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299 | 6af0bf9c | bellard | } |
300 | 6af0bf9c | bellard | print:
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301 | 6af0bf9c | bellard | #if defined MIPS_DEBUG_DISAS
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302 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
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303 | 6af0bf9c | bellard | fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
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304 | 6af0bf9c | bellard | env->PC, rn, T0, reg, sel); |
305 | 6af0bf9c | bellard | } |
306 | 6af0bf9c | bellard | #endif
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307 | 6af0bf9c | bellard | return;
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308 | 6af0bf9c | bellard | } |
309 | 6af0bf9c | bellard | |
310 | 6af0bf9c | bellard | void do_mtc0 (int reg, int sel) |
311 | 6af0bf9c | bellard | { |
312 | 6af0bf9c | bellard | const unsigned char *rn; |
313 | 6af0bf9c | bellard | uint32_t val, old, mask; |
314 | 6af0bf9c | bellard | |
315 | 6af0bf9c | bellard | if (sel != 0 && reg != 16 && reg != 28) { |
316 | 6af0bf9c | bellard | val = -1;
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317 | 6af0bf9c | bellard | old = -1;
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318 | 6af0bf9c | bellard | rn = "invalid";
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319 | 6af0bf9c | bellard | goto print;
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320 | 6af0bf9c | bellard | } |
321 | 6af0bf9c | bellard | switch (reg) {
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322 | 6af0bf9c | bellard | case 0: |
323 | 6af0bf9c | bellard | val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); |
324 | 6af0bf9c | bellard | old = env->CP0_index; |
325 | 6af0bf9c | bellard | env->CP0_index = val; |
326 | 6af0bf9c | bellard | rn = "Index";
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327 | 6af0bf9c | bellard | break;
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328 | 6af0bf9c | bellard | case 2: |
329 | 3d9fb9fe | bellard | val = T0 & 0x3FFFFFFF;
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330 | 6af0bf9c | bellard | old = env->CP0_EntryLo0; |
331 | 6af0bf9c | bellard | env->CP0_EntryLo0 = val; |
332 | 6af0bf9c | bellard | rn = "EntryLo0";
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333 | 6af0bf9c | bellard | break;
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334 | 6af0bf9c | bellard | case 3: |
335 | 3d9fb9fe | bellard | val = T0 & 0x3FFFFFFF;
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336 | 6af0bf9c | bellard | old = env->CP0_EntryLo1; |
337 | 6af0bf9c | bellard | env->CP0_EntryLo1 = val; |
338 | 6af0bf9c | bellard | rn = "EntryLo1";
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339 | 6af0bf9c | bellard | break;
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340 | 6af0bf9c | bellard | case 4: |
341 | ba9a74da | bellard | val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0); |
342 | 6af0bf9c | bellard | old = env->CP0_Context; |
343 | 6af0bf9c | bellard | env->CP0_Context = val; |
344 | 6af0bf9c | bellard | rn = "Context";
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345 | 6af0bf9c | bellard | break;
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346 | 6af0bf9c | bellard | case 5: |
347 | 6af0bf9c | bellard | val = T0 & 0x01FFE000;
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348 | 6af0bf9c | bellard | old = env->CP0_PageMask; |
349 | 6af0bf9c | bellard | env->CP0_PageMask = val; |
350 | 6af0bf9c | bellard | rn = "PageMask";
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351 | 6af0bf9c | bellard | break;
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352 | 6af0bf9c | bellard | case 6: |
353 | 6af0bf9c | bellard | val = T0 & 0x0000000F;
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354 | 6af0bf9c | bellard | old = env->CP0_Wired; |
355 | 6af0bf9c | bellard | env->CP0_Wired = val; |
356 | 6af0bf9c | bellard | rn = "Wired";
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357 | 6af0bf9c | bellard | break;
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358 | 6af0bf9c | bellard | case 9: |
359 | 6af0bf9c | bellard | val = T0; |
360 | 6af0bf9c | bellard | old = cpu_mips_get_count(env); |
361 | 6af0bf9c | bellard | cpu_mips_store_count(env, val); |
362 | 6af0bf9c | bellard | rn = "Count";
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363 | 6af0bf9c | bellard | break;
|
364 | 6af0bf9c | bellard | case 10: |
365 | ba9a74da | bellard | val = T0 & 0xFFFFE0FF;
|
366 | 6af0bf9c | bellard | old = env->CP0_EntryHi; |
367 | 6af0bf9c | bellard | env->CP0_EntryHi = val; |
368 | 4ad40f36 | bellard | /* If the ASID changes, flush qemu's TLB. */
|
369 | 4ad40f36 | bellard | if ((old & 0xFF) != (val & 0xFF)) |
370 | 4ad40f36 | bellard | tlb_flush (env, 1);
|
371 | 6af0bf9c | bellard | rn = "EntryHi";
|
372 | 6af0bf9c | bellard | break;
|
373 | 6af0bf9c | bellard | case 11: |
374 | 6af0bf9c | bellard | val = T0; |
375 | 6af0bf9c | bellard | old = env->CP0_Compare; |
376 | 6af0bf9c | bellard | cpu_mips_store_compare(env, val); |
377 | 6af0bf9c | bellard | rn = "Compare";
|
378 | 6af0bf9c | bellard | break;
|
379 | 6af0bf9c | bellard | case 12: |
380 | 6af0bf9c | bellard | val = T0 & 0xFA78FF01;
|
381 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_UM)) |
382 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_UM; |
383 | 6af0bf9c | bellard | else
|
384 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_UM; |
385 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_ERL)) |
386 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_ERL; |
387 | 6af0bf9c | bellard | else
|
388 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_ERL; |
389 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_EXL)) |
390 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_EXL; |
391 | 6af0bf9c | bellard | else
|
392 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_EXL; |
393 | 6af0bf9c | bellard | old = env->CP0_Status; |
394 | 6af0bf9c | bellard | env->CP0_Status = val; |
395 | 6af0bf9c | bellard | /* If we unmasked an asserted IRQ, raise it */
|
396 | ae022501 | bellard | mask = 0x0000FF00;
|
397 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
398 | 6af0bf9c | bellard | fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
|
399 | 6af0bf9c | bellard | old, val, env->CP0_Cause, old & mask, val & mask, |
400 | 6af0bf9c | bellard | env->CP0_Cause & mask); |
401 | 6af0bf9c | bellard | } |
402 | 6af0bf9c | bellard | if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
403 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_EXL) && |
404 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_ERL) && |
405 | 3d9fb9fe | bellard | !(env->hflags & MIPS_HFLAG_DM) && |
406 | e1d9a508 | bellard | (env->CP0_Status & env->CP0_Cause & mask)) { |
407 | 6af0bf9c | bellard | if (logfile)
|
408 | 6af0bf9c | bellard | fprintf(logfile, "Raise pending IRQs\n");
|
409 | 6af0bf9c | bellard | env->interrupt_request |= CPU_INTERRUPT_HARD; |
410 | 3d9fb9fe | bellard | } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) { |
411 | 6af0bf9c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
412 | 6af0bf9c | bellard | } |
413 | 6af0bf9c | bellard | rn = "Status";
|
414 | 6af0bf9c | bellard | break;
|
415 | 6af0bf9c | bellard | case 13: |
416 | 6af0bf9c | bellard | val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
417 | 6af0bf9c | bellard | old = env->CP0_Cause; |
418 | 6af0bf9c | bellard | env->CP0_Cause = val; |
419 | 6af0bf9c | bellard | #if 0
|
420 | e37e863f | bellard | {
|
421 | e37e863f | bellard | int i;
|
422 | e37e863f | bellard | /* Check if we ever asserted a software IRQ */
|
423 | e37e863f | bellard | for (i = 0; i < 2; i++) {
|
424 | e37e863f | bellard | mask = 0x100 << i;
|
425 | e37e863f | bellard | if ((val & mask) & !(old & mask))
|
426 | e37e863f | bellard | mips_set_irq(i);
|
427 | e37e863f | bellard | }
|
428 | 6af0bf9c | bellard | }
|
429 | 6af0bf9c | bellard | #endif
|
430 | 6af0bf9c | bellard | rn = "Cause";
|
431 | 6af0bf9c | bellard | break;
|
432 | 6af0bf9c | bellard | case 14: |
433 | 6af0bf9c | bellard | val = T0; |
434 | 6af0bf9c | bellard | old = env->CP0_EPC; |
435 | 6af0bf9c | bellard | env->CP0_EPC = val; |
436 | 6af0bf9c | bellard | rn = "EPC";
|
437 | 6af0bf9c | bellard | break;
|
438 | 6af0bf9c | bellard | case 16: |
439 | 6af0bf9c | bellard | switch (sel) {
|
440 | 6af0bf9c | bellard | case 0: |
441 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
442 | 6af0bf9c | bellard | val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
443 | 6af0bf9c | bellard | #else
|
444 | 6af0bf9c | bellard | val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); |
445 | 6af0bf9c | bellard | #endif
|
446 | 6af0bf9c | bellard | old = env->CP0_Config0; |
447 | 6af0bf9c | bellard | env->CP0_Config0 = val; |
448 | 6af0bf9c | bellard | rn = "Config0";
|
449 | 6af0bf9c | bellard | break;
|
450 | 6af0bf9c | bellard | default:
|
451 | 6af0bf9c | bellard | val = -1;
|
452 | 6af0bf9c | bellard | old = -1;
|
453 | 6af0bf9c | bellard | rn = "bad config selector";
|
454 | 6af0bf9c | bellard | break;
|
455 | 6af0bf9c | bellard | } |
456 | 6af0bf9c | bellard | break;
|
457 | 6af0bf9c | bellard | case 18: |
458 | 6af0bf9c | bellard | val = T0; |
459 | 6af0bf9c | bellard | old = env->CP0_WatchLo; |
460 | 6af0bf9c | bellard | env->CP0_WatchLo = val; |
461 | 6af0bf9c | bellard | rn = "WatchLo";
|
462 | 6af0bf9c | bellard | break;
|
463 | 6af0bf9c | bellard | case 19: |
464 | 6af0bf9c | bellard | val = T0 & 0x40FF0FF8;
|
465 | 6af0bf9c | bellard | old = env->CP0_WatchHi; |
466 | 6af0bf9c | bellard | env->CP0_WatchHi = val; |
467 | 6af0bf9c | bellard | rn = "WatchHi";
|
468 | 6af0bf9c | bellard | break;
|
469 | 6af0bf9c | bellard | case 23: |
470 | 6af0bf9c | bellard | val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
471 | 6af0bf9c | bellard | if (T0 & (1 << CP0DB_DM)) |
472 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_DM; |
473 | 6af0bf9c | bellard | else
|
474 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_DM; |
475 | 6af0bf9c | bellard | old = env->CP0_Debug; |
476 | 6af0bf9c | bellard | env->CP0_Debug = val; |
477 | 6af0bf9c | bellard | rn = "Debug";
|
478 | 6af0bf9c | bellard | break;
|
479 | 6af0bf9c | bellard | case 24: |
480 | 6af0bf9c | bellard | val = T0; |
481 | 6af0bf9c | bellard | old = env->CP0_DEPC; |
482 | 6af0bf9c | bellard | env->CP0_DEPC = val; |
483 | 6af0bf9c | bellard | rn = "DEPC";
|
484 | 6af0bf9c | bellard | break;
|
485 | 6af0bf9c | bellard | case 28: |
486 | 6af0bf9c | bellard | switch (sel) {
|
487 | 6af0bf9c | bellard | case 0: |
488 | 6af0bf9c | bellard | val = T0 & 0xFFFFFCF6;
|
489 | 6af0bf9c | bellard | old = env->CP0_TagLo; |
490 | 6af0bf9c | bellard | env->CP0_TagLo = val; |
491 | 6af0bf9c | bellard | rn = "TagLo";
|
492 | 6af0bf9c | bellard | break;
|
493 | 6af0bf9c | bellard | default:
|
494 | 6af0bf9c | bellard | val = -1;
|
495 | 6af0bf9c | bellard | old = -1;
|
496 | 6af0bf9c | bellard | rn = "invalid sel";
|
497 | 6af0bf9c | bellard | break;
|
498 | 6af0bf9c | bellard | } |
499 | 6af0bf9c | bellard | break;
|
500 | 6af0bf9c | bellard | case 30: |
501 | 6af0bf9c | bellard | val = T0; |
502 | 6af0bf9c | bellard | old = env->CP0_ErrorEPC; |
503 | 6af0bf9c | bellard | env->CP0_ErrorEPC = val; |
504 | 6af0bf9c | bellard | rn = "EPC";
|
505 | 6af0bf9c | bellard | break;
|
506 | 6af0bf9c | bellard | case 31: |
507 | 6af0bf9c | bellard | val = T0; |
508 | 6af0bf9c | bellard | old = env->CP0_DESAVE; |
509 | 6af0bf9c | bellard | env->CP0_DESAVE = val; |
510 | 6af0bf9c | bellard | rn = "DESAVE";
|
511 | 6af0bf9c | bellard | break;
|
512 | 6af0bf9c | bellard | default:
|
513 | 6af0bf9c | bellard | val = -1;
|
514 | 6af0bf9c | bellard | old = -1;
|
515 | 6af0bf9c | bellard | rn = "unknown";
|
516 | 6af0bf9c | bellard | break;
|
517 | 6af0bf9c | bellard | } |
518 | 6af0bf9c | bellard | print:
|
519 | 6af0bf9c | bellard | #if defined MIPS_DEBUG_DISAS
|
520 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
521 | 6af0bf9c | bellard | fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
|
522 | 6af0bf9c | bellard | env->PC, rn, T0, val, reg, sel, old); |
523 | 6af0bf9c | bellard | } |
524 | 6af0bf9c | bellard | #endif
|
525 | 6af0bf9c | bellard | return;
|
526 | 6af0bf9c | bellard | } |
527 | 6af0bf9c | bellard | |
528 | 6ea83fed | bellard | #ifdef MIPS_USES_FPU
|
529 | 6ea83fed | bellard | #include "softfloat.h" |
530 | 6ea83fed | bellard | |
531 | 6ea83fed | bellard | void fpu_handle_exception(void) |
532 | 6ea83fed | bellard | { |
533 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
534 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status);
|
535 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
536 | 6ea83fed | bellard | |
537 | 6ea83fed | bellard | enable = GET_FP_ENABLE(env->fcr31); |
538 | 6ea83fed | bellard | |
539 | 6ea83fed | bellard | /* determine current flags */
|
540 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
|
541 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
542 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
543 | 6ea83fed | bellard | } |
544 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
|
545 | 6ea83fed | bellard | cpuflags |= FP_DIV0; |
546 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
547 | 6ea83fed | bellard | } |
548 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
|
549 | 6ea83fed | bellard | cpuflags |= FP_OVERFLOW; |
550 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
551 | 6ea83fed | bellard | } |
552 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
|
553 | 6ea83fed | bellard | cpuflags |= FP_UNDERFLOW; |
554 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
555 | 6ea83fed | bellard | } |
556 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
|
557 | 6ea83fed | bellard | cpuflags |= FP_INEXACT; |
558 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
559 | 6ea83fed | bellard | } |
560 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, cpuflags); |
561 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, cause); |
562 | 6ea83fed | bellard | #else
|
563 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, 0);
|
564 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, 0);
|
565 | 6ea83fed | bellard | #endif
|
566 | 6ea83fed | bellard | } |
567 | 6ea83fed | bellard | #endif /* MIPS_USES_FPU */ |
568 | 6ea83fed | bellard | |
569 | 6af0bf9c | bellard | /* TLB management */
|
570 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
571 | 98c1b82b | pbrook | static void invalidate_tlb (int idx) |
572 | 6af0bf9c | bellard | { |
573 | 6af0bf9c | bellard | tlb_t *tlb; |
574 | 98c1b82b | pbrook | target_ulong addr; |
575 | 483dcf53 | pbrook | uint8_t ASID; |
576 | 483dcf53 | pbrook | |
577 | 483dcf53 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
578 | 6af0bf9c | bellard | |
579 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
580 | 483dcf53 | pbrook | /* The qemu TLB is flushed then the ASID changes, so no need to
|
581 | 483dcf53 | pbrook | flush these entries again. */
|
582 | 483dcf53 | pbrook | if (tlb->G == 0 && tlb->ASID != ASID) { |
583 | 483dcf53 | pbrook | return;
|
584 | 483dcf53 | pbrook | } |
585 | 483dcf53 | pbrook | |
586 | 98c1b82b | pbrook | if (tlb->V0) {
|
587 | 98c1b82b | pbrook | tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
|
588 | 4ad40f36 | bellard | addr = tlb->VPN; |
589 | 4ad40f36 | bellard | while (addr < tlb->end) {
|
590 | 4ad40f36 | bellard | tlb_flush_page (env, addr); |
591 | 4ad40f36 | bellard | addr += TARGET_PAGE_SIZE; |
592 | 4ad40f36 | bellard | } |
593 | 6af0bf9c | bellard | } |
594 | 98c1b82b | pbrook | if (tlb->V1) {
|
595 | 98c1b82b | pbrook | tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end);
|
596 | 4ad40f36 | bellard | addr = tlb->end; |
597 | 4ad40f36 | bellard | while (addr < tlb->end2) {
|
598 | 4ad40f36 | bellard | tlb_flush_page (env, addr); |
599 | 4ad40f36 | bellard | addr += TARGET_PAGE_SIZE; |
600 | 4ad40f36 | bellard | } |
601 | 6af0bf9c | bellard | } |
602 | 6af0bf9c | bellard | } |
603 | 6af0bf9c | bellard | |
604 | 98c1b82b | pbrook | static void fill_tlb (int idx) |
605 | 6af0bf9c | bellard | { |
606 | 6af0bf9c | bellard | tlb_t *tlb; |
607 | 6af0bf9c | bellard | int size;
|
608 | 6af0bf9c | bellard | |
609 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
610 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
611 | 6af0bf9c | bellard | tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
|
612 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
613 | 6af0bf9c | bellard | size = env->CP0_PageMask >> 13;
|
614 | 6af0bf9c | bellard | size = 4 * (size + 1); |
615 | 6af0bf9c | bellard | tlb->end = tlb->VPN + (1 << (8 + size)); |
616 | 4ad40f36 | bellard | tlb->end2 = tlb->end + (1 << (8 + size)); |
617 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
618 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
619 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
620 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
621 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
622 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
623 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
624 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
625 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
626 | 6af0bf9c | bellard | } |
627 | 6af0bf9c | bellard | |
628 | 6af0bf9c | bellard | void do_tlbwi (void) |
629 | 6af0bf9c | bellard | { |
630 | 7a962d30 | bellard | /* Wildly undefined effects for CP0_index containing a too high value and
|
631 | 7a962d30 | bellard | MIPS_TLB_NB not being a power of two. But so does real silicon. */
|
632 | 98c1b82b | pbrook | invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
|
633 | 98c1b82b | pbrook | fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
|
634 | 6af0bf9c | bellard | } |
635 | 6af0bf9c | bellard | |
636 | 6af0bf9c | bellard | void do_tlbwr (void) |
637 | 6af0bf9c | bellard | { |
638 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
639 | 6af0bf9c | bellard | |
640 | 98c1b82b | pbrook | invalidate_tlb(r); |
641 | 98c1b82b | pbrook | fill_tlb(r); |
642 | 6af0bf9c | bellard | } |
643 | 6af0bf9c | bellard | |
644 | 6af0bf9c | bellard | void do_tlbp (void) |
645 | 6af0bf9c | bellard | { |
646 | 6af0bf9c | bellard | tlb_t *tlb; |
647 | 6af0bf9c | bellard | target_ulong tag; |
648 | 6af0bf9c | bellard | uint8_t ASID; |
649 | 6af0bf9c | bellard | int i;
|
650 | 6af0bf9c | bellard | |
651 | 3d9fb9fe | bellard | tag = env->CP0_EntryHi & 0xFFFFE000;
|
652 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
653 | 3d9fb9fe | bellard | for (i = 0; i < MIPS_TLB_NB; i++) { |
654 | 6af0bf9c | bellard | tlb = &env->tlb[i]; |
655 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
656 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
657 | 6af0bf9c | bellard | /* TLB match */
|
658 | 6af0bf9c | bellard | env->CP0_index = i; |
659 | 6af0bf9c | bellard | break;
|
660 | 6af0bf9c | bellard | } |
661 | 6af0bf9c | bellard | } |
662 | 7a962d30 | bellard | if (i == MIPS_TLB_NB) {
|
663 | 6af0bf9c | bellard | env->CP0_index |= 0x80000000;
|
664 | 6af0bf9c | bellard | } |
665 | 6af0bf9c | bellard | } |
666 | 6af0bf9c | bellard | |
667 | 6af0bf9c | bellard | void do_tlbr (void) |
668 | 6af0bf9c | bellard | { |
669 | 6af0bf9c | bellard | tlb_t *tlb; |
670 | 09c56b84 | pbrook | uint8_t ASID; |
671 | 6af0bf9c | bellard | int size;
|
672 | 6af0bf9c | bellard | |
673 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
674 | 7a962d30 | bellard | tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
|
675 | 4ad40f36 | bellard | |
676 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
677 | 09c56b84 | pbrook | if (ASID != tlb->ASID && tlb->G != 1) |
678 | 4ad40f36 | bellard | tlb_flush (env, 1);
|
679 | 4ad40f36 | bellard | |
680 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
681 | 6af0bf9c | bellard | size = (tlb->end - tlb->VPN) >> 12;
|
682 | 6af0bf9c | bellard | env->CP0_PageMask = (size - 1) << 13; |
683 | 98c1b82b | pbrook | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
684 | 98c1b82b | pbrook | | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
685 | 98c1b82b | pbrook | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
686 | 98c1b82b | pbrook | | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
687 | 6af0bf9c | bellard | } |
688 | 6af0bf9c | bellard | #endif
|
689 | 6af0bf9c | bellard | |
690 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
691 | 048f6b4d | bellard | |
692 | 6af0bf9c | bellard | void op_dump_ldst (const unsigned char *func) |
693 | 6af0bf9c | bellard | { |
694 | 6af0bf9c | bellard | if (loglevel)
|
695 | 6af0bf9c | bellard | fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
|
696 | 6af0bf9c | bellard | } |
697 | 6af0bf9c | bellard | |
698 | 6af0bf9c | bellard | void dump_sc (void) |
699 | 6af0bf9c | bellard | { |
700 | 6af0bf9c | bellard | if (loglevel) {
|
701 | 6af0bf9c | bellard | fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
|
702 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
703 | 6af0bf9c | bellard | } |
704 | 6af0bf9c | bellard | } |
705 | 6af0bf9c | bellard | |
706 | 6af0bf9c | bellard | void debug_eret (void) |
707 | 6af0bf9c | bellard | { |
708 | 6af0bf9c | bellard | if (loglevel) {
|
709 | 6af0bf9c | bellard | fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
|
710 | 6af0bf9c | bellard | env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
711 | 6af0bf9c | bellard | env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
712 | 6af0bf9c | bellard | } |
713 | 6af0bf9c | bellard | } |
714 | 6af0bf9c | bellard | |
715 | 6af0bf9c | bellard | void do_pmon (int function) |
716 | 6af0bf9c | bellard | { |
717 | 6af0bf9c | bellard | function /= 2;
|
718 | 6af0bf9c | bellard | switch (function) {
|
719 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
720 | 6af0bf9c | bellard | if (env->gpr[4] == 0) |
721 | 6af0bf9c | bellard | env->gpr[2] = -1; |
722 | 6af0bf9c | bellard | /* Fall through */
|
723 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
724 | 6af0bf9c | bellard | env->gpr[2] = -1; |
725 | 6af0bf9c | bellard | break;
|
726 | 6af0bf9c | bellard | case 3: |
727 | 6af0bf9c | bellard | case 12: |
728 | 6af0bf9c | bellard | printf("%c", env->gpr[4] & 0xFF); |
729 | 6af0bf9c | bellard | break;
|
730 | 6af0bf9c | bellard | case 17: |
731 | 6af0bf9c | bellard | break;
|
732 | 6af0bf9c | bellard | case 158: |
733 | 6af0bf9c | bellard | { |
734 | 6af0bf9c | bellard | unsigned char *fmt = (void *)env->gpr[4]; |
735 | 6af0bf9c | bellard | printf("%s", fmt);
|
736 | 6af0bf9c | bellard | } |
737 | 6af0bf9c | bellard | break;
|
738 | 6af0bf9c | bellard | } |
739 | 6af0bf9c | bellard | } |
740 | e37e863f | bellard | |
741 | e37e863f | bellard | #if !defined(CONFIG_USER_ONLY)
|
742 | e37e863f | bellard | |
743 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
744 | 4ad40f36 | bellard | |
745 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
746 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
747 | e37e863f | bellard | |
748 | e37e863f | bellard | #define SHIFT 0 |
749 | e37e863f | bellard | #include "softmmu_template.h" |
750 | e37e863f | bellard | |
751 | e37e863f | bellard | #define SHIFT 1 |
752 | e37e863f | bellard | #include "softmmu_template.h" |
753 | e37e863f | bellard | |
754 | e37e863f | bellard | #define SHIFT 2 |
755 | e37e863f | bellard | #include "softmmu_template.h" |
756 | e37e863f | bellard | |
757 | e37e863f | bellard | #define SHIFT 3 |
758 | e37e863f | bellard | #include "softmmu_template.h" |
759 | e37e863f | bellard | |
760 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
761 | 4ad40f36 | bellard | { |
762 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
763 | 4ad40f36 | bellard | do_restore_state (retaddr); |
764 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
765 | 4ad40f36 | bellard | } |
766 | 4ad40f36 | bellard | |
767 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
768 | e37e863f | bellard | { |
769 | e37e863f | bellard | TranslationBlock *tb; |
770 | e37e863f | bellard | CPUState *saved_env; |
771 | e37e863f | bellard | unsigned long pc; |
772 | e37e863f | bellard | int ret;
|
773 | e37e863f | bellard | |
774 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
775 | e37e863f | bellard | generated code */
|
776 | e37e863f | bellard | saved_env = env; |
777 | e37e863f | bellard | env = cpu_single_env; |
778 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
779 | e37e863f | bellard | if (ret) {
|
780 | e37e863f | bellard | if (retaddr) {
|
781 | e37e863f | bellard | /* now we have a real cpu fault */
|
782 | e37e863f | bellard | pc = (unsigned long)retaddr; |
783 | e37e863f | bellard | tb = tb_find_pc(pc); |
784 | e37e863f | bellard | if (tb) {
|
785 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
786 | e37e863f | bellard | a virtual CPU fault */
|
787 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
788 | e37e863f | bellard | } |
789 | e37e863f | bellard | } |
790 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
791 | e37e863f | bellard | } |
792 | e37e863f | bellard | env = saved_env; |
793 | e37e863f | bellard | } |
794 | e37e863f | bellard | |
795 | e37e863f | bellard | #endif |