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Revision 4852e5d8

b/hw/omap.h
745	745	struct omap_dss_s;
746	746	void omap_dss_reset(struct omap_dss_s *s);
747	747	struct omap_dss_s omap_dss_init(struct omap_target_agent_s ta,
	748	MemoryRegion *sysmem,
748	749	target_phys_addr_t l3_base,
749	750	qemu_irq irq, qemu_irq drq,
750	751	omap_clk fck1, omap_clk fck2, omap_clk ck54m,

                         omap_findclk(s, "spi2_fclk"),
                         omap_findclk(s, "spi2_iclk"));
         s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
         s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
                         /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
                         qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
                                s->drq[OMAP24XX_DMA_DSS],

         qemu_irq irq;
         qemu_irq drq;
         DisplayState *state;
         MemoryRegion iomem_diss1, iomem_disc1, iomem_rfbi1, iomem_venc1, iomem_im3;
         int autoidle;
         int control;
-...
         omap_dispc_interrupt_update(s);
+    }
     static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
     static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
                                    unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_read32(opaque, addr);
+        }
         switch (addr) {
         case 0x00:	/* DSS_REVISIONNUMBER */
             return 0x20;
-...
+    }
     static void omap_diss_write(void *opaque, target_phys_addr_t addr,
                     uint32_t value)
                                 uint64_t value, unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_write32(opaque, addr, value);
+        }
         switch (addr) {
         case 0x00:	/* DSS_REVISIONNUMBER */
         case 0x14:	/* DSS_SYSSTATUS */
-...
+        }
+    }
     static CPUReadMemoryFunc * const omap_diss1_readfn[] = {
         omap_badwidth_read32,
         omap_badwidth_read32,
         omap_diss_read,
     static const MemoryRegionOps omap_diss_ops = {
         .read = omap_diss_read,
         .write = omap_diss_write,
         .endianness = DEVICE_NATIVE_ENDIAN,
     };
     static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
         omap_badwidth_write32,
         omap_badwidth_write32,
         omap_diss_write,
     };
     static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
     static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
                                    unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_read32(opaque, addr);
+        }
         switch (addr) {
         case 0x000:	/* DISPC_REVISION */
             return 0x20;
-...
+    }
     static void omap_disc_write(void *opaque, target_phys_addr_t addr,
                     uint32_t value)
                                 uint64_t value, unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_write32(opaque, addr, value);
+        }
         switch (addr) {
         case 0x010:	/* DISPC_SYSCONFIG */
             if (value & 2)						/* SOFTRESET */
-...
+        }
+    }
     static CPUReadMemoryFunc * const omap_disc1_readfn[] = {
         omap_badwidth_read32,
         omap_badwidth_read32,
         omap_disc_read,
     };
     static CPUWriteMemoryFunc * const omap_disc1_writefn[] = {
         omap_badwidth_write32,
         omap_badwidth_write32,
         omap_disc_write,
     static const MemoryRegionOps omap_disc_ops = {
         .read = omap_disc_read,
         .write = omap_disc_write,
         .endianness = DEVICE_NATIVE_ENDIAN,
     };
     static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
-...
         omap_dispc_interrupt_update(s);
+    }
     static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
     static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
                                    unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_read32(opaque, addr);
+        }
         switch (addr) {
         case 0x00:	/* RFBI_REVISION */
             return 0x10;
-...
+    }
     static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
                     uint32_t value)
                                 uint64_t value, unsigned size)
+    {
         struct omap_dss_s *s = (struct omap_dss_s *) opaque;
         if (size != 4) {
             return omap_badwidth_write32(opaque, addr, value);
+        }
         switch (addr) {
         case 0x10:	/* RFBI_SYSCONFIG */
             if (value & 2)						/* SOFTRESET */
-...
+        }
+    }
     static CPUReadMemoryFunc * const omap_rfbi1_readfn[] = {
         omap_badwidth_read32,
         omap_badwidth_read32,
         omap_rfbi_read,
     };
     static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
         omap_badwidth_write32,
         omap_badwidth_write32,
         omap_rfbi_write,
     static const MemoryRegionOps omap_rfbi_ops = {
         .read = omap_rfbi_read,
         .write = omap_rfbi_write,
         .endianness = DEVICE_NATIVE_ENDIAN,
     };
     static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
     static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
                                    unsigned size)
+    {
         if (size != 4) {
             return omap_badwidth_read32(opaque, addr);
+        }
         switch (addr) {
         case 0x00:	/* REV_ID */
         case 0x04:	/* STATUS */
-...
+    }
     static void omap_venc_write(void *opaque, target_phys_addr_t addr,
                     uint32_t value)
                                 uint64_t value, unsigned size)
+    {
         if (size != 4) {
             return omap_badwidth_write32(opaque, addr, size);
+        }
         switch (addr) {
         case 0x08:	/* F_CONTROL */
         case 0x10:	/* VIDOUT_CTRL */
-...
+        }
+    }
     static CPUReadMemoryFunc * const omap_venc1_readfn[] = {
         omap_badwidth_read32,
         omap_badwidth_read32,
         omap_venc_read,
     static const MemoryRegionOps omap_venc_ops = {
         .read = omap_venc_read,
         .write = omap_venc_write,
         .endianness = DEVICE_NATIVE_ENDIAN,
     };
     static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
         omap_badwidth_write32,
         omap_badwidth_write32,
         omap_venc_write,
     };
     static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
     static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
                                   unsigned size)
+    {
         if (size != 4) {
             return omap_badwidth_read32(opaque, addr);
+        }
         switch (addr) {
         case 0x0a8:	/* SBIMERRLOGA */
         case 0x0b0:	/* SBIMERRLOG */
-...
+    }
     static void omap_im3_write(void *opaque, target_phys_addr_t addr,
                     uint32_t value)
                                uint64_t value, unsigned size)
+    {
         if (size != 4) {
             return omap_badwidth_write32(opaque, addr, value);
+        }
         switch (addr) {
         case 0x0b0:	/* SBIMERRLOG */
         case 0x190:	/* SBIMSTATE */
-...
+        }
+    }
     static CPUReadMemoryFunc * const omap_im3_readfn[] = {
         omap_badwidth_read32,
         omap_badwidth_read32,
         omap_im3_read,
     };
     static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
         omap_badwidth_write32,
         omap_badwidth_write32,
         omap_im3_write,
     static const MemoryRegionOps omap_im3_ops = {
         .read = omap_im3_read,
         .write = omap_im3_write,
         .endianness = DEVICE_NATIVE_ENDIAN,
     };
     struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
                     MemoryRegion *sysmem,
                     target_phys_addr_t l3_base,
                     qemu_irq irq, qemu_irq drq,
                     omap_clk fck1, omap_clk fck2, omap_clk ck54m,
                     omap_clk ick1, omap_clk ick2)
+    {
         int iomemtype[5];
         struct omap_dss_s *s = (struct omap_dss_s *)
                 g_malloc0(sizeof(struct omap_dss_s));
-...
         s->drq = drq;
         omap_dss_reset(s);
         iomemtype[0] = cpu_register_io_memory(omap_diss1_readfn,
                         omap_diss1_writefn, s, DEVICE_NATIVE_ENDIAN);
         iomemtype[1] = cpu_register_io_memory(omap_disc1_readfn,
                         omap_disc1_writefn, s, DEVICE_NATIVE_ENDIAN);
         iomemtype[2] = cpu_register_io_memory(omap_rfbi1_readfn,
                         omap_rfbi1_writefn, s, DEVICE_NATIVE_ENDIAN);
         iomemtype[3] = cpu_register_io_memory(omap_venc1_readfn,
                         omap_venc1_writefn, s, DEVICE_NATIVE_ENDIAN);
         iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
                         omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN);
         omap_l4_attach(ta, 0, iomemtype[0]);
         omap_l4_attach(ta, 1, iomemtype[1]);
         omap_l4_attach(ta, 2, iomemtype[2]);
         omap_l4_attach(ta, 3, iomemtype[3]);
         cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
         memory_region_init_io(&s->iomem_diss1, &omap_diss_ops, s, "omap.diss1",
                               omap_l4_region_size(ta, 0));
         memory_region_init_io(&s->iomem_disc1, &omap_disc_ops, s, "omap.disc1",
                               omap_l4_region_size(ta, 1));
         memory_region_init_io(&s->iomem_rfbi1, &omap_rfbi_ops, s, "omap.rfbi1",
                               omap_l4_region_size(ta, 2));
         memory_region_init_io(&s->iomem_venc1, &omap_venc_ops, s, "omap.venc1",
                               omap_l4_region_size(ta, 3));
         memory_region_init_io(&s->iomem_im3, &omap_im3_ops, s,
                               "omap.im3", 0x1000);
         omap_l4_attach_region(ta, 0, &s->iomem_diss1);
         omap_l4_attach_region(ta, 1, &s->iomem_disc1);
         omap_l4_attach_region(ta, 2, &s->iomem_rfbi1);
         omap_l4_attach_region(ta, 3, &s->iomem_venc1);
         memory_region_add_subregion(sysmem, l3_base, &s->iomem_im3);
     #if 0
         s->state = graphic_console_init(omap_update_display,

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Revision 4852e5d8