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1 | 663e8e51 | ths | /*
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2 | 663e8e51 | ths | * QEMU i8255x (PRO100) emulation
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3 | 663e8e51 | ths | *
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4 | 663e8e51 | ths | * Copyright (c) 2006-2007 Stefan Weil
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5 | 663e8e51 | ths | *
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6 | 663e8e51 | ths | * Portions of the code are copies from grub / etherboot eepro100.c
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7 | 663e8e51 | ths | * and linux e100.c.
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8 | 663e8e51 | ths | *
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9 | 663e8e51 | ths | * This program is free software; you can redistribute it and/or modify
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10 | 663e8e51 | ths | * it under the terms of the GNU General Public License as published by
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11 | 663e8e51 | ths | * the Free Software Foundation; either version 2 of the License, or
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12 | 663e8e51 | ths | * (at your option) any later version.
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13 | 663e8e51 | ths | *
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14 | 663e8e51 | ths | * This program is distributed in the hope that it will be useful,
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15 | 663e8e51 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 663e8e51 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 663e8e51 | ths | * GNU General Public License for more details.
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18 | 663e8e51 | ths | *
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19 | 663e8e51 | ths | * You should have received a copy of the GNU General Public License
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20 | 663e8e51 | ths | * along with this program; if not, write to the Free Software
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21 | 663e8e51 | ths | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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22 | 663e8e51 | ths | *
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23 | 663e8e51 | ths | * Tested features (i82559):
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24 | 663e8e51 | ths | * PXE boot (i386) no valid link
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25 | 663e8e51 | ths | * Linux networking (i386) ok
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26 | 663e8e51 | ths | *
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27 | 663e8e51 | ths | * Untested:
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28 | 663e8e51 | ths | * non-i386 platforms
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29 | 663e8e51 | ths | * Windows networking
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30 | 663e8e51 | ths | *
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31 | 663e8e51 | ths | * References:
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32 | 663e8e51 | ths | *
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33 | 663e8e51 | ths | * Intel 8255x 10/100 Mbps Ethernet Controller Family
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34 | 663e8e51 | ths | * Open Source Software Developer Manual
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35 | 663e8e51 | ths | */
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36 | 663e8e51 | ths | |
37 | 663e8e51 | ths | #if defined(TARGET_I386)
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38 | 663e8e51 | ths | # warning "PXE boot still not working!" |
39 | 663e8e51 | ths | #endif
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40 | 663e8e51 | ths | |
41 | 663e8e51 | ths | #include <assert.h> |
42 | 663e8e51 | ths | #include <stddef.h> /* offsetof */ |
43 | 87ecb68b | pbrook | #include "hw.h" |
44 | 87ecb68b | pbrook | #include "pci.h" |
45 | 87ecb68b | pbrook | #include "net.h" |
46 | 663e8e51 | ths | #include "eeprom93xx.h" |
47 | 663e8e51 | ths | |
48 | 663e8e51 | ths | /* Common declarations for all PCI devices. */
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49 | 663e8e51 | ths | |
50 | 663e8e51 | ths | #define PCI_CONFIG_8(offset, value) \
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51 | 663e8e51 | ths | (pci_conf[offset] = (value)) |
52 | 663e8e51 | ths | #define PCI_CONFIG_16(offset, value) \
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53 | 663e8e51 | ths | (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) |
54 | 663e8e51 | ths | #define PCI_CONFIG_32(offset, value) \
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55 | 663e8e51 | ths | (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) |
56 | 663e8e51 | ths | |
57 | 663e8e51 | ths | #define KiB 1024 |
58 | 663e8e51 | ths | |
59 | 663e8e51 | ths | /* debug EEPRO100 card */
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60 | 663e8e51 | ths | //~ #define DEBUG_EEPRO100
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61 | 663e8e51 | ths | |
62 | 663e8e51 | ths | #ifdef DEBUG_EEPRO100
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63 | 663e8e51 | ths | #define logout(fmt, args...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ##args) |
64 | 663e8e51 | ths | #else
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65 | 663e8e51 | ths | #define logout(fmt, args...) ((void)0) |
66 | 663e8e51 | ths | #endif
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67 | 663e8e51 | ths | |
68 | 663e8e51 | ths | /* Set flags to 0 to disable debug output. */
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69 | 663e8e51 | ths | #define MDI 0 |
70 | 663e8e51 | ths | |
71 | 663e8e51 | ths | #define TRACE(flag, command) ((flag) ? (command) : (void)0) |
72 | 663e8e51 | ths | |
73 | 663e8e51 | ths | #define missing(text) assert(!"feature is missing in this emulation: " text) |
74 | 663e8e51 | ths | |
75 | 663e8e51 | ths | #define MAX_ETH_FRAME_SIZE 1514 |
76 | 663e8e51 | ths | |
77 | 663e8e51 | ths | /* This driver supports several different devices which are declared here. */
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78 | 663e8e51 | ths | #define i82551 0x82551 |
79 | 663e8e51 | ths | #define i82557B 0x82557b |
80 | 663e8e51 | ths | #define i82557C 0x82557c |
81 | 663e8e51 | ths | #define i82558B 0x82558b |
82 | 663e8e51 | ths | #define i82559C 0x82559c |
83 | 663e8e51 | ths | #define i82559ER 0x82559e |
84 | 663e8e51 | ths | #define i82562 0x82562 |
85 | 663e8e51 | ths | |
86 | 663e8e51 | ths | #define EEPROM_SIZE 64 |
87 | 663e8e51 | ths | |
88 | 663e8e51 | ths | #define PCI_MEM_SIZE (4 * KiB) |
89 | 663e8e51 | ths | #define PCI_IO_SIZE 64 |
90 | 663e8e51 | ths | #define PCI_FLASH_SIZE (128 * KiB) |
91 | 663e8e51 | ths | |
92 | 663e8e51 | ths | #define BIT(n) (1 << (n)) |
93 | 663e8e51 | ths | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
94 | 663e8e51 | ths | |
95 | 663e8e51 | ths | /* The SCB accepts the following controls for the Tx and Rx units: */
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96 | 663e8e51 | ths | #define CU_NOP 0x0000 /* No operation. */ |
97 | 663e8e51 | ths | #define CU_START 0x0010 /* CU start. */ |
98 | 663e8e51 | ths | #define CU_RESUME 0x0020 /* CU resume. */ |
99 | 663e8e51 | ths | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
100 | 663e8e51 | ths | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
101 | 663e8e51 | ths | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
102 | 663e8e51 | ths | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
103 | 663e8e51 | ths | #define CU_SRESUME 0x00a0 /* CU static resume. */ |
104 | 663e8e51 | ths | |
105 | 663e8e51 | ths | #define RU_NOP 0x0000 |
106 | 663e8e51 | ths | #define RX_START 0x0001 |
107 | 663e8e51 | ths | #define RX_RESUME 0x0002 |
108 | 663e8e51 | ths | #define RX_ABORT 0x0004 |
109 | 663e8e51 | ths | #define RX_ADDR_LOAD 0x0006 |
110 | 663e8e51 | ths | #define RX_RESUMENR 0x0007 |
111 | 663e8e51 | ths | #define INT_MASK 0x0100 |
112 | 663e8e51 | ths | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
113 | 663e8e51 | ths | |
114 | 663e8e51 | ths | typedef unsigned char bool; |
115 | 663e8e51 | ths | |
116 | 663e8e51 | ths | /* Offsets to the various registers.
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117 | 663e8e51 | ths | All accesses need not be longword aligned. */
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118 | 663e8e51 | ths | enum speedo_offsets {
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119 | 663e8e51 | ths | SCBStatus = 0,
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120 | 663e8e51 | ths | SCBAck = 1,
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121 | 663e8e51 | ths | SCBCmd = 2, /* Rx/Command Unit command and status. */ |
122 | 663e8e51 | ths | SCBIntmask = 3,
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123 | 663e8e51 | ths | SCBPointer = 4, /* General purpose pointer. */ |
124 | 663e8e51 | ths | SCBPort = 8, /* Misc. commands and operands. */ |
125 | 663e8e51 | ths | SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ |
126 | 663e8e51 | ths | SCBCtrlMDI = 16, /* MDI interface control. */ |
127 | 663e8e51 | ths | SCBEarlyRx = 20, /* Early receive byte count. */ |
128 | 3257d2b6 | ths | SCBFlow = 24,
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129 | 663e8e51 | ths | }; |
130 | 663e8e51 | ths | |
131 | 663e8e51 | ths | /* A speedo3 transmit buffer descriptor with two buffers... */
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132 | 663e8e51 | ths | typedef struct { |
133 | 663e8e51 | ths | uint16_t status; |
134 | 663e8e51 | ths | uint16_t command; |
135 | 663e8e51 | ths | uint32_t link; /* void * */
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136 | 663e8e51 | ths | uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
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137 | 663e8e51 | ths | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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138 | 663e8e51 | ths | uint8_t tx_threshold; /* transmit threshold */
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139 | 663e8e51 | ths | uint8_t tbd_count; /* TBD number */
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140 | 663e8e51 | ths | //~ /* This constitutes two "TBD" entries: hdr and data */
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141 | 663e8e51 | ths | //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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142 | 663e8e51 | ths | //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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143 | 663e8e51 | ths | //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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144 | 663e8e51 | ths | //~ int32_t tx_buf_size1; /* Length of Tx data. */
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145 | 663e8e51 | ths | } eepro100_tx_t; |
146 | 663e8e51 | ths | |
147 | 663e8e51 | ths | /* Receive frame descriptor. */
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148 | 663e8e51 | ths | typedef struct { |
149 | 663e8e51 | ths | int16_t status; |
150 | 663e8e51 | ths | uint16_t command; |
151 | 663e8e51 | ths | uint32_t link; /* struct RxFD * */
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152 | 663e8e51 | ths | uint32_t rx_buf_addr; /* void * */
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153 | 663e8e51 | ths | uint16_t count; |
154 | 663e8e51 | ths | uint16_t size; |
155 | 663e8e51 | ths | char packet[MAX_ETH_FRAME_SIZE + 4]; |
156 | 663e8e51 | ths | } eepro100_rx_t; |
157 | 663e8e51 | ths | |
158 | 663e8e51 | ths | typedef struct { |
159 | 663e8e51 | ths | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
160 | 663e8e51 | ths | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
161 | 663e8e51 | ths | tx_multiple_collisions, tx_total_collisions; |
162 | 663e8e51 | ths | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
163 | 663e8e51 | ths | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
164 | 663e8e51 | ths | rx_short_frame_errors; |
165 | 663e8e51 | ths | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
166 | 663e8e51 | ths | uint16_t xmt_tco_frames, rcv_tco_frames; |
167 | 663e8e51 | ths | uint32_t complete; |
168 | 663e8e51 | ths | } eepro100_stats_t; |
169 | 663e8e51 | ths | |
170 | 663e8e51 | ths | typedef enum { |
171 | 663e8e51 | ths | cu_idle = 0,
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172 | 663e8e51 | ths | cu_suspended = 1,
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173 | 663e8e51 | ths | cu_active = 2,
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174 | 663e8e51 | ths | cu_lpq_active = 2,
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175 | 663e8e51 | ths | cu_hqp_active = 3
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176 | 663e8e51 | ths | } cu_state_t; |
177 | 663e8e51 | ths | |
178 | 663e8e51 | ths | typedef enum { |
179 | 663e8e51 | ths | ru_idle = 0,
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180 | 663e8e51 | ths | ru_suspended = 1,
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181 | 663e8e51 | ths | ru_no_resources = 2,
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182 | 663e8e51 | ths | ru_ready = 4
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183 | 663e8e51 | ths | } ru_state_t; |
184 | 663e8e51 | ths | |
185 | 663e8e51 | ths | typedef struct { |
186 | 663e8e51 | ths | #if 1 |
187 | 663e8e51 | ths | uint8_t cmd; |
188 | 663e8e51 | ths | uint32_t start; |
189 | 663e8e51 | ths | uint32_t stop; |
190 | 663e8e51 | ths | uint8_t boundary; |
191 | 663e8e51 | ths | uint8_t tsr; |
192 | 663e8e51 | ths | uint8_t tpsr; |
193 | 663e8e51 | ths | uint16_t tcnt; |
194 | 663e8e51 | ths | uint16_t rcnt; |
195 | 663e8e51 | ths | uint32_t rsar; |
196 | 663e8e51 | ths | uint8_t rsr; |
197 | 663e8e51 | ths | uint8_t rxcr; |
198 | 663e8e51 | ths | uint8_t isr; |
199 | 663e8e51 | ths | uint8_t dcfg; |
200 | 663e8e51 | ths | uint8_t imr; |
201 | 663e8e51 | ths | uint8_t phys[6]; /* mac address */ |
202 | 663e8e51 | ths | uint8_t curpag; |
203 | 663e8e51 | ths | uint8_t mult[8]; /* multicast mask array */ |
204 | 663e8e51 | ths | int mmio_index;
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205 | 663e8e51 | ths | PCIDevice *pci_dev; |
206 | 663e8e51 | ths | VLANClientState *vc; |
207 | 663e8e51 | ths | #endif
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208 | 663e8e51 | ths | uint8_t scb_stat; /* SCB stat/ack byte */
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209 | 663e8e51 | ths | uint8_t int_stat; /* PCI interrupt status */
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210 | 663e8e51 | ths | uint32_t region[3]; /* PCI region addresses */ |
211 | 663e8e51 | ths | uint8_t macaddr[6];
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212 | 663e8e51 | ths | uint32_t statcounter[19];
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213 | 663e8e51 | ths | uint16_t mdimem[32];
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214 | 663e8e51 | ths | eeprom_t *eeprom; |
215 | 663e8e51 | ths | uint32_t device; /* device variant */
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216 | 663e8e51 | ths | uint32_t pointer; |
217 | 663e8e51 | ths | /* (cu_base + cu_offset) address the next command block in the command block list. */
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218 | 663e8e51 | ths | uint32_t cu_base; /* CU base address */
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219 | 663e8e51 | ths | uint32_t cu_offset; /* CU address offset */
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220 | 663e8e51 | ths | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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221 | 663e8e51 | ths | uint32_t ru_base; /* RU base address */
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222 | 663e8e51 | ths | uint32_t ru_offset; /* RU address offset */
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223 | 663e8e51 | ths | uint32_t statsaddr; /* pointer to eepro100_stats_t */
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224 | 663e8e51 | ths | eepro100_stats_t statistics; /* statistical counters */
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225 | 663e8e51 | ths | #if 0
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226 | 663e8e51 | ths | uint16_t status;
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227 | 663e8e51 | ths | #endif
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228 | 663e8e51 | ths | |
229 | 663e8e51 | ths | /* Configuration bytes. */
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230 | 663e8e51 | ths | uint8_t configuration[22];
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231 | 663e8e51 | ths | |
232 | 663e8e51 | ths | /* Data in mem is always in the byte order of the controller (le). */
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233 | 663e8e51 | ths | uint8_t mem[PCI_MEM_SIZE]; |
234 | 663e8e51 | ths | } EEPRO100State; |
235 | 663e8e51 | ths | |
236 | 663e8e51 | ths | /* Default values for MDI (PHY) registers */
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237 | 663e8e51 | ths | static const uint16_t eepro100_mdi_default[] = { |
238 | 663e8e51 | ths | /* MDI Registers 0 - 6, 7 */
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239 | 663e8e51 | ths | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
240 | 663e8e51 | ths | /* MDI Registers 8 - 15 */
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241 | 663e8e51 | ths | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
242 | 663e8e51 | ths | /* MDI Registers 16 - 31 */
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243 | 663e8e51 | ths | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
244 | 663e8e51 | ths | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
245 | 663e8e51 | ths | }; |
246 | 663e8e51 | ths | |
247 | 663e8e51 | ths | /* Readonly mask for MDI (PHY) registers */
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248 | 663e8e51 | ths | static const uint16_t eepro100_mdi_mask[] = { |
249 | 663e8e51 | ths | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
250 | 663e8e51 | ths | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
251 | 663e8e51 | ths | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
252 | 663e8e51 | ths | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
253 | 663e8e51 | ths | }; |
254 | 663e8e51 | ths | |
255 | 663e8e51 | ths | #define POLYNOMIAL 0x04c11db6 |
256 | 663e8e51 | ths | |
257 | 663e8e51 | ths | /* From FreeBSD */
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258 | 663e8e51 | ths | /* XXX: optimize */
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259 | 663e8e51 | ths | static int compute_mcast_idx(const uint8_t * ep) |
260 | 663e8e51 | ths | { |
261 | 663e8e51 | ths | uint32_t crc; |
262 | 663e8e51 | ths | int carry, i, j;
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263 | 663e8e51 | ths | uint8_t b; |
264 | 663e8e51 | ths | |
265 | 663e8e51 | ths | crc = 0xffffffff;
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266 | 663e8e51 | ths | for (i = 0; i < 6; i++) { |
267 | 663e8e51 | ths | b = *ep++; |
268 | 663e8e51 | ths | for (j = 0; j < 8; j++) { |
269 | 663e8e51 | ths | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
270 | 663e8e51 | ths | crc <<= 1;
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271 | 663e8e51 | ths | b >>= 1;
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272 | 663e8e51 | ths | if (carry)
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273 | 663e8e51 | ths | crc = ((crc ^ POLYNOMIAL) | carry); |
274 | 663e8e51 | ths | } |
275 | 663e8e51 | ths | } |
276 | 663e8e51 | ths | return (crc >> 26); |
277 | 663e8e51 | ths | } |
278 | 663e8e51 | ths | |
279 | 663e8e51 | ths | #if defined(DEBUG_EEPRO100)
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280 | 663e8e51 | ths | static const char *nic_dump(const uint8_t * buf, unsigned size) |
281 | 663e8e51 | ths | { |
282 | 663e8e51 | ths | static char dump[3 * 16 + 1]; |
283 | 663e8e51 | ths | char *p = &dump[0]; |
284 | 663e8e51 | ths | if (size > 16) |
285 | 663e8e51 | ths | size = 16;
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286 | 663e8e51 | ths | while (size-- > 0) { |
287 | 663e8e51 | ths | p += sprintf(p, " %02x", *buf++);
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288 | 663e8e51 | ths | } |
289 | 663e8e51 | ths | return dump;
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290 | 663e8e51 | ths | } |
291 | 663e8e51 | ths | #endif /* DEBUG_EEPRO100 */ |
292 | 663e8e51 | ths | |
293 | 663e8e51 | ths | enum scb_stat_ack {
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294 | 663e8e51 | ths | stat_ack_not_ours = 0x00,
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295 | 663e8e51 | ths | stat_ack_sw_gen = 0x04,
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296 | 663e8e51 | ths | stat_ack_rnr = 0x10,
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297 | 663e8e51 | ths | stat_ack_cu_idle = 0x20,
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298 | 663e8e51 | ths | stat_ack_frame_rx = 0x40,
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299 | 663e8e51 | ths | stat_ack_cu_cmd_done = 0x80,
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300 | 663e8e51 | ths | stat_ack_not_present = 0xFF,
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301 | 663e8e51 | ths | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
302 | 663e8e51 | ths | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
303 | 663e8e51 | ths | }; |
304 | 663e8e51 | ths | |
305 | 663e8e51 | ths | static void disable_interrupt(EEPRO100State * s) |
306 | 663e8e51 | ths | { |
307 | 663e8e51 | ths | if (s->int_stat) {
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308 | 663e8e51 | ths | logout("interrupt disabled\n");
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309 | d537cf6c | pbrook | qemu_irq_lower(s->pci_dev->irq[0]);
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310 | 663e8e51 | ths | s->int_stat = 0;
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311 | 663e8e51 | ths | } |
312 | 663e8e51 | ths | } |
313 | 663e8e51 | ths | |
314 | 663e8e51 | ths | static void enable_interrupt(EEPRO100State * s) |
315 | 663e8e51 | ths | { |
316 | 663e8e51 | ths | if (!s->int_stat) {
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317 | 663e8e51 | ths | logout("interrupt enabled\n");
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318 | d537cf6c | pbrook | qemu_irq_raise(s->pci_dev->irq[0]);
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319 | 663e8e51 | ths | s->int_stat = 1;
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320 | 663e8e51 | ths | } |
321 | 663e8e51 | ths | } |
322 | 663e8e51 | ths | |
323 | 663e8e51 | ths | static void eepro100_acknowledge(EEPRO100State * s) |
324 | 663e8e51 | ths | { |
325 | 663e8e51 | ths | s->scb_stat &= ~s->mem[SCBAck]; |
326 | 663e8e51 | ths | s->mem[SCBAck] = s->scb_stat; |
327 | 663e8e51 | ths | if (s->scb_stat == 0) { |
328 | 663e8e51 | ths | disable_interrupt(s); |
329 | 663e8e51 | ths | } |
330 | 663e8e51 | ths | } |
331 | 663e8e51 | ths | |
332 | 663e8e51 | ths | static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) |
333 | 663e8e51 | ths | { |
334 | 663e8e51 | ths | uint8_t mask = ~s->mem[SCBIntmask]; |
335 | 663e8e51 | ths | s->mem[SCBAck] |= stat; |
336 | 663e8e51 | ths | stat = s->scb_stat = s->mem[SCBAck]; |
337 | 663e8e51 | ths | stat &= (mask | 0x0f);
|
338 | 663e8e51 | ths | //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
|
339 | 663e8e51 | ths | if (stat && (mask & 0x01)) { |
340 | 663e8e51 | ths | /* SCB mask and SCB Bit M do not disable interrupt. */
|
341 | 663e8e51 | ths | enable_interrupt(s); |
342 | 663e8e51 | ths | } else if (s->int_stat) { |
343 | 663e8e51 | ths | disable_interrupt(s); |
344 | 663e8e51 | ths | } |
345 | 663e8e51 | ths | } |
346 | 663e8e51 | ths | |
347 | 663e8e51 | ths | static void eepro100_cx_interrupt(EEPRO100State * s) |
348 | 663e8e51 | ths | { |
349 | 663e8e51 | ths | /* CU completed action command. */
|
350 | 663e8e51 | ths | /* Transmit not ok (82557 only, not in emulation). */
|
351 | 663e8e51 | ths | eepro100_interrupt(s, 0x80);
|
352 | 663e8e51 | ths | } |
353 | 663e8e51 | ths | |
354 | 663e8e51 | ths | static void eepro100_cna_interrupt(EEPRO100State * s) |
355 | 663e8e51 | ths | { |
356 | 663e8e51 | ths | /* CU left the active state. */
|
357 | 663e8e51 | ths | eepro100_interrupt(s, 0x20);
|
358 | 663e8e51 | ths | } |
359 | 663e8e51 | ths | |
360 | 663e8e51 | ths | static void eepro100_fr_interrupt(EEPRO100State * s) |
361 | 663e8e51 | ths | { |
362 | 663e8e51 | ths | /* RU received a complete frame. */
|
363 | 663e8e51 | ths | eepro100_interrupt(s, 0x40);
|
364 | 663e8e51 | ths | } |
365 | 663e8e51 | ths | |
366 | 663e8e51 | ths | #if 0
|
367 | 663e8e51 | ths | static void eepro100_rnr_interrupt(EEPRO100State * s)
|
368 | 663e8e51 | ths | {
|
369 | 663e8e51 | ths | /* RU is not ready. */
|
370 | 663e8e51 | ths | eepro100_interrupt(s, 0x10);
|
371 | 663e8e51 | ths | }
|
372 | 663e8e51 | ths | #endif
|
373 | 663e8e51 | ths | |
374 | 663e8e51 | ths | static void eepro100_mdi_interrupt(EEPRO100State * s) |
375 | 663e8e51 | ths | { |
376 | 663e8e51 | ths | /* MDI completed read or write cycle. */
|
377 | 663e8e51 | ths | eepro100_interrupt(s, 0x08);
|
378 | 663e8e51 | ths | } |
379 | 663e8e51 | ths | |
380 | 663e8e51 | ths | static void eepro100_swi_interrupt(EEPRO100State * s) |
381 | 663e8e51 | ths | { |
382 | 663e8e51 | ths | /* Software has requested an interrupt. */
|
383 | 663e8e51 | ths | eepro100_interrupt(s, 0x04);
|
384 | 663e8e51 | ths | } |
385 | 663e8e51 | ths | |
386 | 663e8e51 | ths | #if 0
|
387 | 663e8e51 | ths | static void eepro100_fcp_interrupt(EEPRO100State * s)
|
388 | 663e8e51 | ths | {
|
389 | 663e8e51 | ths | /* Flow control pause interrupt (82558 and later). */
|
390 | 663e8e51 | ths | eepro100_interrupt(s, 0x01);
|
391 | 663e8e51 | ths | }
|
392 | 663e8e51 | ths | #endif
|
393 | 663e8e51 | ths | |
394 | 663e8e51 | ths | static void pci_reset(EEPRO100State * s) |
395 | 663e8e51 | ths | { |
396 | 663e8e51 | ths | uint32_t device = s->device; |
397 | 663e8e51 | ths | uint8_t *pci_conf = s->pci_dev->config; |
398 | 663e8e51 | ths | |
399 | 663e8e51 | ths | logout("%p\n", s);
|
400 | 663e8e51 | ths | |
401 | 663e8e51 | ths | /* PCI Vendor ID */
|
402 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
403 | 663e8e51 | ths | /* PCI Device ID */
|
404 | a770dc7e | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
405 | 663e8e51 | ths | /* PCI Command */
|
406 | 663e8e51 | ths | PCI_CONFIG_16(PCI_COMMAND, 0x0000);
|
407 | 663e8e51 | ths | /* PCI Status */
|
408 | 663e8e51 | ths | PCI_CONFIG_16(PCI_STATUS, 0x2800);
|
409 | 663e8e51 | ths | /* PCI Revision ID */
|
410 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
411 | 663e8e51 | ths | /* PCI Class Code */
|
412 | 663e8e51 | ths | PCI_CONFIG_8(0x09, 0x00); |
413 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
414 | 663e8e51 | ths | /* PCI Cache Line Size */
|
415 | 663e8e51 | ths | /* check cache line size!!! */
|
416 | 663e8e51 | ths | //~ PCI_CONFIG_8(0x0c, 0x00);
|
417 | 663e8e51 | ths | /* PCI Latency Timer */
|
418 | 663e8e51 | ths | PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks |
419 | 663e8e51 | ths | /* PCI Header Type */
|
420 | 663e8e51 | ths | /* BIST (built-in self test) */
|
421 | 663e8e51 | ths | #if defined(TARGET_I386)
|
422 | 663e8e51 | ths | // !!! workaround for buggy bios
|
423 | 663e8e51 | ths | //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
|
424 | 663e8e51 | ths | #endif
|
425 | 663e8e51 | ths | #if 0
|
426 | 663e8e51 | ths | /* PCI Base Address Registers */
|
427 | 663e8e51 | ths | /* CSR Memory Mapped Base Address */
|
428 | 663e8e51 | ths | PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
|
429 | 663e8e51 | ths | PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
|
430 | 663e8e51 | ths | /* CSR I/O Mapped Base Address */
|
431 | 663e8e51 | ths | PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
|
432 | 663e8e51 | ths | #if 0
|
433 | 663e8e51 | ths | /* Flash Memory Mapped Base Address */
|
434 | 663e8e51 | ths | PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
|
435 | 663e8e51 | ths | #endif
|
436 | 663e8e51 | ths | #endif
|
437 | 663e8e51 | ths | /* Expansion ROM Base Address (depends on boot disable!!!) */
|
438 | 663e8e51 | ths | PCI_CONFIG_32(0x30, 0x00000000); |
439 | 663e8e51 | ths | /* Capability Pointer */
|
440 | 663e8e51 | ths | PCI_CONFIG_8(0x34, 0xdc); |
441 | 663e8e51 | ths | /* Interrupt Pin */
|
442 | 663e8e51 | ths | PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 |
443 | 663e8e51 | ths | /* Minimum Grant */
|
444 | 663e8e51 | ths | PCI_CONFIG_8(0x3e, 0x08); |
445 | 663e8e51 | ths | /* Maximum Latency */
|
446 | 663e8e51 | ths | PCI_CONFIG_8(0x3f, 0x18); |
447 | 663e8e51 | ths | /* Power Management Capabilities / Next Item Pointer / Capability ID */
|
448 | 663e8e51 | ths | PCI_CONFIG_32(0xdc, 0x7e210001); |
449 | 663e8e51 | ths | |
450 | 663e8e51 | ths | switch (device) {
|
451 | 663e8e51 | ths | case i82551:
|
452 | 663e8e51 | ths | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
453 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
|
454 | 663e8e51 | ths | break;
|
455 | 663e8e51 | ths | case i82557B:
|
456 | 663e8e51 | ths | PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
457 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
|
458 | 663e8e51 | ths | break;
|
459 | 663e8e51 | ths | case i82557C:
|
460 | 663e8e51 | ths | PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
461 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
|
462 | 663e8e51 | ths | break;
|
463 | 663e8e51 | ths | case i82558B:
|
464 | 663e8e51 | ths | PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
465 | 663e8e51 | ths | PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
466 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
467 | 663e8e51 | ths | break;
|
468 | 663e8e51 | ths | case i82559C:
|
469 | 663e8e51 | ths | PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
470 | 663e8e51 | ths | PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
471 | 663e8e51 | ths | //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
472 | 663e8e51 | ths | break;
|
473 | 663e8e51 | ths | case i82559ER:
|
474 | 663e8e51 | ths | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
475 | 663e8e51 | ths | PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
476 | 663e8e51 | ths | PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
477 | 663e8e51 | ths | break;
|
478 | 663e8e51 | ths | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
|
479 | 663e8e51 | ths | //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
|
480 | 663e8e51 | ths | default:
|
481 | 663e8e51 | ths | logout("Device %X is undefined!\n", device);
|
482 | 663e8e51 | ths | } |
483 | 663e8e51 | ths | |
484 | 663e8e51 | ths | if (device == i82557C || device == i82558B || device == i82559C) {
|
485 | 663e8e51 | ths | logout("Get device id and revision from EEPROM!!!\n");
|
486 | 663e8e51 | ths | } |
487 | 663e8e51 | ths | } |
488 | 663e8e51 | ths | |
489 | 663e8e51 | ths | static void nic_selective_reset(EEPRO100State * s) |
490 | 663e8e51 | ths | { |
491 | 663e8e51 | ths | size_t i; |
492 | 663e8e51 | ths | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
493 | 663e8e51 | ths | //~ eeprom93xx_reset(s->eeprom);
|
494 | 663e8e51 | ths | memcpy(eeprom_contents, s->macaddr, 6);
|
495 | 663e8e51 | ths | eeprom_contents[0xa] = 0x4000; |
496 | 663e8e51 | ths | uint16_t sum = 0;
|
497 | 663e8e51 | ths | for (i = 0; i < EEPROM_SIZE - 1; i++) { |
498 | 663e8e51 | ths | sum += eeprom_contents[i]; |
499 | 663e8e51 | ths | } |
500 | 663e8e51 | ths | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
501 | 663e8e51 | ths | |
502 | 663e8e51 | ths | memset(s->mem, 0, sizeof(s->mem)); |
503 | 663e8e51 | ths | uint32_t val = BIT(21);
|
504 | 663e8e51 | ths | memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
|
505 | 663e8e51 | ths | |
506 | 663e8e51 | ths | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
507 | 663e8e51 | ths | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
508 | 663e8e51 | ths | } |
509 | 663e8e51 | ths | |
510 | 663e8e51 | ths | static void nic_reset(void *opaque) |
511 | 663e8e51 | ths | { |
512 | 663e8e51 | ths | EEPRO100State *s = (EEPRO100State *) opaque; |
513 | 663e8e51 | ths | logout("%p\n", s);
|
514 | 663e8e51 | ths | static int first; |
515 | 663e8e51 | ths | if (!first) {
|
516 | 663e8e51 | ths | first = 1;
|
517 | 663e8e51 | ths | } |
518 | 663e8e51 | ths | nic_selective_reset(s); |
519 | 663e8e51 | ths | } |
520 | 663e8e51 | ths | |
521 | 663e8e51 | ths | #if defined(DEBUG_EEPRO100)
|
522 | 663e8e51 | ths | static const char *reg[PCI_IO_SIZE / 4] = { |
523 | 663e8e51 | ths | "Command/Status",
|
524 | 663e8e51 | ths | "General Pointer",
|
525 | 663e8e51 | ths | "Port",
|
526 | 663e8e51 | ths | "EEPROM/Flash Control",
|
527 | 663e8e51 | ths | "MDI Control",
|
528 | 663e8e51 | ths | "Receive DMA Byte Count",
|
529 | 663e8e51 | ths | "Flow control register",
|
530 | 663e8e51 | ths | "General Status/Control"
|
531 | 663e8e51 | ths | }; |
532 | 663e8e51 | ths | |
533 | 663e8e51 | ths | static char *regname(uint32_t addr) |
534 | 663e8e51 | ths | { |
535 | 663e8e51 | ths | static char buf[16]; |
536 | 663e8e51 | ths | if (addr < PCI_IO_SIZE) {
|
537 | 663e8e51 | ths | const char *r = reg[addr / 4]; |
538 | 663e8e51 | ths | if (r != 0) { |
539 | 663e8e51 | ths | sprintf(buf, "%s+%u", r, addr % 4); |
540 | 663e8e51 | ths | } else {
|
541 | 663e8e51 | ths | sprintf(buf, "0x%02x", addr);
|
542 | 663e8e51 | ths | } |
543 | 663e8e51 | ths | } else {
|
544 | 663e8e51 | ths | sprintf(buf, "??? 0x%08x", addr);
|
545 | 663e8e51 | ths | } |
546 | 663e8e51 | ths | return buf;
|
547 | 663e8e51 | ths | } |
548 | 663e8e51 | ths | #endif /* DEBUG_EEPRO100 */ |
549 | 663e8e51 | ths | |
550 | 663e8e51 | ths | #if 0
|
551 | 663e8e51 | ths | static uint16_t eepro100_read_status(EEPRO100State * s)
|
552 | 663e8e51 | ths | {
|
553 | 663e8e51 | ths | uint16_t val = s->status;
|
554 | 663e8e51 | ths | logout("val=0x%04x\n", val);
|
555 | 663e8e51 | ths | return val;
|
556 | 663e8e51 | ths | }
|
557 | 663e8e51 | ths | |
558 | 663e8e51 | ths | static void eepro100_write_status(EEPRO100State * s, uint16_t val)
|
559 | 663e8e51 | ths | {
|
560 | 663e8e51 | ths | logout("val=0x%04x\n", val);
|
561 | 663e8e51 | ths | s->status = val;
|
562 | 663e8e51 | ths | }
|
563 | 663e8e51 | ths | #endif
|
564 | 663e8e51 | ths | |
565 | 663e8e51 | ths | /*****************************************************************************
|
566 | 663e8e51 | ths | *
|
567 | 663e8e51 | ths | * Command emulation.
|
568 | 663e8e51 | ths | *
|
569 | 663e8e51 | ths | ****************************************************************************/
|
570 | 663e8e51 | ths | |
571 | 663e8e51 | ths | #if 0
|
572 | 663e8e51 | ths | static uint16_t eepro100_read_command(EEPRO100State * s)
|
573 | 663e8e51 | ths | {
|
574 | 663e8e51 | ths | uint16_t val = 0xffff;
|
575 | 663e8e51 | ths | //~ logout("val=0x%04x\n", val);
|
576 | 663e8e51 | ths | return val;
|
577 | 663e8e51 | ths | }
|
578 | 663e8e51 | ths | #endif
|
579 | 663e8e51 | ths | |
580 | 663e8e51 | ths | /* Commands that can be put in a command list entry. */
|
581 | 663e8e51 | ths | enum commands {
|
582 | 663e8e51 | ths | CmdNOp = 0,
|
583 | 663e8e51 | ths | CmdIASetup = 1,
|
584 | 663e8e51 | ths | CmdConfigure = 2,
|
585 | 663e8e51 | ths | CmdMulticastList = 3,
|
586 | 663e8e51 | ths | CmdTx = 4,
|
587 | 663e8e51 | ths | CmdTDR = 5, /* load microcode */ |
588 | 663e8e51 | ths | CmdDump = 6,
|
589 | 663e8e51 | ths | CmdDiagnose = 7,
|
590 | 663e8e51 | ths | |
591 | 663e8e51 | ths | /* And some extra flags: */
|
592 | 663e8e51 | ths | CmdSuspend = 0x4000, /* Suspend after completion. */ |
593 | 663e8e51 | ths | CmdIntr = 0x2000, /* Interrupt after completion. */ |
594 | 663e8e51 | ths | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
595 | 663e8e51 | ths | }; |
596 | 663e8e51 | ths | |
597 | 663e8e51 | ths | static cu_state_t get_cu_state(EEPRO100State * s)
|
598 | 663e8e51 | ths | { |
599 | 663e8e51 | ths | return ((s->mem[SCBStatus] >> 6) & 0x03); |
600 | 663e8e51 | ths | } |
601 | 663e8e51 | ths | |
602 | 663e8e51 | ths | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
603 | 663e8e51 | ths | { |
604 | 663e8e51 | ths | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); |
605 | 663e8e51 | ths | } |
606 | 663e8e51 | ths | |
607 | 663e8e51 | ths | static ru_state_t get_ru_state(EEPRO100State * s)
|
608 | 663e8e51 | ths | { |
609 | 663e8e51 | ths | return ((s->mem[SCBStatus] >> 2) & 0x0f); |
610 | 663e8e51 | ths | } |
611 | 663e8e51 | ths | |
612 | 663e8e51 | ths | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
613 | 663e8e51 | ths | { |
614 | 663e8e51 | ths | s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); |
615 | 663e8e51 | ths | } |
616 | 663e8e51 | ths | |
617 | 663e8e51 | ths | static void dump_statistics(EEPRO100State * s) |
618 | 663e8e51 | ths | { |
619 | 663e8e51 | ths | /* Dump statistical data. Most data is never changed by the emulation
|
620 | 663e8e51 | ths | * and always 0, so we first just copy the whole block and then those
|
621 | 663e8e51 | ths | * values which really matter.
|
622 | 663e8e51 | ths | * Number of data should check configuration!!!
|
623 | 663e8e51 | ths | */
|
624 | 663e8e51 | ths | cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
|
625 | 663e8e51 | ths | stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
626 | 663e8e51 | ths | stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
627 | 663e8e51 | ths | stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
628 | 663e8e51 | ths | stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
629 | 663e8e51 | ths | //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
630 | 663e8e51 | ths | //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
631 | 663e8e51 | ths | //~ missing("CU dump statistical counters");
|
632 | 663e8e51 | ths | } |
633 | 663e8e51 | ths | |
634 | 663e8e51 | ths | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
635 | 663e8e51 | ths | { |
636 | 663e8e51 | ths | eepro100_tx_t tx; |
637 | 663e8e51 | ths | uint32_t cb_address; |
638 | 663e8e51 | ths | switch (val) {
|
639 | 663e8e51 | ths | case CU_NOP:
|
640 | 663e8e51 | ths | /* No operation. */
|
641 | 663e8e51 | ths | break;
|
642 | 663e8e51 | ths | case CU_START:
|
643 | 663e8e51 | ths | if (get_cu_state(s) != cu_idle) {
|
644 | 663e8e51 | ths | /* Intel documentation says that CU must be idle for the CU
|
645 | 663e8e51 | ths | * start command. Intel driver for Linux also starts the CU
|
646 | 663e8e51 | ths | * from suspended state. */
|
647 | 663e8e51 | ths | logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
|
648 | 663e8e51 | ths | //~ assert(!"wrong CU state");
|
649 | 663e8e51 | ths | } |
650 | 663e8e51 | ths | set_cu_state(s, cu_active); |
651 | 663e8e51 | ths | s->cu_offset = s->pointer; |
652 | 663e8e51 | ths | next_command:
|
653 | 663e8e51 | ths | cb_address = s->cu_base + s->cu_offset; |
654 | 663e8e51 | ths | cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
|
655 | 663e8e51 | ths | uint16_t status = le16_to_cpu(tx.status); |
656 | 663e8e51 | ths | uint16_t command = le16_to_cpu(tx.command); |
657 | 663e8e51 | ths | logout |
658 | 663e8e51 | ths | ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
659 | 663e8e51 | ths | val, status, command, tx.link); |
660 | 663e8e51 | ths | bool bit_el = ((command & 0x8000) != 0); |
661 | 663e8e51 | ths | bool bit_s = ((command & 0x4000) != 0); |
662 | 663e8e51 | ths | bool bit_i = ((command & 0x2000) != 0); |
663 | 663e8e51 | ths | bool bit_nc = ((command & 0x0010) != 0); |
664 | 663e8e51 | ths | //~ bool bit_sf = ((command & 0x0008) != 0);
|
665 | 663e8e51 | ths | uint16_t cmd = command & 0x0007;
|
666 | 663e8e51 | ths | s->cu_offset = le32_to_cpu(tx.link); |
667 | 663e8e51 | ths | switch (cmd) {
|
668 | 663e8e51 | ths | case CmdNOp:
|
669 | 663e8e51 | ths | /* Do nothing. */
|
670 | 663e8e51 | ths | break;
|
671 | 663e8e51 | ths | case CmdIASetup:
|
672 | 663e8e51 | ths | cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6); |
673 | 663e8e51 | ths | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
674 | 663e8e51 | ths | break;
|
675 | 663e8e51 | ths | case CmdConfigure:
|
676 | 663e8e51 | ths | cpu_physical_memory_read(cb_address + 8, &s->configuration[0], |
677 | 663e8e51 | ths | sizeof(s->configuration));
|
678 | 663e8e51 | ths | logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)); |
679 | 663e8e51 | ths | break;
|
680 | 663e8e51 | ths | case CmdMulticastList:
|
681 | 663e8e51 | ths | //~ missing("multicast list");
|
682 | 663e8e51 | ths | break;
|
683 | 663e8e51 | ths | case CmdTx:
|
684 | 663e8e51 | ths | (void)0; |
685 | 663e8e51 | ths | uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); |
686 | 663e8e51 | ths | uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
|
687 | 663e8e51 | ths | logout |
688 | 663e8e51 | ths | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
689 | 663e8e51 | ths | tbd_array, tcb_bytes, tx.tbd_count); |
690 | 663e8e51 | ths | assert(!bit_nc); |
691 | 663e8e51 | ths | //~ assert(!bit_sf);
|
692 | 663e8e51 | ths | assert(tcb_bytes <= 2600);
|
693 | 663e8e51 | ths | /* Next assertion fails for local configuration. */
|
694 | 663e8e51 | ths | //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
|
695 | 663e8e51 | ths | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
696 | 663e8e51 | ths | logout |
697 | 663e8e51 | ths | ("illegal values of TBD array address and TCB byte count!\n");
|
698 | 663e8e51 | ths | } |
699 | 663e8e51 | ths | uint8_t buf[MAX_ETH_FRAME_SIZE + 4];
|
700 | 663e8e51 | ths | uint16_t size = 0;
|
701 | 663e8e51 | ths | uint32_t tbd_address = cb_address + 0x10;
|
702 | 663e8e51 | ths | assert(tcb_bytes <= sizeof(buf));
|
703 | 663e8e51 | ths | while (size < tcb_bytes) {
|
704 | 663e8e51 | ths | uint32_t tx_buffer_address = ldl_phys(tbd_address); |
705 | 663e8e51 | ths | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
706 | 663e8e51 | ths | //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
707 | 663e8e51 | ths | tbd_address += 8;
|
708 | 663e8e51 | ths | logout |
709 | 663e8e51 | ths | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
710 | 663e8e51 | ths | tx_buffer_address, tx_buffer_size); |
711 | 663e8e51 | ths | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
712 | 663e8e51 | ths | tx_buffer_size); |
713 | 663e8e51 | ths | size += tx_buffer_size; |
714 | 663e8e51 | ths | } |
715 | 663e8e51 | ths | if (tbd_array == 0xffffffff) { |
716 | 663e8e51 | ths | /* Simplified mode. Was already handled by code above. */
|
717 | 663e8e51 | ths | } else {
|
718 | 663e8e51 | ths | /* Flexible mode. */
|
719 | 663e8e51 | ths | uint8_t tbd_count = 0;
|
720 | 663e8e51 | ths | if (!(s->configuration[6] & BIT(4))) { |
721 | 663e8e51 | ths | /* Extended TCB. */
|
722 | 663e8e51 | ths | assert(tcb_bytes == 0);
|
723 | 663e8e51 | ths | for (; tbd_count < 2; tbd_count++) { |
724 | 663e8e51 | ths | uint32_t tx_buffer_address = ldl_phys(tbd_address); |
725 | 663e8e51 | ths | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
726 | 663e8e51 | ths | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
727 | 663e8e51 | ths | tbd_address += 8;
|
728 | 663e8e51 | ths | logout |
729 | 663e8e51 | ths | ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
|
730 | 663e8e51 | ths | tx_buffer_address, tx_buffer_size); |
731 | 663e8e51 | ths | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
732 | 663e8e51 | ths | tx_buffer_size); |
733 | 663e8e51 | ths | size += tx_buffer_size; |
734 | 663e8e51 | ths | if (tx_buffer_el & 1) { |
735 | 663e8e51 | ths | break;
|
736 | 663e8e51 | ths | } |
737 | 663e8e51 | ths | } |
738 | 663e8e51 | ths | } |
739 | 663e8e51 | ths | tbd_address = tbd_array; |
740 | 663e8e51 | ths | for (; tbd_count < tx.tbd_count; tbd_count++) {
|
741 | 663e8e51 | ths | uint32_t tx_buffer_address = ldl_phys(tbd_address); |
742 | 663e8e51 | ths | uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
743 | 663e8e51 | ths | uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
744 | 663e8e51 | ths | tbd_address += 8;
|
745 | 663e8e51 | ths | logout |
746 | 663e8e51 | ths | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
747 | 663e8e51 | ths | tx_buffer_address, tx_buffer_size); |
748 | 663e8e51 | ths | cpu_physical_memory_read(tx_buffer_address, &buf[size], |
749 | 663e8e51 | ths | tx_buffer_size); |
750 | 663e8e51 | ths | size += tx_buffer_size; |
751 | 663e8e51 | ths | if (tx_buffer_el & 1) { |
752 | 663e8e51 | ths | break;
|
753 | 663e8e51 | ths | } |
754 | 663e8e51 | ths | } |
755 | 663e8e51 | ths | } |
756 | 663e8e51 | ths | qemu_send_packet(s->vc, buf, size); |
757 | 663e8e51 | ths | s->statistics.tx_good_frames++; |
758 | 663e8e51 | ths | /* Transmit with bad status would raise an CX/TNO interrupt.
|
759 | 663e8e51 | ths | * (82557 only). Emulation never has bad status. */
|
760 | 663e8e51 | ths | //~ eepro100_cx_interrupt(s);
|
761 | 663e8e51 | ths | break;
|
762 | 663e8e51 | ths | case CmdTDR:
|
763 | 663e8e51 | ths | logout("load microcode\n");
|
764 | 663e8e51 | ths | /* Starting with offset 8, the command contains
|
765 | 663e8e51 | ths | * 64 dwords microcode which we just ignore here. */
|
766 | 663e8e51 | ths | break;
|
767 | 663e8e51 | ths | default:
|
768 | 663e8e51 | ths | missing("undefined command");
|
769 | 663e8e51 | ths | } |
770 | 663e8e51 | ths | /* Write new status (success). */
|
771 | 663e8e51 | ths | stw_phys(cb_address, status | 0x8000 | 0x2000); |
772 | 663e8e51 | ths | if (bit_i) {
|
773 | 663e8e51 | ths | /* CU completed action. */
|
774 | 663e8e51 | ths | eepro100_cx_interrupt(s); |
775 | 663e8e51 | ths | } |
776 | 663e8e51 | ths | if (bit_el) {
|
777 | 663e8e51 | ths | /* CU becomes idle. */
|
778 | 663e8e51 | ths | set_cu_state(s, cu_idle); |
779 | 663e8e51 | ths | eepro100_cna_interrupt(s); |
780 | 663e8e51 | ths | } else if (bit_s) { |
781 | 663e8e51 | ths | /* CU becomes suspended. */
|
782 | 663e8e51 | ths | set_cu_state(s, cu_suspended); |
783 | 663e8e51 | ths | eepro100_cna_interrupt(s); |
784 | 663e8e51 | ths | } else {
|
785 | 663e8e51 | ths | /* More entries in list. */
|
786 | 663e8e51 | ths | logout("CU list with at least one more entry\n");
|
787 | 663e8e51 | ths | goto next_command;
|
788 | 663e8e51 | ths | } |
789 | 663e8e51 | ths | logout("CU list empty\n");
|
790 | 663e8e51 | ths | /* List is empty. Now CU is idle or suspended. */
|
791 | 663e8e51 | ths | break;
|
792 | 663e8e51 | ths | case CU_RESUME:
|
793 | 663e8e51 | ths | if (get_cu_state(s) != cu_suspended) {
|
794 | 663e8e51 | ths | logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
795 | 663e8e51 | ths | /* Workaround for bad Linux eepro100 driver which resumes
|
796 | 663e8e51 | ths | * from idle state. */
|
797 | 663e8e51 | ths | //~ missing("cu resume");
|
798 | 663e8e51 | ths | set_cu_state(s, cu_suspended); |
799 | 663e8e51 | ths | } |
800 | 663e8e51 | ths | if (get_cu_state(s) == cu_suspended) {
|
801 | 663e8e51 | ths | logout("CU resuming\n");
|
802 | 663e8e51 | ths | set_cu_state(s, cu_active); |
803 | 663e8e51 | ths | goto next_command;
|
804 | 663e8e51 | ths | } |
805 | 663e8e51 | ths | break;
|
806 | 663e8e51 | ths | case CU_STATSADDR:
|
807 | 663e8e51 | ths | /* Load dump counters address. */
|
808 | 663e8e51 | ths | s->statsaddr = s->pointer; |
809 | 663e8e51 | ths | logout("val=0x%02x (status address)\n", val);
|
810 | 663e8e51 | ths | break;
|
811 | 663e8e51 | ths | case CU_SHOWSTATS:
|
812 | 663e8e51 | ths | /* Dump statistical counters. */
|
813 | 663e8e51 | ths | dump_statistics(s); |
814 | 663e8e51 | ths | break;
|
815 | 663e8e51 | ths | case CU_CMD_BASE:
|
816 | 663e8e51 | ths | /* Load CU base. */
|
817 | 663e8e51 | ths | logout("val=0x%02x (CU base address)\n", val);
|
818 | 663e8e51 | ths | s->cu_base = s->pointer; |
819 | 663e8e51 | ths | break;
|
820 | 663e8e51 | ths | case CU_DUMPSTATS:
|
821 | 663e8e51 | ths | /* Dump and reset statistical counters. */
|
822 | 663e8e51 | ths | dump_statistics(s); |
823 | 663e8e51 | ths | memset(&s->statistics, 0, sizeof(s->statistics)); |
824 | 663e8e51 | ths | break;
|
825 | 663e8e51 | ths | case CU_SRESUME:
|
826 | 663e8e51 | ths | /* CU static resume. */
|
827 | 663e8e51 | ths | missing("CU static resume");
|
828 | 663e8e51 | ths | break;
|
829 | 663e8e51 | ths | default:
|
830 | 663e8e51 | ths | missing("Undefined CU command");
|
831 | 663e8e51 | ths | } |
832 | 663e8e51 | ths | } |
833 | 663e8e51 | ths | |
834 | 663e8e51 | ths | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
835 | 663e8e51 | ths | { |
836 | 663e8e51 | ths | switch (val) {
|
837 | 663e8e51 | ths | case RU_NOP:
|
838 | 663e8e51 | ths | /* No operation. */
|
839 | 663e8e51 | ths | break;
|
840 | 663e8e51 | ths | case RX_START:
|
841 | 663e8e51 | ths | /* RU start. */
|
842 | 663e8e51 | ths | if (get_ru_state(s) != ru_idle) {
|
843 | 663e8e51 | ths | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
844 | 663e8e51 | ths | //~ assert(!"wrong RU state");
|
845 | 663e8e51 | ths | } |
846 | 663e8e51 | ths | set_ru_state(s, ru_ready); |
847 | 663e8e51 | ths | s->ru_offset = s->pointer; |
848 | 663e8e51 | ths | logout("val=0x%02x (rx start)\n", val);
|
849 | 663e8e51 | ths | break;
|
850 | 663e8e51 | ths | case RX_RESUME:
|
851 | 663e8e51 | ths | /* Restart RU. */
|
852 | 663e8e51 | ths | if (get_ru_state(s) != ru_suspended) {
|
853 | 663e8e51 | ths | logout("RU state is %u, should be %u\n", get_ru_state(s),
|
854 | 663e8e51 | ths | ru_suspended); |
855 | 663e8e51 | ths | //~ assert(!"wrong RU state");
|
856 | 663e8e51 | ths | } |
857 | 663e8e51 | ths | set_ru_state(s, ru_ready); |
858 | 663e8e51 | ths | break;
|
859 | 663e8e51 | ths | case RX_ADDR_LOAD:
|
860 | 663e8e51 | ths | /* Load RU base. */
|
861 | 663e8e51 | ths | logout("val=0x%02x (RU base address)\n", val);
|
862 | 663e8e51 | ths | s->ru_base = s->pointer; |
863 | 663e8e51 | ths | break;
|
864 | 663e8e51 | ths | default:
|
865 | 663e8e51 | ths | logout("val=0x%02x (undefined RU command)\n", val);
|
866 | 663e8e51 | ths | missing("Undefined SU command");
|
867 | 663e8e51 | ths | } |
868 | 663e8e51 | ths | } |
869 | 663e8e51 | ths | |
870 | 663e8e51 | ths | static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
871 | 663e8e51 | ths | { |
872 | 663e8e51 | ths | eepro100_ru_command(s, val & 0x0f);
|
873 | 663e8e51 | ths | eepro100_cu_command(s, val & 0xf0);
|
874 | 663e8e51 | ths | if ((val) == 0) { |
875 | 663e8e51 | ths | logout("val=0x%02x\n", val);
|
876 | 663e8e51 | ths | } |
877 | 663e8e51 | ths | /* Clear command byte after command was accepted. */
|
878 | 663e8e51 | ths | s->mem[SCBCmd] = 0;
|
879 | 663e8e51 | ths | } |
880 | 663e8e51 | ths | |
881 | 663e8e51 | ths | /*****************************************************************************
|
882 | 663e8e51 | ths | *
|
883 | 663e8e51 | ths | * EEPROM emulation.
|
884 | 663e8e51 | ths | *
|
885 | 663e8e51 | ths | ****************************************************************************/
|
886 | 663e8e51 | ths | |
887 | 663e8e51 | ths | #define EEPROM_CS 0x02 |
888 | 663e8e51 | ths | #define EEPROM_SK 0x01 |
889 | 663e8e51 | ths | #define EEPROM_DI 0x04 |
890 | 663e8e51 | ths | #define EEPROM_DO 0x08 |
891 | 663e8e51 | ths | |
892 | 663e8e51 | ths | static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
893 | 663e8e51 | ths | { |
894 | 663e8e51 | ths | uint16_t val; |
895 | 663e8e51 | ths | memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
|
896 | 663e8e51 | ths | if (eeprom93xx_read(s->eeprom)) {
|
897 | 663e8e51 | ths | val |= EEPROM_DO; |
898 | 663e8e51 | ths | } else {
|
899 | 663e8e51 | ths | val &= ~EEPROM_DO; |
900 | 663e8e51 | ths | } |
901 | 663e8e51 | ths | return val;
|
902 | 663e8e51 | ths | } |
903 | 663e8e51 | ths | |
904 | 663e8e51 | ths | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
905 | 663e8e51 | ths | { |
906 | 663e8e51 | ths | logout("write val=0x%02x\n", val);
|
907 | 663e8e51 | ths | |
908 | 663e8e51 | ths | /* mask unwriteable bits */
|
909 | 663e8e51 | ths | //~ val = SET_MASKED(val, 0x31, eeprom->value);
|
910 | 663e8e51 | ths | |
911 | 663e8e51 | ths | int eecs = ((val & EEPROM_CS) != 0); |
912 | 663e8e51 | ths | int eesk = ((val & EEPROM_SK) != 0); |
913 | 663e8e51 | ths | int eedi = ((val & EEPROM_DI) != 0); |
914 | 663e8e51 | ths | eeprom93xx_write(eeprom, eecs, eesk, eedi); |
915 | 663e8e51 | ths | } |
916 | 663e8e51 | ths | |
917 | 663e8e51 | ths | static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) |
918 | 663e8e51 | ths | { |
919 | 663e8e51 | ths | s->pointer = le32_to_cpu(val); |
920 | 663e8e51 | ths | logout("val=0x%08x\n", val);
|
921 | 663e8e51 | ths | } |
922 | 663e8e51 | ths | |
923 | 663e8e51 | ths | /*****************************************************************************
|
924 | 663e8e51 | ths | *
|
925 | 663e8e51 | ths | * MDI emulation.
|
926 | 663e8e51 | ths | *
|
927 | 663e8e51 | ths | ****************************************************************************/
|
928 | 663e8e51 | ths | |
929 | 663e8e51 | ths | #if defined(DEBUG_EEPRO100)
|
930 | 663e8e51 | ths | static const char *mdi_op_name[] = { |
931 | 663e8e51 | ths | "opcode 0",
|
932 | 663e8e51 | ths | "write",
|
933 | 663e8e51 | ths | "read",
|
934 | 663e8e51 | ths | "opcode 3"
|
935 | 663e8e51 | ths | }; |
936 | 663e8e51 | ths | |
937 | 663e8e51 | ths | static const char *mdi_reg_name[] = { |
938 | 663e8e51 | ths | "Control",
|
939 | 663e8e51 | ths | "Status",
|
940 | 663e8e51 | ths | "PHY Identification (Word 1)",
|
941 | 663e8e51 | ths | "PHY Identification (Word 2)",
|
942 | 663e8e51 | ths | "Auto-Negotiation Advertisement",
|
943 | 663e8e51 | ths | "Auto-Negotiation Link Partner Ability",
|
944 | 663e8e51 | ths | "Auto-Negotiation Expansion"
|
945 | 663e8e51 | ths | }; |
946 | 663e8e51 | ths | #endif /* DEBUG_EEPRO100 */ |
947 | 663e8e51 | ths | |
948 | 663e8e51 | ths | static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
949 | 663e8e51 | ths | { |
950 | 663e8e51 | ths | uint32_t val; |
951 | 663e8e51 | ths | memcpy(&val, &s->mem[0x10], sizeof(val)); |
952 | 663e8e51 | ths | |
953 | 663e8e51 | ths | #ifdef DEBUG_EEPRO100
|
954 | 663e8e51 | ths | uint8_t raiseint = (val & BIT(29)) >> 29; |
955 | 663e8e51 | ths | uint8_t opcode = (val & BITS(27, 26)) >> 26; |
956 | 663e8e51 | ths | uint8_t phy = (val & BITS(25, 21)) >> 21; |
957 | 663e8e51 | ths | uint8_t reg = (val & BITS(20, 16)) >> 16; |
958 | 663e8e51 | ths | uint16_t data = (val & BITS(15, 0)); |
959 | 663e8e51 | ths | #endif
|
960 | 663e8e51 | ths | /* Emulation takes no time to finish MDI transaction. */
|
961 | 663e8e51 | ths | val |= BIT(28);
|
962 | 663e8e51 | ths | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
963 | 663e8e51 | ths | val, raiseint, mdi_op_name[opcode], phy, |
964 | 663e8e51 | ths | mdi_reg_name[reg], data)); |
965 | 663e8e51 | ths | return val;
|
966 | 663e8e51 | ths | } |
967 | 663e8e51 | ths | |
968 | 663e8e51 | ths | //~ #define BITS(val, upper, lower) (val & ???)
|
969 | 663e8e51 | ths | static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
970 | 663e8e51 | ths | { |
971 | 663e8e51 | ths | uint8_t raiseint = (val & BIT(29)) >> 29; |
972 | 663e8e51 | ths | uint8_t opcode = (val & BITS(27, 26)) >> 26; |
973 | 663e8e51 | ths | uint8_t phy = (val & BITS(25, 21)) >> 21; |
974 | 663e8e51 | ths | uint8_t reg = (val & BITS(20, 16)) >> 16; |
975 | 663e8e51 | ths | uint16_t data = (val & BITS(15, 0)); |
976 | 663e8e51 | ths | if (phy != 1) { |
977 | 663e8e51 | ths | /* Unsupported PHY address. */
|
978 | 663e8e51 | ths | //~ logout("phy must be 1 but is %u\n", phy);
|
979 | 663e8e51 | ths | data = 0;
|
980 | 663e8e51 | ths | } else if (opcode != 1 && opcode != 2) { |
981 | 663e8e51 | ths | /* Unsupported opcode. */
|
982 | 663e8e51 | ths | logout("opcode must be 1 or 2 but is %u\n", opcode);
|
983 | 663e8e51 | ths | data = 0;
|
984 | 663e8e51 | ths | } else if (reg > 6) { |
985 | 663e8e51 | ths | /* Unsupported register. */
|
986 | 663e8e51 | ths | logout("register must be 0...6 but is %u\n", reg);
|
987 | 663e8e51 | ths | data = 0;
|
988 | 663e8e51 | ths | } else {
|
989 | 663e8e51 | ths | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
990 | 663e8e51 | ths | val, raiseint, mdi_op_name[opcode], phy, |
991 | 663e8e51 | ths | mdi_reg_name[reg], data)); |
992 | 663e8e51 | ths | if (opcode == 1) { |
993 | 663e8e51 | ths | /* MDI write */
|
994 | 663e8e51 | ths | switch (reg) {
|
995 | 663e8e51 | ths | case 0: /* Control Register */ |
996 | 663e8e51 | ths | if (data & 0x8000) { |
997 | 663e8e51 | ths | /* Reset status and control registers to default. */
|
998 | 663e8e51 | ths | s->mdimem[0] = eepro100_mdi_default[0]; |
999 | 663e8e51 | ths | s->mdimem[1] = eepro100_mdi_default[1]; |
1000 | 663e8e51 | ths | data = s->mdimem[reg]; |
1001 | 663e8e51 | ths | } else {
|
1002 | 663e8e51 | ths | /* Restart Auto Configuration = Normal Operation */
|
1003 | 663e8e51 | ths | data &= ~0x0200;
|
1004 | 663e8e51 | ths | } |
1005 | 663e8e51 | ths | break;
|
1006 | 663e8e51 | ths | case 1: /* Status Register */ |
1007 | 663e8e51 | ths | missing("not writable");
|
1008 | 663e8e51 | ths | data = s->mdimem[reg]; |
1009 | 663e8e51 | ths | break;
|
1010 | 663e8e51 | ths | case 2: /* PHY Identification Register (Word 1) */ |
1011 | 663e8e51 | ths | case 3: /* PHY Identification Register (Word 2) */ |
1012 | 663e8e51 | ths | missing("not implemented");
|
1013 | 663e8e51 | ths | break;
|
1014 | 663e8e51 | ths | case 4: /* Auto-Negotiation Advertisement Register */ |
1015 | 663e8e51 | ths | case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1016 | 663e8e51 | ths | break;
|
1017 | 663e8e51 | ths | case 6: /* Auto-Negotiation Expansion Register */ |
1018 | 663e8e51 | ths | default:
|
1019 | 663e8e51 | ths | missing("not implemented");
|
1020 | 663e8e51 | ths | } |
1021 | 663e8e51 | ths | s->mdimem[reg] = data; |
1022 | 663e8e51 | ths | } else if (opcode == 2) { |
1023 | 663e8e51 | ths | /* MDI read */
|
1024 | 663e8e51 | ths | switch (reg) {
|
1025 | 663e8e51 | ths | case 0: /* Control Register */ |
1026 | 663e8e51 | ths | if (data & 0x8000) { |
1027 | 663e8e51 | ths | /* Reset status and control registers to default. */
|
1028 | 663e8e51 | ths | s->mdimem[0] = eepro100_mdi_default[0]; |
1029 | 663e8e51 | ths | s->mdimem[1] = eepro100_mdi_default[1]; |
1030 | 663e8e51 | ths | } |
1031 | 663e8e51 | ths | break;
|
1032 | 663e8e51 | ths | case 1: /* Status Register */ |
1033 | 663e8e51 | ths | s->mdimem[reg] |= 0x0020;
|
1034 | 663e8e51 | ths | break;
|
1035 | 663e8e51 | ths | case 2: /* PHY Identification Register (Word 1) */ |
1036 | 663e8e51 | ths | case 3: /* PHY Identification Register (Word 2) */ |
1037 | 663e8e51 | ths | case 4: /* Auto-Negotiation Advertisement Register */ |
1038 | 663e8e51 | ths | break;
|
1039 | 663e8e51 | ths | case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1040 | 663e8e51 | ths | s->mdimem[reg] = 0x41fe;
|
1041 | 663e8e51 | ths | break;
|
1042 | 663e8e51 | ths | case 6: /* Auto-Negotiation Expansion Register */ |
1043 | 663e8e51 | ths | s->mdimem[reg] = 0x0001;
|
1044 | 663e8e51 | ths | break;
|
1045 | 663e8e51 | ths | } |
1046 | 663e8e51 | ths | data = s->mdimem[reg]; |
1047 | 663e8e51 | ths | } |
1048 | 663e8e51 | ths | /* Emulation takes no time to finish MDI transaction.
|
1049 | 663e8e51 | ths | * Set MDI bit in SCB status register. */
|
1050 | 663e8e51 | ths | s->mem[SCBAck] |= 0x08;
|
1051 | 663e8e51 | ths | val |= BIT(28);
|
1052 | 663e8e51 | ths | if (raiseint) {
|
1053 | 663e8e51 | ths | eepro100_mdi_interrupt(s); |
1054 | 663e8e51 | ths | } |
1055 | 663e8e51 | ths | } |
1056 | 663e8e51 | ths | val = (val & 0xffff0000) + data;
|
1057 | 663e8e51 | ths | memcpy(&s->mem[0x10], &val, sizeof(val)); |
1058 | 663e8e51 | ths | } |
1059 | 663e8e51 | ths | |
1060 | 663e8e51 | ths | /*****************************************************************************
|
1061 | 663e8e51 | ths | *
|
1062 | 663e8e51 | ths | * Port emulation.
|
1063 | 663e8e51 | ths | *
|
1064 | 663e8e51 | ths | ****************************************************************************/
|
1065 | 663e8e51 | ths | |
1066 | 663e8e51 | ths | #define PORT_SOFTWARE_RESET 0 |
1067 | 663e8e51 | ths | #define PORT_SELFTEST 1 |
1068 | 663e8e51 | ths | #define PORT_SELECTIVE_RESET 2 |
1069 | 663e8e51 | ths | #define PORT_DUMP 3 |
1070 | 663e8e51 | ths | #define PORT_SELECTION_MASK 3 |
1071 | 663e8e51 | ths | |
1072 | 663e8e51 | ths | typedef struct { |
1073 | 663e8e51 | ths | uint32_t st_sign; /* Self Test Signature */
|
1074 | 663e8e51 | ths | uint32_t st_result; /* Self Test Results */
|
1075 | 663e8e51 | ths | } eepro100_selftest_t; |
1076 | 663e8e51 | ths | |
1077 | 663e8e51 | ths | static uint32_t eepro100_read_port(EEPRO100State * s)
|
1078 | 663e8e51 | ths | { |
1079 | 663e8e51 | ths | return 0; |
1080 | 663e8e51 | ths | } |
1081 | 663e8e51 | ths | |
1082 | 663e8e51 | ths | static void eepro100_write_port(EEPRO100State * s, uint32_t val) |
1083 | 663e8e51 | ths | { |
1084 | 663e8e51 | ths | val = le32_to_cpu(val); |
1085 | 663e8e51 | ths | uint32_t address = (val & ~PORT_SELECTION_MASK); |
1086 | 663e8e51 | ths | uint8_t selection = (val & PORT_SELECTION_MASK); |
1087 | 663e8e51 | ths | switch (selection) {
|
1088 | 663e8e51 | ths | case PORT_SOFTWARE_RESET:
|
1089 | 663e8e51 | ths | nic_reset(s); |
1090 | 663e8e51 | ths | break;
|
1091 | 663e8e51 | ths | case PORT_SELFTEST:
|
1092 | 663e8e51 | ths | logout("selftest address=0x%08x\n", address);
|
1093 | 663e8e51 | ths | eepro100_selftest_t data; |
1094 | 663e8e51 | ths | cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
|
1095 | 663e8e51 | ths | data.st_sign = 0xffffffff;
|
1096 | 663e8e51 | ths | data.st_result = 0;
|
1097 | 663e8e51 | ths | cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
|
1098 | 663e8e51 | ths | break;
|
1099 | 663e8e51 | ths | case PORT_SELECTIVE_RESET:
|
1100 | 663e8e51 | ths | logout("selective reset, selftest address=0x%08x\n", address);
|
1101 | 663e8e51 | ths | nic_selective_reset(s); |
1102 | 663e8e51 | ths | break;
|
1103 | 663e8e51 | ths | default:
|
1104 | 663e8e51 | ths | logout("val=0x%08x\n", val);
|
1105 | 663e8e51 | ths | missing("unknown port selection");
|
1106 | 663e8e51 | ths | } |
1107 | 663e8e51 | ths | } |
1108 | 663e8e51 | ths | |
1109 | 663e8e51 | ths | /*****************************************************************************
|
1110 | 663e8e51 | ths | *
|
1111 | 663e8e51 | ths | * General hardware emulation.
|
1112 | 663e8e51 | ths | *
|
1113 | 663e8e51 | ths | ****************************************************************************/
|
1114 | 663e8e51 | ths | |
1115 | 663e8e51 | ths | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
1116 | 663e8e51 | ths | { |
1117 | 663e8e51 | ths | uint8_t val; |
1118 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1119 | 663e8e51 | ths | memcpy(&val, &s->mem[addr], sizeof(val));
|
1120 | 663e8e51 | ths | } |
1121 | 663e8e51 | ths | |
1122 | 663e8e51 | ths | switch (addr) {
|
1123 | 663e8e51 | ths | case SCBStatus:
|
1124 | 663e8e51 | ths | //~ val = eepro100_read_status(s);
|
1125 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1126 | 663e8e51 | ths | break;
|
1127 | 663e8e51 | ths | case SCBAck:
|
1128 | 663e8e51 | ths | //~ val = eepro100_read_status(s);
|
1129 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1130 | 663e8e51 | ths | break;
|
1131 | 663e8e51 | ths | case SCBCmd:
|
1132 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1133 | 663e8e51 | ths | //~ val = eepro100_read_command(s);
|
1134 | 663e8e51 | ths | break;
|
1135 | 663e8e51 | ths | case SCBIntmask:
|
1136 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1137 | 663e8e51 | ths | break;
|
1138 | 663e8e51 | ths | case SCBPort + 3: |
1139 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1140 | 663e8e51 | ths | break;
|
1141 | 663e8e51 | ths | case SCBeeprom:
|
1142 | 663e8e51 | ths | val = eepro100_read_eeprom(s); |
1143 | 663e8e51 | ths | break;
|
1144 | 663e8e51 | ths | case 0x1b: /* PMDR (power management driver register) */ |
1145 | 663e8e51 | ths | val = 0;
|
1146 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1147 | 663e8e51 | ths | break;
|
1148 | 663e8e51 | ths | case 0x1d: /* general status register */ |
1149 | 663e8e51 | ths | /* 100 Mbps full duplex, valid link */
|
1150 | 663e8e51 | ths | val = 0x07;
|
1151 | 663e8e51 | ths | logout("addr=General Status val=%02x\n", val);
|
1152 | 663e8e51 | ths | break;
|
1153 | 663e8e51 | ths | default:
|
1154 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1155 | 663e8e51 | ths | missing("unknown byte read");
|
1156 | 663e8e51 | ths | } |
1157 | 663e8e51 | ths | return val;
|
1158 | 663e8e51 | ths | } |
1159 | 663e8e51 | ths | |
1160 | 663e8e51 | ths | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
1161 | 663e8e51 | ths | { |
1162 | 663e8e51 | ths | uint16_t val; |
1163 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1164 | 663e8e51 | ths | memcpy(&val, &s->mem[addr], sizeof(val));
|
1165 | 663e8e51 | ths | } |
1166 | 663e8e51 | ths | |
1167 | 663e8e51 | ths | logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1168 | 663e8e51 | ths | |
1169 | 663e8e51 | ths | switch (addr) {
|
1170 | 663e8e51 | ths | case SCBStatus:
|
1171 | 663e8e51 | ths | //~ val = eepro100_read_status(s);
|
1172 | 663e8e51 | ths | break;
|
1173 | 663e8e51 | ths | case SCBeeprom:
|
1174 | 663e8e51 | ths | val = eepro100_read_eeprom(s); |
1175 | 663e8e51 | ths | break;
|
1176 | 663e8e51 | ths | default:
|
1177 | 663e8e51 | ths | logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1178 | 663e8e51 | ths | missing("unknown word read");
|
1179 | 663e8e51 | ths | } |
1180 | 663e8e51 | ths | return val;
|
1181 | 663e8e51 | ths | } |
1182 | 663e8e51 | ths | |
1183 | 663e8e51 | ths | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
1184 | 663e8e51 | ths | { |
1185 | 663e8e51 | ths | uint32_t val; |
1186 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1187 | 663e8e51 | ths | memcpy(&val, &s->mem[addr], sizeof(val));
|
1188 | 663e8e51 | ths | } |
1189 | 663e8e51 | ths | |
1190 | 663e8e51 | ths | switch (addr) {
|
1191 | 663e8e51 | ths | case SCBStatus:
|
1192 | 663e8e51 | ths | //~ val = eepro100_read_status(s);
|
1193 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1194 | 663e8e51 | ths | break;
|
1195 | 663e8e51 | ths | case SCBPointer:
|
1196 | 663e8e51 | ths | //~ val = eepro100_read_pointer(s);
|
1197 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1198 | 663e8e51 | ths | break;
|
1199 | 663e8e51 | ths | case SCBPort:
|
1200 | 663e8e51 | ths | val = eepro100_read_port(s); |
1201 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1202 | 663e8e51 | ths | break;
|
1203 | 663e8e51 | ths | case SCBCtrlMDI:
|
1204 | 663e8e51 | ths | val = eepro100_read_mdi(s); |
1205 | 663e8e51 | ths | break;
|
1206 | 663e8e51 | ths | default:
|
1207 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1208 | 663e8e51 | ths | missing("unknown longword read");
|
1209 | 663e8e51 | ths | } |
1210 | 663e8e51 | ths | return val;
|
1211 | 663e8e51 | ths | } |
1212 | 663e8e51 | ths | |
1213 | 663e8e51 | ths | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
1214 | 663e8e51 | ths | { |
1215 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1216 | 663e8e51 | ths | memcpy(&s->mem[addr], &val, sizeof(val));
|
1217 | 663e8e51 | ths | } |
1218 | 663e8e51 | ths | |
1219 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1220 | 663e8e51 | ths | |
1221 | 663e8e51 | ths | switch (addr) {
|
1222 | 663e8e51 | ths | case SCBStatus:
|
1223 | 663e8e51 | ths | //~ eepro100_write_status(s, val);
|
1224 | 663e8e51 | ths | break;
|
1225 | 663e8e51 | ths | case SCBAck:
|
1226 | 663e8e51 | ths | eepro100_acknowledge(s); |
1227 | 663e8e51 | ths | break;
|
1228 | 663e8e51 | ths | case SCBCmd:
|
1229 | 663e8e51 | ths | eepro100_write_command(s, val); |
1230 | 663e8e51 | ths | break;
|
1231 | 663e8e51 | ths | case SCBIntmask:
|
1232 | 663e8e51 | ths | if (val & BIT(1)) { |
1233 | 663e8e51 | ths | eepro100_swi_interrupt(s); |
1234 | 663e8e51 | ths | } |
1235 | 663e8e51 | ths | eepro100_interrupt(s, 0);
|
1236 | 663e8e51 | ths | break;
|
1237 | 663e8e51 | ths | case SCBPort + 3: |
1238 | 3257d2b6 | ths | case SCBFlow:
|
1239 | 3257d2b6 | ths | case SCBFlow + 1: |
1240 | 3257d2b6 | ths | case SCBFlow + 2: |
1241 | 3257d2b6 | ths | case SCBFlow + 3: |
1242 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1243 | 663e8e51 | ths | break;
|
1244 | 663e8e51 | ths | case SCBeeprom:
|
1245 | 663e8e51 | ths | eepro100_write_eeprom(s->eeprom, val); |
1246 | 663e8e51 | ths | break;
|
1247 | 663e8e51 | ths | default:
|
1248 | 663e8e51 | ths | logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1249 | 663e8e51 | ths | missing("unknown byte write");
|
1250 | 663e8e51 | ths | } |
1251 | 663e8e51 | ths | } |
1252 | 663e8e51 | ths | |
1253 | 663e8e51 | ths | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
1254 | 663e8e51 | ths | { |
1255 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1256 | 663e8e51 | ths | memcpy(&s->mem[addr], &val, sizeof(val));
|
1257 | 663e8e51 | ths | } |
1258 | 663e8e51 | ths | |
1259 | 663e8e51 | ths | logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1260 | 663e8e51 | ths | |
1261 | 663e8e51 | ths | switch (addr) {
|
1262 | 663e8e51 | ths | case SCBStatus:
|
1263 | 663e8e51 | ths | //~ eepro100_write_status(s, val);
|
1264 | 663e8e51 | ths | eepro100_acknowledge(s); |
1265 | 663e8e51 | ths | break;
|
1266 | 663e8e51 | ths | case SCBCmd:
|
1267 | 663e8e51 | ths | eepro100_write_command(s, val); |
1268 | 663e8e51 | ths | eepro100_write1(s, SCBIntmask, val >> 8);
|
1269 | 663e8e51 | ths | break;
|
1270 | 663e8e51 | ths | case SCBeeprom:
|
1271 | 663e8e51 | ths | eepro100_write_eeprom(s->eeprom, val); |
1272 | 663e8e51 | ths | break;
|
1273 | 663e8e51 | ths | default:
|
1274 | 663e8e51 | ths | logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1275 | 663e8e51 | ths | missing("unknown word write");
|
1276 | 663e8e51 | ths | } |
1277 | 663e8e51 | ths | } |
1278 | 663e8e51 | ths | |
1279 | 663e8e51 | ths | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
1280 | 663e8e51 | ths | { |
1281 | 663e8e51 | ths | if (addr <= sizeof(s->mem) - sizeof(val)) { |
1282 | 663e8e51 | ths | memcpy(&s->mem[addr], &val, sizeof(val));
|
1283 | 663e8e51 | ths | } |
1284 | 663e8e51 | ths | |
1285 | 663e8e51 | ths | switch (addr) {
|
1286 | 663e8e51 | ths | case SCBPointer:
|
1287 | 663e8e51 | ths | eepro100_write_pointer(s, val); |
1288 | 663e8e51 | ths | break;
|
1289 | 663e8e51 | ths | case SCBPort:
|
1290 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1291 | 663e8e51 | ths | eepro100_write_port(s, val); |
1292 | 663e8e51 | ths | break;
|
1293 | 663e8e51 | ths | case SCBCtrlMDI:
|
1294 | 663e8e51 | ths | eepro100_write_mdi(s, val); |
1295 | 663e8e51 | ths | break;
|
1296 | 663e8e51 | ths | default:
|
1297 | 663e8e51 | ths | logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1298 | 663e8e51 | ths | missing("unknown longword write");
|
1299 | 663e8e51 | ths | } |
1300 | 663e8e51 | ths | } |
1301 | 663e8e51 | ths | |
1302 | 663e8e51 | ths | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1303 | 663e8e51 | ths | { |
1304 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1305 | 663e8e51 | ths | //~ logout("addr=%s\n", regname(addr));
|
1306 | 663e8e51 | ths | return eepro100_read1(s, addr - s->region[1]); |
1307 | 663e8e51 | ths | } |
1308 | 663e8e51 | ths | |
1309 | 663e8e51 | ths | static uint32_t ioport_read2(void *opaque, uint32_t addr) |
1310 | 663e8e51 | ths | { |
1311 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1312 | 663e8e51 | ths | return eepro100_read2(s, addr - s->region[1]); |
1313 | 663e8e51 | ths | } |
1314 | 663e8e51 | ths | |
1315 | 663e8e51 | ths | static uint32_t ioport_read4(void *opaque, uint32_t addr) |
1316 | 663e8e51 | ths | { |
1317 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1318 | 663e8e51 | ths | return eepro100_read4(s, addr - s->region[1]); |
1319 | 663e8e51 | ths | } |
1320 | 663e8e51 | ths | |
1321 | 663e8e51 | ths | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
1322 | 663e8e51 | ths | { |
1323 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1324 | 663e8e51 | ths | //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1325 | 663e8e51 | ths | eepro100_write1(s, addr - s->region[1], val);
|
1326 | 663e8e51 | ths | } |
1327 | 663e8e51 | ths | |
1328 | 663e8e51 | ths | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
1329 | 663e8e51 | ths | { |
1330 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1331 | 663e8e51 | ths | eepro100_write2(s, addr - s->region[1], val);
|
1332 | 663e8e51 | ths | } |
1333 | 663e8e51 | ths | |
1334 | 663e8e51 | ths | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
1335 | 663e8e51 | ths | { |
1336 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1337 | 663e8e51 | ths | eepro100_write4(s, addr - s->region[1], val);
|
1338 | 663e8e51 | ths | } |
1339 | 663e8e51 | ths | |
1340 | 663e8e51 | ths | /***********************************************************/
|
1341 | 663e8e51 | ths | /* PCI EEPRO100 definitions */
|
1342 | 663e8e51 | ths | |
1343 | 663e8e51 | ths | typedef struct PCIEEPRO100State { |
1344 | 663e8e51 | ths | PCIDevice dev; |
1345 | 663e8e51 | ths | EEPRO100State eepro100; |
1346 | 663e8e51 | ths | } PCIEEPRO100State; |
1347 | 663e8e51 | ths | |
1348 | 663e8e51 | ths | static void pci_map(PCIDevice * pci_dev, int region_num, |
1349 | 663e8e51 | ths | uint32_t addr, uint32_t size, int type)
|
1350 | 663e8e51 | ths | { |
1351 | 663e8e51 | ths | PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev; |
1352 | 663e8e51 | ths | EEPRO100State *s = &d->eepro100; |
1353 | 663e8e51 | ths | |
1354 | 663e8e51 | ths | logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
1355 | 663e8e51 | ths | region_num, addr, size, type); |
1356 | 663e8e51 | ths | |
1357 | 663e8e51 | ths | assert(region_num == 1);
|
1358 | 663e8e51 | ths | register_ioport_write(addr, size, 1, ioport_write1, s);
|
1359 | 663e8e51 | ths | register_ioport_read(addr, size, 1, ioport_read1, s);
|
1360 | 663e8e51 | ths | register_ioport_write(addr, size, 2, ioport_write2, s);
|
1361 | 663e8e51 | ths | register_ioport_read(addr, size, 2, ioport_read2, s);
|
1362 | 663e8e51 | ths | register_ioport_write(addr, size, 4, ioport_write4, s);
|
1363 | 663e8e51 | ths | register_ioport_read(addr, size, 4, ioport_read4, s);
|
1364 | 663e8e51 | ths | |
1365 | 663e8e51 | ths | s->region[region_num] = addr; |
1366 | 663e8e51 | ths | } |
1367 | 663e8e51 | ths | |
1368 | 663e8e51 | ths | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1369 | 663e8e51 | ths | { |
1370 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1371 | 663e8e51 | ths | //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1372 | 663e8e51 | ths | eepro100_write1(s, addr, val); |
1373 | 663e8e51 | ths | } |
1374 | 663e8e51 | ths | |
1375 | 663e8e51 | ths | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1376 | 663e8e51 | ths | { |
1377 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1378 | 663e8e51 | ths | //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1379 | 663e8e51 | ths | eepro100_write2(s, addr, val); |
1380 | 663e8e51 | ths | } |
1381 | 663e8e51 | ths | |
1382 | 663e8e51 | ths | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1383 | 663e8e51 | ths | { |
1384 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1385 | 663e8e51 | ths | //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1386 | 663e8e51 | ths | eepro100_write4(s, addr, val); |
1387 | 663e8e51 | ths | } |
1388 | 663e8e51 | ths | |
1389 | 663e8e51 | ths | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
1390 | 663e8e51 | ths | { |
1391 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1392 | 663e8e51 | ths | //~ logout("addr=%s\n", regname(addr));
|
1393 | 663e8e51 | ths | return eepro100_read1(s, addr);
|
1394 | 663e8e51 | ths | } |
1395 | 663e8e51 | ths | |
1396 | 663e8e51 | ths | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
1397 | 663e8e51 | ths | { |
1398 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1399 | 663e8e51 | ths | //~ logout("addr=%s\n", regname(addr));
|
1400 | 663e8e51 | ths | return eepro100_read2(s, addr);
|
1401 | 663e8e51 | ths | } |
1402 | 663e8e51 | ths | |
1403 | 663e8e51 | ths | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
1404 | 663e8e51 | ths | { |
1405 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1406 | 663e8e51 | ths | //~ logout("addr=%s\n", regname(addr));
|
1407 | 663e8e51 | ths | return eepro100_read4(s, addr);
|
1408 | 663e8e51 | ths | } |
1409 | 663e8e51 | ths | |
1410 | 663e8e51 | ths | static CPUWriteMemoryFunc *pci_mmio_write[] = {
|
1411 | 663e8e51 | ths | pci_mmio_writeb, |
1412 | 663e8e51 | ths | pci_mmio_writew, |
1413 | 663e8e51 | ths | pci_mmio_writel |
1414 | 663e8e51 | ths | }; |
1415 | 663e8e51 | ths | |
1416 | 663e8e51 | ths | static CPUReadMemoryFunc *pci_mmio_read[] = {
|
1417 | 663e8e51 | ths | pci_mmio_readb, |
1418 | 663e8e51 | ths | pci_mmio_readw, |
1419 | 663e8e51 | ths | pci_mmio_readl |
1420 | 663e8e51 | ths | }; |
1421 | 663e8e51 | ths | |
1422 | 663e8e51 | ths | static void pci_mmio_map(PCIDevice * pci_dev, int region_num, |
1423 | 663e8e51 | ths | uint32_t addr, uint32_t size, int type)
|
1424 | 663e8e51 | ths | { |
1425 | 663e8e51 | ths | PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev; |
1426 | 663e8e51 | ths | |
1427 | 663e8e51 | ths | logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
1428 | 663e8e51 | ths | region_num, addr, size, type); |
1429 | 663e8e51 | ths | |
1430 | 663e8e51 | ths | if (region_num == 0) { |
1431 | 663e8e51 | ths | /* Map control / status registers. */
|
1432 | 663e8e51 | ths | cpu_register_physical_memory(addr, size, d->eepro100.mmio_index); |
1433 | 663e8e51 | ths | d->eepro100.region[region_num] = addr; |
1434 | 663e8e51 | ths | } |
1435 | 663e8e51 | ths | } |
1436 | 663e8e51 | ths | |
1437 | 663e8e51 | ths | static int nic_can_receive(void *opaque) |
1438 | 663e8e51 | ths | { |
1439 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1440 | 663e8e51 | ths | logout("%p\n", s);
|
1441 | 663e8e51 | ths | return get_ru_state(s) == ru_ready;
|
1442 | 663e8e51 | ths | //~ return !eepro100_buffer_full(s);
|
1443 | 663e8e51 | ths | } |
1444 | 663e8e51 | ths | |
1445 | 663e8e51 | ths | static void nic_receive(void *opaque, const uint8_t * buf, int size) |
1446 | 663e8e51 | ths | { |
1447 | 663e8e51 | ths | /* TODO:
|
1448 | 663e8e51 | ths | * - Magic packets should set bit 30 in power management driver register.
|
1449 | 663e8e51 | ths | * - Interesting packets should set bit 29 in power management driver register.
|
1450 | 663e8e51 | ths | */
|
1451 | 663e8e51 | ths | EEPRO100State *s = opaque; |
1452 | 663e8e51 | ths | uint16_t rfd_status = 0xa000;
|
1453 | 663e8e51 | ths | static const uint8_t broadcast_macaddr[6] = |
1454 | 663e8e51 | ths | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
1455 | 663e8e51 | ths | |
1456 | 663e8e51 | ths | /* TODO: check multiple IA bit. */
|
1457 | 663e8e51 | ths | assert(!(s->configuration[20] & BIT(6))); |
1458 | 663e8e51 | ths | |
1459 | 663e8e51 | ths | if (s->configuration[8] & 0x80) { |
1460 | 663e8e51 | ths | /* CSMA is disabled. */
|
1461 | 663e8e51 | ths | logout("%p received while CSMA is disabled\n", s);
|
1462 | 663e8e51 | ths | return;
|
1463 | 663e8e51 | ths | } else if (size < 64 && (s->configuration[7] & 1)) { |
1464 | 663e8e51 | ths | /* Short frame and configuration byte 7/0 (discard short receive) set:
|
1465 | 663e8e51 | ths | * Short frame is discarded */
|
1466 | 663e8e51 | ths | logout("%p received short frame (%d byte)\n", s, size);
|
1467 | 663e8e51 | ths | s->statistics.rx_short_frame_errors++; |
1468 | 663e8e51 | ths | //~ return;
|
1469 | 663e8e51 | ths | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1470 | 663e8e51 | ths | /* Long frame and configuration byte 18/3 (long receive ok) not set:
|
1471 | 663e8e51 | ths | * Long frames are discarded. */
|
1472 | 663e8e51 | ths | logout("%p received long frame (%d byte), ignored\n", s, size);
|
1473 | 663e8e51 | ths | return;
|
1474 | 663e8e51 | ths | } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!! |
1475 | 663e8e51 | ths | /* Frame matches individual address. */
|
1476 | 663e8e51 | ths | /* TODO: check configuration byte 15/4 (ignore U/L). */
|
1477 | 663e8e51 | ths | logout("%p received frame for me, len=%d\n", s, size);
|
1478 | 663e8e51 | ths | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1479 | 663e8e51 | ths | /* Broadcast frame. */
|
1480 | 663e8e51 | ths | logout("%p received broadcast, len=%d\n", s, size);
|
1481 | 663e8e51 | ths | rfd_status |= 0x0002;
|
1482 | 663e8e51 | ths | } else if (buf[0] & 0x01) { // !!! |
1483 | 663e8e51 | ths | /* Multicast frame. */
|
1484 | 663e8e51 | ths | logout("%p received multicast, len=%d\n", s, size);
|
1485 | 663e8e51 | ths | /* TODO: check multicast all bit. */
|
1486 | 663e8e51 | ths | assert(!(s->configuration[21] & BIT(3))); |
1487 | 663e8e51 | ths | int mcast_idx = compute_mcast_idx(buf);
|
1488 | 663e8e51 | ths | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
1489 | 663e8e51 | ths | return;
|
1490 | 663e8e51 | ths | } |
1491 | 663e8e51 | ths | rfd_status |= 0x0002;
|
1492 | 663e8e51 | ths | } else if (s->configuration[15] & 1) { |
1493 | 663e8e51 | ths | /* Promiscuous: receive all. */
|
1494 | 663e8e51 | ths | logout("%p received frame in promiscuous mode, len=%d\n", s, size);
|
1495 | 663e8e51 | ths | rfd_status |= 0x0004;
|
1496 | 663e8e51 | ths | } else {
|
1497 | 663e8e51 | ths | logout("%p received frame, ignored, len=%d,%s\n", s, size,
|
1498 | 663e8e51 | ths | nic_dump(buf, size)); |
1499 | 663e8e51 | ths | return;
|
1500 | 663e8e51 | ths | } |
1501 | 663e8e51 | ths | |
1502 | 663e8e51 | ths | if (get_ru_state(s) != ru_ready) {
|
1503 | 663e8e51 | ths | /* No ressources available. */
|
1504 | 663e8e51 | ths | logout("no ressources, state=%u\n", get_ru_state(s));
|
1505 | 663e8e51 | ths | s->statistics.rx_resource_errors++; |
1506 | 663e8e51 | ths | //~ assert(!"no ressources");
|
1507 | 663e8e51 | ths | return;
|
1508 | 663e8e51 | ths | } |
1509 | 663e8e51 | ths | //~ !!!
|
1510 | 663e8e51 | ths | //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
1511 | 663e8e51 | ths | eepro100_rx_t rx; |
1512 | 663e8e51 | ths | cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
1513 | 663e8e51 | ths | offsetof(eepro100_rx_t, packet)); |
1514 | 663e8e51 | ths | uint16_t rfd_command = le16_to_cpu(rx.command); |
1515 | 663e8e51 | ths | uint16_t rfd_size = le16_to_cpu(rx.size); |
1516 | 663e8e51 | ths | assert(size <= rfd_size); |
1517 | 663e8e51 | ths | if (size < 64) { |
1518 | 663e8e51 | ths | rfd_status |= 0x0080;
|
1519 | 663e8e51 | ths | } |
1520 | 663e8e51 | ths | logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
|
1521 | 663e8e51 | ths | rx.link, rx.rx_buf_addr, rfd_size); |
1522 | 663e8e51 | ths | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
1523 | 663e8e51 | ths | rfd_status); |
1524 | 663e8e51 | ths | stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
1525 | 663e8e51 | ths | /* Early receive interrupt not supported. */
|
1526 | 663e8e51 | ths | //~ eepro100_er_interrupt(s);
|
1527 | 663e8e51 | ths | /* Receive CRC Transfer not supported. */
|
1528 | 663e8e51 | ths | assert(!(s->configuration[18] & 4)); |
1529 | 663e8e51 | ths | /* TODO: check stripping enable bit. */
|
1530 | 663e8e51 | ths | //~ assert(!(s->configuration[17] & 1));
|
1531 | 663e8e51 | ths | cpu_physical_memory_write(s->ru_base + s->ru_offset + |
1532 | 663e8e51 | ths | offsetof(eepro100_rx_t, packet), buf, size); |
1533 | 663e8e51 | ths | s->statistics.rx_good_frames++; |
1534 | 663e8e51 | ths | eepro100_fr_interrupt(s); |
1535 | 663e8e51 | ths | s->ru_offset = le32_to_cpu(rx.link); |
1536 | 663e8e51 | ths | if (rfd_command & 0x8000) { |
1537 | 663e8e51 | ths | /* EL bit is set, so this was the last frame. */
|
1538 | 663e8e51 | ths | assert(0);
|
1539 | 663e8e51 | ths | } |
1540 | 663e8e51 | ths | if (rfd_command & 0x4000) { |
1541 | 663e8e51 | ths | /* S bit is set. */
|
1542 | 663e8e51 | ths | set_ru_state(s, ru_suspended); |
1543 | 663e8e51 | ths | } |
1544 | 663e8e51 | ths | } |
1545 | 663e8e51 | ths | |
1546 | 663e8e51 | ths | static int nic_load(QEMUFile * f, void *opaque, int version_id) |
1547 | 663e8e51 | ths | { |
1548 | 663e8e51 | ths | EEPRO100State *s = (EEPRO100State *) opaque; |
1549 | 2657c663 | balrog | int i;
|
1550 | 663e8e51 | ths | int ret;
|
1551 | 663e8e51 | ths | |
1552 | 663e8e51 | ths | if (version_id > 3) |
1553 | 663e8e51 | ths | return -EINVAL;
|
1554 | 663e8e51 | ths | |
1555 | 663e8e51 | ths | if (s->pci_dev && version_id >= 3) { |
1556 | 663e8e51 | ths | ret = pci_device_load(s->pci_dev, f); |
1557 | 663e8e51 | ths | if (ret < 0) |
1558 | 663e8e51 | ths | return ret;
|
1559 | 663e8e51 | ths | } |
1560 | 663e8e51 | ths | |
1561 | 663e8e51 | ths | if (version_id >= 2) { |
1562 | 663e8e51 | ths | qemu_get_8s(f, &s->rxcr); |
1563 | 663e8e51 | ths | } else {
|
1564 | 663e8e51 | ths | s->rxcr = 0x0c;
|
1565 | 663e8e51 | ths | } |
1566 | 663e8e51 | ths | |
1567 | 663e8e51 | ths | qemu_get_8s(f, &s->cmd); |
1568 | 663e8e51 | ths | qemu_get_be32s(f, &s->start); |
1569 | 663e8e51 | ths | qemu_get_be32s(f, &s->stop); |
1570 | 663e8e51 | ths | qemu_get_8s(f, &s->boundary); |
1571 | 663e8e51 | ths | qemu_get_8s(f, &s->tsr); |
1572 | 663e8e51 | ths | qemu_get_8s(f, &s->tpsr); |
1573 | 663e8e51 | ths | qemu_get_be16s(f, &s->tcnt); |
1574 | 663e8e51 | ths | qemu_get_be16s(f, &s->rcnt); |
1575 | 663e8e51 | ths | qemu_get_be32s(f, &s->rsar); |
1576 | 663e8e51 | ths | qemu_get_8s(f, &s->rsr); |
1577 | 663e8e51 | ths | qemu_get_8s(f, &s->isr); |
1578 | 663e8e51 | ths | qemu_get_8s(f, &s->dcfg); |
1579 | 663e8e51 | ths | qemu_get_8s(f, &s->imr); |
1580 | 663e8e51 | ths | qemu_get_buffer(f, s->phys, 6);
|
1581 | 663e8e51 | ths | qemu_get_8s(f, &s->curpag); |
1582 | 663e8e51 | ths | qemu_get_buffer(f, s->mult, 8);
|
1583 | 663e8e51 | ths | qemu_get_buffer(f, s->mem, sizeof(s->mem));
|
1584 | 663e8e51 | ths | |
1585 | 2657c663 | balrog | /* Restore all members of struct between scv_stat and mem */
|
1586 | 2657c663 | balrog | qemu_get_8s(f, &s->scb_stat); |
1587 | 2657c663 | balrog | qemu_get_8s(f, &s->int_stat); |
1588 | 2657c663 | balrog | for (i = 0; i < 3; i++) |
1589 | 2657c663 | balrog | qemu_get_be32s(f, &s->region[i]); |
1590 | 2657c663 | balrog | qemu_get_buffer(f, s->macaddr, 6);
|
1591 | 5fafdf24 | ths | for (i = 0; i < 19; i++) |
1592 | 2657c663 | balrog | qemu_get_be32s(f, &s->statcounter[i]); |
1593 | 2657c663 | balrog | for (i = 0; i < 32; i++) |
1594 | 2657c663 | balrog | qemu_get_be16s(f, &s->mdimem[i]); |
1595 | 2657c663 | balrog | /* The eeprom should be saved and restored by its own routines */
|
1596 | 2657c663 | balrog | qemu_get_be32s(f, &s->device); |
1597 | 2657c663 | balrog | qemu_get_be32s(f, &s->pointer); |
1598 | 2657c663 | balrog | qemu_get_be32s(f, &s->cu_base); |
1599 | 2657c663 | balrog | qemu_get_be32s(f, &s->cu_offset); |
1600 | 2657c663 | balrog | qemu_get_be32s(f, &s->ru_base); |
1601 | 2657c663 | balrog | qemu_get_be32s(f, &s->ru_offset); |
1602 | 2657c663 | balrog | qemu_get_be32s(f, &s->statsaddr); |
1603 | 2657c663 | balrog | /* Restore epro100_stats_t statistics */
|
1604 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_good_frames); |
1605 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_max_collisions); |
1606 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_late_collisions); |
1607 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_underruns); |
1608 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_lost_crs); |
1609 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_deferred); |
1610 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_single_collisions); |
1611 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_multiple_collisions); |
1612 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.tx_total_collisions); |
1613 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_good_frames); |
1614 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_crc_errors); |
1615 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_alignment_errors); |
1616 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_resource_errors); |
1617 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_overrun_errors); |
1618 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_cdt_errors); |
1619 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.rx_short_frame_errors); |
1620 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.fc_xmt_pause); |
1621 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.fc_rcv_pause); |
1622 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported); |
1623 | 2657c663 | balrog | qemu_get_be16s(f, &s->statistics.xmt_tco_frames); |
1624 | 2657c663 | balrog | qemu_get_be16s(f, &s->statistics.rcv_tco_frames); |
1625 | 2657c663 | balrog | qemu_get_be32s(f, &s->statistics.complete); |
1626 | 2657c663 | balrog | #if 0
|
1627 | 2657c663 | balrog | qemu_get_be16s(f, &s->status);
|
1628 | 2657c663 | balrog | #endif
|
1629 | 2657c663 | balrog | |
1630 | 2657c663 | balrog | /* Configuration bytes. */
|
1631 | 2657c663 | balrog | qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
|
1632 | 2657c663 | balrog | |
1633 | 663e8e51 | ths | return 0; |
1634 | 663e8e51 | ths | } |
1635 | 663e8e51 | ths | |
1636 | 663e8e51 | ths | static void nic_save(QEMUFile * f, void *opaque) |
1637 | 663e8e51 | ths | { |
1638 | 663e8e51 | ths | EEPRO100State *s = (EEPRO100State *) opaque; |
1639 | 2657c663 | balrog | int i;
|
1640 | 663e8e51 | ths | |
1641 | 663e8e51 | ths | if (s->pci_dev)
|
1642 | 663e8e51 | ths | pci_device_save(s->pci_dev, f); |
1643 | 663e8e51 | ths | |
1644 | 663e8e51 | ths | qemu_put_8s(f, &s->rxcr); |
1645 | 663e8e51 | ths | |
1646 | 663e8e51 | ths | qemu_put_8s(f, &s->cmd); |
1647 | 663e8e51 | ths | qemu_put_be32s(f, &s->start); |
1648 | 663e8e51 | ths | qemu_put_be32s(f, &s->stop); |
1649 | 663e8e51 | ths | qemu_put_8s(f, &s->boundary); |
1650 | 663e8e51 | ths | qemu_put_8s(f, &s->tsr); |
1651 | 663e8e51 | ths | qemu_put_8s(f, &s->tpsr); |
1652 | 663e8e51 | ths | qemu_put_be16s(f, &s->tcnt); |
1653 | 663e8e51 | ths | qemu_put_be16s(f, &s->rcnt); |
1654 | 663e8e51 | ths | qemu_put_be32s(f, &s->rsar); |
1655 | 663e8e51 | ths | qemu_put_8s(f, &s->rsr); |
1656 | 663e8e51 | ths | qemu_put_8s(f, &s->isr); |
1657 | 663e8e51 | ths | qemu_put_8s(f, &s->dcfg); |
1658 | 663e8e51 | ths | qemu_put_8s(f, &s->imr); |
1659 | 663e8e51 | ths | qemu_put_buffer(f, s->phys, 6);
|
1660 | 663e8e51 | ths | qemu_put_8s(f, &s->curpag); |
1661 | 663e8e51 | ths | qemu_put_buffer(f, s->mult, 8);
|
1662 | 663e8e51 | ths | qemu_put_buffer(f, s->mem, sizeof(s->mem));
|
1663 | 2657c663 | balrog | |
1664 | 2657c663 | balrog | /* Save all members of struct between scv_stat and mem */
|
1665 | 2657c663 | balrog | qemu_put_8s(f, &s->scb_stat); |
1666 | 2657c663 | balrog | qemu_put_8s(f, &s->int_stat); |
1667 | 2657c663 | balrog | for (i = 0; i < 3; i++) |
1668 | 2657c663 | balrog | qemu_put_be32s(f, &s->region[i]); |
1669 | 2657c663 | balrog | qemu_put_buffer(f, s->macaddr, 6);
|
1670 | 5fafdf24 | ths | for (i = 0; i < 19; i++) |
1671 | 2657c663 | balrog | qemu_put_be32s(f, &s->statcounter[i]); |
1672 | 2657c663 | balrog | for (i = 0; i < 32; i++) |
1673 | 2657c663 | balrog | qemu_put_be16s(f, &s->mdimem[i]); |
1674 | 2657c663 | balrog | /* The eeprom should be saved and restored by its own routines */
|
1675 | 2657c663 | balrog | qemu_put_be32s(f, &s->device); |
1676 | 2657c663 | balrog | qemu_put_be32s(f, &s->pointer); |
1677 | 2657c663 | balrog | qemu_put_be32s(f, &s->cu_base); |
1678 | 2657c663 | balrog | qemu_put_be32s(f, &s->cu_offset); |
1679 | 2657c663 | balrog | qemu_put_be32s(f, &s->ru_base); |
1680 | 2657c663 | balrog | qemu_put_be32s(f, &s->ru_offset); |
1681 | 2657c663 | balrog | qemu_put_be32s(f, &s->statsaddr); |
1682 | 2657c663 | balrog | /* Save epro100_stats_t statistics */
|
1683 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_good_frames); |
1684 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_max_collisions); |
1685 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_late_collisions); |
1686 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_underruns); |
1687 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_lost_crs); |
1688 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_deferred); |
1689 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_single_collisions); |
1690 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_multiple_collisions); |
1691 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.tx_total_collisions); |
1692 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_good_frames); |
1693 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_crc_errors); |
1694 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_alignment_errors); |
1695 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_resource_errors); |
1696 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_overrun_errors); |
1697 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_cdt_errors); |
1698 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.rx_short_frame_errors); |
1699 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.fc_xmt_pause); |
1700 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.fc_rcv_pause); |
1701 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported); |
1702 | 2657c663 | balrog | qemu_put_be16s(f, &s->statistics.xmt_tco_frames); |
1703 | 2657c663 | balrog | qemu_put_be16s(f, &s->statistics.rcv_tco_frames); |
1704 | 2657c663 | balrog | qemu_put_be32s(f, &s->statistics.complete); |
1705 | 2657c663 | balrog | #if 0
|
1706 | 2657c663 | balrog | qemu_put_be16s(f, &s->status);
|
1707 | 2657c663 | balrog | #endif
|
1708 | 2657c663 | balrog | |
1709 | 2657c663 | balrog | /* Configuration bytes. */
|
1710 | 2657c663 | balrog | qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
|
1711 | 663e8e51 | ths | } |
1712 | 663e8e51 | ths | |
1713 | b946a153 | aliguori | static void nic_cleanup(VLANClientState *vc) |
1714 | b946a153 | aliguori | { |
1715 | b946a153 | aliguori | EEPRO100State *s = vc->opaque; |
1716 | b946a153 | aliguori | |
1717 | b946a153 | aliguori | unregister_savevm(vc->model, s); |
1718 | b946a153 | aliguori | |
1719 | b946a153 | aliguori | eeprom93xx_free(s->eeprom); |
1720 | b946a153 | aliguori | } |
1721 | b946a153 | aliguori | |
1722 | b946a153 | aliguori | static int pci_nic_uninit(PCIDevice *dev) |
1723 | b946a153 | aliguori | { |
1724 | b946a153 | aliguori | PCIEEPRO100State *d = (PCIEEPRO100State *) dev; |
1725 | b946a153 | aliguori | EEPRO100State *s = &d->eepro100; |
1726 | b946a153 | aliguori | |
1727 | b946a153 | aliguori | cpu_unregister_io_memory(s->mmio_index); |
1728 | b946a153 | aliguori | |
1729 | b946a153 | aliguori | return 0; |
1730 | b946a153 | aliguori | } |
1731 | b946a153 | aliguori | |
1732 | 32a8f6ae | aliguori | static PCIDevice *nic_init(PCIBus * bus, NICInfo * nd, uint32_t device)
|
1733 | 663e8e51 | ths | { |
1734 | 663e8e51 | ths | PCIEEPRO100State *d; |
1735 | 663e8e51 | ths | EEPRO100State *s; |
1736 | 663e8e51 | ths | |
1737 | 663e8e51 | ths | logout("\n");
|
1738 | 663e8e51 | ths | |
1739 | 32a8f6ae | aliguori | d = (PCIEEPRO100State *) pci_register_device(bus, nd->model, |
1740 | 663e8e51 | ths | sizeof(PCIEEPRO100State), -1, |
1741 | 663e8e51 | ths | NULL, NULL); |
1742 | b946a153 | aliguori | d->dev.unregister = pci_nic_uninit; |
1743 | 663e8e51 | ths | |
1744 | 663e8e51 | ths | s = &d->eepro100; |
1745 | 663e8e51 | ths | s->device = device; |
1746 | 663e8e51 | ths | s->pci_dev = &d->dev; |
1747 | 663e8e51 | ths | |
1748 | 663e8e51 | ths | pci_reset(s); |
1749 | 663e8e51 | ths | |
1750 | 663e8e51 | ths | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
1751 | 663e8e51 | ths | * i82559 and later support 64 or 256 word EEPROM. */
|
1752 | 663e8e51 | ths | s->eeprom = eeprom93xx_new(EEPROM_SIZE); |
1753 | 663e8e51 | ths | |
1754 | 663e8e51 | ths | /* Handler for memory-mapped I/O */
|
1755 | 663e8e51 | ths | d->eepro100.mmio_index = |
1756 | 663e8e51 | ths | cpu_register_io_memory(0, pci_mmio_read, pci_mmio_write, s);
|
1757 | 663e8e51 | ths | |
1758 | 663e8e51 | ths | pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,
|
1759 | 663e8e51 | ths | PCI_ADDRESS_SPACE_MEM | |
1760 | 663e8e51 | ths | PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map); |
1761 | 663e8e51 | ths | pci_register_io_region(&d->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
|
1762 | 663e8e51 | ths | pci_map); |
1763 | 663e8e51 | ths | pci_register_io_region(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
|
1764 | 663e8e51 | ths | pci_mmio_map); |
1765 | 663e8e51 | ths | |
1766 | 663e8e51 | ths | memcpy(s->macaddr, nd->macaddr, 6);
|
1767 | 663e8e51 | ths | logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1768 | 663e8e51 | ths | assert(s->region[1] == 0); |
1769 | 663e8e51 | ths | |
1770 | 663e8e51 | ths | nic_reset(s); |
1771 | 663e8e51 | ths | |
1772 | 7a9f6e4a | aliguori | s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
1773 | b946a153 | aliguori | nic_receive, nic_can_receive, |
1774 | b946a153 | aliguori | nic_cleanup, s); |
1775 | 663e8e51 | ths | |
1776 | 7cb7434b | aliguori | qemu_format_nic_info_str(s->vc, s->macaddr); |
1777 | 663e8e51 | ths | |
1778 | 663e8e51 | ths | qemu_register_reset(nic_reset, s); |
1779 | 663e8e51 | ths | |
1780 | 32a8f6ae | aliguori | register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s); |
1781 | 72da4208 | aliguori | return (PCIDevice *)d;
|
1782 | 663e8e51 | ths | } |
1783 | 663e8e51 | ths | |
1784 | 72da4208 | aliguori | PCIDevice *pci_i82551_init(PCIBus * bus, NICInfo * nd, int devfn)
|
1785 | 663e8e51 | ths | { |
1786 | 32a8f6ae | aliguori | return nic_init(bus, nd, i82551);
|
1787 | 663e8e51 | ths | } |
1788 | 663e8e51 | ths | |
1789 | 72da4208 | aliguori | PCIDevice *pci_i82557b_init(PCIBus * bus, NICInfo * nd, int devfn)
|
1790 | 663e8e51 | ths | { |
1791 | 32a8f6ae | aliguori | return nic_init(bus, nd, i82557B);
|
1792 | 663e8e51 | ths | } |
1793 | 663e8e51 | ths | |
1794 | 72da4208 | aliguori | PCIDevice *pci_i82559er_init(PCIBus * bus, NICInfo * nd, int devfn)
|
1795 | 663e8e51 | ths | { |
1796 | 32a8f6ae | aliguori | return nic_init(bus, nd, i82559ER);
|
1797 | 663e8e51 | ths | } |
1798 | 663e8e51 | ths | |
1799 | 663e8e51 | ths | /* eof */ |