root / hw / sh_pci.c @ 4870852c
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1 | 1e5459a3 | balrog | /*
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2 | 1e5459a3 | balrog | * SuperH on-chip PCIC emulation.
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3 | 1e5459a3 | balrog | *
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4 | 1e5459a3 | balrog | * Copyright (c) 2008 Takashi YOSHII
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5 | 1e5459a3 | balrog | *
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6 | 1e5459a3 | balrog | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1e5459a3 | balrog | * of this software and associated documentation files (the "Software"), to deal
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8 | 1e5459a3 | balrog | * in the Software without restriction, including without limitation the rights
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9 | 1e5459a3 | balrog | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1e5459a3 | balrog | * copies of the Software, and to permit persons to whom the Software is
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11 | 1e5459a3 | balrog | * furnished to do so, subject to the following conditions:
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12 | 1e5459a3 | balrog | *
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13 | 1e5459a3 | balrog | * The above copyright notice and this permission notice shall be included in
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14 | 1e5459a3 | balrog | * all copies or substantial portions of the Software.
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15 | 1e5459a3 | balrog | *
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16 | 1e5459a3 | balrog | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1e5459a3 | balrog | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1e5459a3 | balrog | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1e5459a3 | balrog | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1e5459a3 | balrog | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1e5459a3 | balrog | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1e5459a3 | balrog | * THE SOFTWARE.
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23 | 1e5459a3 | balrog | */
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24 | 1e5459a3 | balrog | #include "hw.h" |
25 | 1e5459a3 | balrog | #include "sh.h" |
26 | 1e5459a3 | balrog | #include "pci.h" |
27 | 1e5459a3 | balrog | #include "bswap.h" |
28 | 1e5459a3 | balrog | |
29 | 1e5459a3 | balrog | typedef struct { |
30 | 1e5459a3 | balrog | PCIBus *bus; |
31 | 1e5459a3 | balrog | PCIDevice *dev; |
32 | 1e5459a3 | balrog | uint32_t par; |
33 | 1e5459a3 | balrog | uint32_t mbr; |
34 | 1e5459a3 | balrog | uint32_t iobr; |
35 | 1e5459a3 | balrog | } SHPCIC; |
36 | 1e5459a3 | balrog | |
37 | 1e5459a3 | balrog | static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
38 | 1e5459a3 | balrog | { |
39 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
40 | 1e5459a3 | balrog | switch(addr) {
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41 | 1e5459a3 | balrog | case 0 ... 0xfc: |
42 | 1e5459a3 | balrog | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
43 | 1e5459a3 | balrog | break;
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44 | 1e5459a3 | balrog | case 0x1c0: |
45 | 1e5459a3 | balrog | pcic->par = val; |
46 | 1e5459a3 | balrog | break;
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47 | 1e5459a3 | balrog | case 0x1c4: |
48 | 1e5459a3 | balrog | pcic->mbr = val; |
49 | 1e5459a3 | balrog | break;
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50 | 1e5459a3 | balrog | case 0x1c8: |
51 | 1e5459a3 | balrog | pcic->iobr = val; |
52 | 1e5459a3 | balrog | break;
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53 | 1e5459a3 | balrog | case 0x220: |
54 | 1e5459a3 | balrog | pci_data_write(pcic->bus, pcic->par, val, 4);
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55 | 1e5459a3 | balrog | break;
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56 | 1e5459a3 | balrog | } |
57 | 1e5459a3 | balrog | } |
58 | 1e5459a3 | balrog | |
59 | 1e5459a3 | balrog | static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
60 | 1e5459a3 | balrog | { |
61 | 1e5459a3 | balrog | SHPCIC *pcic = p; |
62 | 1e5459a3 | balrog | switch(addr) {
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63 | 1e5459a3 | balrog | case 0 ... 0xfc: |
64 | 1e5459a3 | balrog | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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65 | 1e5459a3 | balrog | case 0x1c0: |
66 | 1e5459a3 | balrog | return pcic->par;
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67 | 1e5459a3 | balrog | case 0x220: |
68 | 1e5459a3 | balrog | return pci_data_read(pcic->bus, pcic->par, 4); |
69 | 1e5459a3 | balrog | } |
70 | 1e5459a3 | balrog | return 0; |
71 | 1e5459a3 | balrog | } |
72 | 1e5459a3 | balrog | |
73 | 1e5459a3 | balrog | static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, |
74 | 1e5459a3 | balrog | uint32_t val, int size)
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75 | 1e5459a3 | balrog | { |
76 | d0ef528a | balrog | pci_data_write(pcic->bus, addr + pcic->mbr, val, size); |
77 | 1e5459a3 | balrog | } |
78 | 1e5459a3 | balrog | |
79 | 1e5459a3 | balrog | static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
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80 | 1e5459a3 | balrog | int size)
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81 | 1e5459a3 | balrog | { |
82 | d0ef528a | balrog | return pci_data_read(pcic->bus, addr + pcic->mbr, size);
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83 | 1e5459a3 | balrog | } |
84 | 1e5459a3 | balrog | |
85 | 1e5459a3 | balrog | static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) |
86 | 1e5459a3 | balrog | { |
87 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 1);
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88 | 1e5459a3 | balrog | } |
89 | 1e5459a3 | balrog | |
90 | 1e5459a3 | balrog | static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val) |
91 | 1e5459a3 | balrog | { |
92 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 2);
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93 | 1e5459a3 | balrog | } |
94 | 1e5459a3 | balrog | |
95 | 1e5459a3 | balrog | static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val) |
96 | 1e5459a3 | balrog | { |
97 | 1e5459a3 | balrog | sh_pci_data_write(p, addr, val, 4);
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98 | 1e5459a3 | balrog | } |
99 | 1e5459a3 | balrog | |
100 | 1e5459a3 | balrog | static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr) |
101 | 1e5459a3 | balrog | { |
102 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 1); |
103 | 1e5459a3 | balrog | } |
104 | 1e5459a3 | balrog | |
105 | 1e5459a3 | balrog | static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr) |
106 | 1e5459a3 | balrog | { |
107 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 2); |
108 | 1e5459a3 | balrog | } |
109 | 1e5459a3 | balrog | |
110 | 1e5459a3 | balrog | static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) |
111 | 1e5459a3 | balrog | { |
112 | 1e5459a3 | balrog | return sh_pci_mem_read(p, addr, 4); |
113 | 1e5459a3 | balrog | } |
114 | 1e5459a3 | balrog | |
115 | 1e5459a3 | balrog | static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) |
116 | 1e5459a3 | balrog | { |
117 | d0ef528a | balrog | return addr + pcic->iobr;
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118 | 1e5459a3 | balrog | } |
119 | 1e5459a3 | balrog | |
120 | 1e5459a3 | balrog | static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) |
121 | 1e5459a3 | balrog | { |
122 | 1e5459a3 | balrog | cpu_outb(NULL, sh_pci_addr2port(p, addr), val);
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123 | 1e5459a3 | balrog | } |
124 | 1e5459a3 | balrog | |
125 | 1e5459a3 | balrog | static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val) |
126 | 1e5459a3 | balrog | { |
127 | 1e5459a3 | balrog | cpu_outw(NULL, sh_pci_addr2port(p, addr), val);
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128 | 1e5459a3 | balrog | } |
129 | 1e5459a3 | balrog | |
130 | 1e5459a3 | balrog | static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val) |
131 | 1e5459a3 | balrog | { |
132 | 1e5459a3 | balrog | cpu_outl(NULL, sh_pci_addr2port(p, addr), val);
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133 | 1e5459a3 | balrog | } |
134 | 1e5459a3 | balrog | |
135 | 1e5459a3 | balrog | static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr) |
136 | 1e5459a3 | balrog | { |
137 | 1e5459a3 | balrog | return cpu_inb(NULL, sh_pci_addr2port(p, addr)); |
138 | 1e5459a3 | balrog | } |
139 | 1e5459a3 | balrog | |
140 | 1e5459a3 | balrog | static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr) |
141 | 1e5459a3 | balrog | { |
142 | 1e5459a3 | balrog | return cpu_inw(NULL, sh_pci_addr2port(p, addr)); |
143 | 1e5459a3 | balrog | } |
144 | 1e5459a3 | balrog | |
145 | 1e5459a3 | balrog | static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr) |
146 | 1e5459a3 | balrog | { |
147 | 1e5459a3 | balrog | return cpu_inl(NULL, sh_pci_addr2port(p, addr)); |
148 | 1e5459a3 | balrog | } |
149 | 1e5459a3 | balrog | |
150 | 1e5459a3 | balrog | typedef struct { |
151 | 1e5459a3 | balrog | CPUReadMemoryFunc *r[3];
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152 | 1e5459a3 | balrog | CPUWriteMemoryFunc *w[3];
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153 | 1e5459a3 | balrog | } MemOp; |
154 | 1e5459a3 | balrog | |
155 | 1e5459a3 | balrog | static MemOp sh_pci_reg = {
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156 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_read }, |
157 | 1e5459a3 | balrog | { NULL, NULL, sh_pci_reg_write }, |
158 | 1e5459a3 | balrog | }; |
159 | 1e5459a3 | balrog | |
160 | 1e5459a3 | balrog | static MemOp sh_pci_mem = {
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161 | 1e5459a3 | balrog | { sh_pci_readb, sh_pci_readw, sh_pci_readl }, |
162 | 1e5459a3 | balrog | { sh_pci_writeb, sh_pci_writew, sh_pci_writel }, |
163 | 1e5459a3 | balrog | }; |
164 | 1e5459a3 | balrog | |
165 | 1e5459a3 | balrog | static MemOp sh_pci_iop = {
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166 | 1e5459a3 | balrog | { sh_pci_inb, sh_pci_inw, sh_pci_inl }, |
167 | 1e5459a3 | balrog | { sh_pci_outb, sh_pci_outw, sh_pci_outl }, |
168 | 1e5459a3 | balrog | }; |
169 | 1e5459a3 | balrog | |
170 | 1e5459a3 | balrog | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
171 | 1e5459a3 | balrog | qemu_irq *pic, int devfn_min, int nirq) |
172 | 1e5459a3 | balrog | { |
173 | 1e5459a3 | balrog | SHPCIC *p; |
174 | 1e5459a3 | balrog | int mem, reg, iop;
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175 | 1e5459a3 | balrog | |
176 | 1e5459a3 | balrog | p = qemu_mallocz(sizeof(SHPCIC));
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177 | 1e5459a3 | balrog | p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq); |
178 | 1e5459a3 | balrog | |
179 | 1e5459a3 | balrog | p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), |
180 | 1e5459a3 | balrog | -1, NULL, NULL); |
181 | 1e5459a3 | balrog | reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
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182 | 1e5459a3 | balrog | iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
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183 | ac2e8522 | aurel32 | mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
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184 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1e200000, 0x224, reg); |
185 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1e240000, 0x40000, iop); |
186 | ac2e8522 | aurel32 | cpu_register_physical_memory(0x1d000000, 0x1000000, mem); |
187 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfe200000, 0x224, reg); |
188 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfe240000, 0x40000, iop); |
189 | ac2e8522 | aurel32 | cpu_register_physical_memory(0xfd000000, 0x1000000, mem); |
190 | 1e5459a3 | balrog | |
191 | deb54399 | aliguori | pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI); |
192 | a770dc7e | aliguori | pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R); |
193 | 1e5459a3 | balrog | p->dev->config[0x04] = 0x80; |
194 | 1e5459a3 | balrog | p->dev->config[0x05] = 0x00; |
195 | 1e5459a3 | balrog | p->dev->config[0x06] = 0x90; |
196 | 1e5459a3 | balrog | p->dev->config[0x07] = 0x02; |
197 | 1e5459a3 | balrog | |
198 | 1e5459a3 | balrog | return p->bus;
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199 | 1e5459a3 | balrog | } |