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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU Uninorth PCI host (for all Mac99 and newer machines)
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc_mac.h" |
26 | 87ecb68b | pbrook | #include "pci.h" |
27 | 87ecb68b | pbrook | |
28 | f3902383 | blueswir1 | /* debug UniNorth */
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29 | f3902383 | blueswir1 | //#define DEBUG_UNIN
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30 | f3902383 | blueswir1 | |
31 | f3902383 | blueswir1 | #ifdef DEBUG_UNIN
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32 | f3902383 | blueswir1 | #define UNIN_DPRINTF(fmt, args...) \
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33 | f3902383 | blueswir1 | do { printf("UNIN: " fmt , ##args); } while (0) |
34 | f3902383 | blueswir1 | #else
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35 | f3902383 | blueswir1 | #define UNIN_DPRINTF(fmt, args...)
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36 | f3902383 | blueswir1 | #endif
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37 | f3902383 | blueswir1 | |
38 | 502a5395 | pbrook | typedef target_phys_addr_t pci_addr_t;
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39 | 502a5395 | pbrook | #include "pci_host.h" |
40 | 502a5395 | pbrook | |
41 | 502a5395 | pbrook | typedef PCIHostState UNINState;
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42 | 502a5395 | pbrook | |
43 | 502a5395 | pbrook | static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
44 | 502a5395 | pbrook | uint32_t val) |
45 | 502a5395 | pbrook | { |
46 | 502a5395 | pbrook | UNINState *s = opaque; |
47 | 502a5395 | pbrook | |
48 | f3902383 | blueswir1 | UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val); |
49 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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50 | 502a5395 | pbrook | val = bswap32(val); |
51 | 502a5395 | pbrook | #endif
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52 | 502a5395 | pbrook | |
53 | e972b3ad | blueswir1 | s->config_reg = val; |
54 | 502a5395 | pbrook | } |
55 | 502a5395 | pbrook | |
56 | 502a5395 | pbrook | static uint32_t pci_unin_main_config_readl (void *opaque, |
57 | 502a5395 | pbrook | target_phys_addr_t addr) |
58 | 502a5395 | pbrook | { |
59 | 502a5395 | pbrook | UNINState *s = opaque; |
60 | 502a5395 | pbrook | uint32_t val; |
61 | 502a5395 | pbrook | |
62 | e972b3ad | blueswir1 | val = s->config_reg; |
63 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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64 | 502a5395 | pbrook | val = bswap32(val); |
65 | 502a5395 | pbrook | #endif
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66 | f3902383 | blueswir1 | UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val); |
67 | 502a5395 | pbrook | |
68 | 502a5395 | pbrook | return val;
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69 | 502a5395 | pbrook | } |
70 | 502a5395 | pbrook | |
71 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
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72 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
73 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
74 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
75 | 502a5395 | pbrook | }; |
76 | 502a5395 | pbrook | |
77 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
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78 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
79 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
80 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
81 | 502a5395 | pbrook | }; |
82 | 502a5395 | pbrook | |
83 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_main_write[] = {
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84 | 502a5395 | pbrook | &pci_host_data_writeb, |
85 | 502a5395 | pbrook | &pci_host_data_writew, |
86 | 502a5395 | pbrook | &pci_host_data_writel, |
87 | 502a5395 | pbrook | }; |
88 | 502a5395 | pbrook | |
89 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_main_read[] = {
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90 | 502a5395 | pbrook | &pci_host_data_readb, |
91 | 502a5395 | pbrook | &pci_host_data_readw, |
92 | 502a5395 | pbrook | &pci_host_data_readl, |
93 | 502a5395 | pbrook | }; |
94 | 502a5395 | pbrook | |
95 | 502a5395 | pbrook | static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
96 | 502a5395 | pbrook | uint32_t val) |
97 | 502a5395 | pbrook | { |
98 | 502a5395 | pbrook | UNINState *s = opaque; |
99 | 502a5395 | pbrook | |
100 | 783a20dc | blueswir1 | s->config_reg = val; |
101 | 502a5395 | pbrook | } |
102 | 502a5395 | pbrook | |
103 | 502a5395 | pbrook | static uint32_t pci_unin_config_readl (void *opaque, |
104 | 502a5395 | pbrook | target_phys_addr_t addr) |
105 | 502a5395 | pbrook | { |
106 | 502a5395 | pbrook | UNINState *s = opaque; |
107 | 502a5395 | pbrook | |
108 | 783a20dc | blueswir1 | return s->config_reg;
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109 | 502a5395 | pbrook | } |
110 | 502a5395 | pbrook | |
111 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_config_write[] = {
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112 | 502a5395 | pbrook | &pci_unin_config_writel, |
113 | 502a5395 | pbrook | &pci_unin_config_writel, |
114 | 502a5395 | pbrook | &pci_unin_config_writel, |
115 | 502a5395 | pbrook | }; |
116 | 502a5395 | pbrook | |
117 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_config_read[] = {
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118 | 502a5395 | pbrook | &pci_unin_config_readl, |
119 | 502a5395 | pbrook | &pci_unin_config_readl, |
120 | 502a5395 | pbrook | &pci_unin_config_readl, |
121 | 502a5395 | pbrook | }; |
122 | 502a5395 | pbrook | |
123 | 783a20dc | blueswir1 | #if 0
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124 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_write[] = {
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125 | 502a5395 | pbrook | &pci_host_pci_writeb,
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126 | 502a5395 | pbrook | &pci_host_pci_writew,
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127 | 502a5395 | pbrook | &pci_host_pci_writel,
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128 | 502a5395 | pbrook | };
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129 | 502a5395 | pbrook | |
130 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_read[] = {
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131 | 502a5395 | pbrook | &pci_host_pci_readb,
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132 | 502a5395 | pbrook | &pci_host_pci_readw,
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133 | 502a5395 | pbrook | &pci_host_pci_readl,
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134 | 502a5395 | pbrook | };
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135 | 502a5395 | pbrook | #endif
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136 | 502a5395 | pbrook | |
137 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
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138 | d2b59317 | pbrook | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
139 | 502a5395 | pbrook | { |
140 | d2b59317 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
141 | d2b59317 | pbrook | } |
142 | d2b59317 | pbrook | |
143 | d537cf6c | pbrook | static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level) |
144 | d2b59317 | pbrook | { |
145 | d537cf6c | pbrook | qemu_set_irq(pic[irq_num + 8], level);
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146 | 502a5395 | pbrook | } |
147 | 502a5395 | pbrook | |
148 | f3902383 | blueswir1 | static void pci_unin_save(QEMUFile* f, void *opaque) |
149 | f3902383 | blueswir1 | { |
150 | f3902383 | blueswir1 | PCIDevice *d = opaque; |
151 | f3902383 | blueswir1 | |
152 | f3902383 | blueswir1 | pci_device_save(d, f); |
153 | f3902383 | blueswir1 | } |
154 | f3902383 | blueswir1 | |
155 | f3902383 | blueswir1 | static int pci_unin_load(QEMUFile* f, void *opaque, int version_id) |
156 | f3902383 | blueswir1 | { |
157 | f3902383 | blueswir1 | PCIDevice *d = opaque; |
158 | f3902383 | blueswir1 | |
159 | f3902383 | blueswir1 | if (version_id != 1) |
160 | f3902383 | blueswir1 | return -EINVAL;
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161 | f3902383 | blueswir1 | |
162 | f3902383 | blueswir1 | return pci_device_load(d, f);
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163 | f3902383 | blueswir1 | } |
164 | f3902383 | blueswir1 | |
165 | f3902383 | blueswir1 | static void pci_unin_reset(void *opaque) |
166 | f3902383 | blueswir1 | { |
167 | f3902383 | blueswir1 | } |
168 | f3902383 | blueswir1 | |
169 | d537cf6c | pbrook | PCIBus *pci_pmac_init(qemu_irq *pic) |
170 | 502a5395 | pbrook | { |
171 | 502a5395 | pbrook | UNINState *s; |
172 | 502a5395 | pbrook | PCIDevice *d; |
173 | 502a5395 | pbrook | int pci_mem_config, pci_mem_data;
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174 | 502a5395 | pbrook | |
175 | 502a5395 | pbrook | /* Use values found on a real PowerMac */
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176 | 502a5395 | pbrook | /* Uninorth main bus */
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177 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(UNINState));
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178 | d2b59317 | pbrook | s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq, |
179 | 80b3ada7 | pbrook | pic, 11 << 3, 4); |
180 | 502a5395 | pbrook | |
181 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
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182 | 502a5395 | pbrook | pci_unin_main_config_write, s); |
183 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
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184 | 502a5395 | pbrook | pci_unin_main_write, s); |
185 | 502a5395 | pbrook | cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
186 | 502a5395 | pbrook | cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
187 | 5fafdf24 | ths | d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice), |
188 | 502a5395 | pbrook | 11 << 3, NULL, NULL); |
189 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
190 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI); |
191 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
192 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
193 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
194 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
195 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type |
196 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer |
197 | 502a5395 | pbrook | |
198 | 9f083493 | ths | #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
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199 | 502a5395 | pbrook | /* pci-to-pci bridge */
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200 | 502a5395 | pbrook | d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
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201 | 502a5395 | pbrook | NULL, NULL);
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202 | 4ebcf884 | blueswir1 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
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203 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
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204 | 502a5395 | pbrook | d->config[0x08] = 0x05; // revision
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205 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
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206 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size
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207 | 502a5395 | pbrook | d->config[0x0D] = 0x20; // latency_timer
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208 | 502a5395 | pbrook | d->config[0x0E] = 0x01; // header_type
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209 | 502a5395 | pbrook | |
210 | 502a5395 | pbrook | d->config[0x18] = 0x01; // primary_bus
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211 | 502a5395 | pbrook | d->config[0x19] = 0x02; // secondary_bus
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212 | 502a5395 | pbrook | d->config[0x1A] = 0x02; // subordinate_bus
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213 | 502a5395 | pbrook | d->config[0x1B] = 0x20; // secondary_latency_timer
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214 | 502a5395 | pbrook | d->config[0x1C] = 0x11; // io_base
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215 | 502a5395 | pbrook | d->config[0x1D] = 0x01; // io_limit
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216 | 502a5395 | pbrook | d->config[0x20] = 0x00; // memory_base
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217 | 502a5395 | pbrook | d->config[0x21] = 0x80;
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218 | 502a5395 | pbrook | d->config[0x22] = 0x00; // memory_limit
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219 | 502a5395 | pbrook | d->config[0x23] = 0x80;
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220 | 502a5395 | pbrook | d->config[0x24] = 0x01; // prefetchable_memory_base
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221 | 502a5395 | pbrook | d->config[0x25] = 0x80;
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222 | 502a5395 | pbrook | d->config[0x26] = 0xF1; // prefectchable_memory_limit
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223 | 502a5395 | pbrook | d->config[0x27] = 0x7F;
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224 | 502a5395 | pbrook | // d->config[0x34] = 0xdc // capabilities_pointer
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225 | 502a5395 | pbrook | #endif
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226 | 783a20dc | blueswir1 | |
227 | 502a5395 | pbrook | /* Uninorth AGP bus */
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228 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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229 | 502a5395 | pbrook | pci_unin_config_write, s); |
230 | 783a20dc | blueswir1 | pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
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231 | 783a20dc | blueswir1 | pci_unin_main_write, s); |
232 | 502a5395 | pbrook | cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config); |
233 | 502a5395 | pbrook | cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data); |
234 | 502a5395 | pbrook | |
235 | 783a20dc | blueswir1 | d = pci_register_device(s->bus, "Uni-north AGP", sizeof(PCIDevice), |
236 | 783a20dc | blueswir1 | 11 << 3, NULL, NULL); |
237 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
238 | deb54399 | aliguori | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); |
239 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
240 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
241 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
242 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
243 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type |
244 | 502a5395 | pbrook | // d->config[0x34] = 0x80; // capabilities_pointer
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245 | 502a5395 | pbrook | |
246 | 502a5395 | pbrook | #if 0 // XXX: not needed for now
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247 | 502a5395 | pbrook | /* Uninorth internal bus */
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248 | 502a5395 | pbrook | s = &pci_bridge[2];
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249 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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250 | 502a5395 | pbrook | pci_unin_config_write, s);
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251 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
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252 | 502a5395 | pbrook | pci_unin_write, s);
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253 | 502a5395 | pbrook | cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
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254 | 502a5395 | pbrook | cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
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255 | 502a5395 | pbrook | |
256 | 502a5395 | pbrook | d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
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257 | 502a5395 | pbrook | 3, 11 << 3, NULL, NULL);
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258 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
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259 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
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260 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision
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261 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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262 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size
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263 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer
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264 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type
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265 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer
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266 | 502a5395 | pbrook | #endif
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267 | f3902383 | blueswir1 | register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d); |
268 | f3902383 | blueswir1 | qemu_register_reset(pci_unin_reset, d); |
269 | f3902383 | blueswir1 | pci_unin_reset(d); |
270 | f3902383 | blueswir1 | |
271 | 502a5395 | pbrook | return s->bus;
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272 | 502a5395 | pbrook | } |