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/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "qemu-common.h" |
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#include "flash.h" |
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#include "irq.h" |
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#include "sysemu.h" |
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#include "block.h" |
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11 |
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6) |
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struct onenand_s {
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uint32_t id; |
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int shift;
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target_phys_addr_t base; |
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qemu_irq intr; |
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qemu_irq rdy; |
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BlockDriverState *bdrv; |
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BlockDriverState *bdrv_cur; |
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uint8_t *image; |
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uint8_t *otp; |
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uint8_t *current; |
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ram_addr_t ram; |
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uint8_t *boot[2];
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uint8_t *data[2][2]; |
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int iomemtype;
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command; |
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uint16_t config[2];
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uint16_t status; |
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uint16_t intstatus; |
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uint16_t wpstatus; |
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struct ecc_state_s ecc;
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp; |
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}; |
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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}; |
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enum {
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ONEN_ERR_CMD = 1 << 10, |
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ONEN_ERR_ERASE = 1 << 11, |
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ONEN_ERR_PROG = 1 << 12, |
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ONEN_ERR_LOAD = 1 << 13, |
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}; |
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enum {
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ONEN_INT_RESET = 1 << 4, |
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ONEN_INT_ERASE = 1 << 5, |
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ONEN_INT_PROG = 1 << 6, |
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ONEN_INT_LOAD = 1 << 7, |
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ONEN_INT = 1 << 15, |
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}; |
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
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ONEN_LOCK_LOCKED = 1 << 1, |
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ONEN_LOCK_UNLOCKED = 1 << 2, |
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}; |
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void onenand_base_update(void *opaque, target_phys_addr_t new) |
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{ |
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struct onenand_s *s = (struct onenand_s *) opaque; |
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s->base = new; |
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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0x0200 << s->shift, s->iomemtype);
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cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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0xbe00 << s->shift,
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(s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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if (s->iomemtype)
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cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
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0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift)); |
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} |
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void onenand_base_unmap(void *opaque) |
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{ |
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struct onenand_s *s = (struct onenand_s *) opaque; |
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cpu_register_physical_memory(s->base, |
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0x10000 << s->shift, IO_MEM_UNASSIGNED);
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} |
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static void onenand_intr_update(struct onenand_s *s) |
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{ |
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
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} |
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(struct onenand_s *s, int cold) |
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{ |
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memset(&s->addr, 0, sizeof(s->addr)); |
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0; |
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s->config[1] = 0x0000; |
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onenand_intr_update(s); |
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qemu_irq_raise(s->rdy); |
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010; |
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s->unladdr[0] = 0; |
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s->unladdr[1] = 0; |
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv; |
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s->current = s->image; |
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s->secs_cur = s->secs; |
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
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cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
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__FUNCTION__); |
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} |
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} |
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static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{ |
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(dest, s->current + (sec << 9), secn << 9); |
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return 0; |
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} |
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static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, |
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void *src)
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{ |
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if (s->bdrv_cur)
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return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (sec << 9), src, secn << 9); |
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return 0; |
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} |
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static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
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return 0; |
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} |
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static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, |
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void *src)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
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return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
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return 0; |
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} |
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static inline int onenand_erase(struct onenand_s *s, int sec, int num) |
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{ |
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/* TODO: optimise */
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uint8_t buf[512];
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memset(buf, 0xff, sizeof(buf)); |
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for (; num > 0; num --, sec ++) { |
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if (onenand_prog_main(s, sec, 1, buf)) |
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return 1; |
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if (onenand_prog_spare(s, sec, 1, buf)) |
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return 1; |
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} |
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return 0; |
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} |
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static void onenand_command(struct onenand_s *s, int cmd) |
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{ |
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \ |
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
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buf += (s->bufaddr & 3) << 9; |
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
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buf += (s->bufaddr & 3) << 4; |
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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#if 0
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
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#if 0
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
317 |
if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
319 |
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x1b: /* Copy-back program */ |
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SETBUF_S() |
328 |
|
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
330 |
if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
332 |
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SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
334 |
if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
336 |
|
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/* TODO: spare areas */
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|
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
340 |
break;
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|
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case 0x23: /* Unlock NAND array block(s) */ |
343 |
s->intstatus |= ONEN_INT; |
344 |
|
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/* XXX the previous (?) area should be locked automatically */
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
347 |
if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD; |
349 |
break;
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} |
351 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
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|
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
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} |
356 |
break;
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357 |
case 0x27: /* Unlock All NAND array blocks */ |
358 |
s->intstatus |= ONEN_INT; |
359 |
|
360 |
for (b = 0; b < s->blocks; b ++) { |
361 |
if (b >= s->blocks) {
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362 |
s->status |= ONEN_ERR_CMD; |
363 |
break;
|
364 |
} |
365 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
366 |
break;
|
367 |
|
368 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
369 |
} |
370 |
break;
|
371 |
|
372 |
case 0x2a: /* Lock NAND array block(s) */ |
373 |
s->intstatus |= ONEN_INT; |
374 |
|
375 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
376 |
if (b >= s->blocks) {
|
377 |
s->status |= ONEN_ERR_CMD; |
378 |
break;
|
379 |
} |
380 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
381 |
break;
|
382 |
|
383 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
384 |
} |
385 |
break;
|
386 |
case 0x2c: /* Lock-tight NAND array block(s) */ |
387 |
s->intstatus |= ONEN_INT; |
388 |
|
389 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
390 |
if (b >= s->blocks) {
|
391 |
s->status |= ONEN_ERR_CMD; |
392 |
break;
|
393 |
} |
394 |
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
395 |
continue;
|
396 |
|
397 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
398 |
} |
399 |
break;
|
400 |
|
401 |
case 0x71: /* Erase-Verify-Read */ |
402 |
s->intstatus |= ONEN_INT; |
403 |
break;
|
404 |
case 0x95: /* Multi-block erase */ |
405 |
qemu_irq_pulse(s->intr); |
406 |
/* Fall through. */
|
407 |
case 0x94: /* Block erase */ |
408 |
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
409 |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
410 |
<< (BLOCK_SHIFT - 9);
|
411 |
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
412 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
413 |
|
414 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
415 |
break;
|
416 |
case 0xb0: /* Erase suspend */ |
417 |
break;
|
418 |
case 0x30: /* Erase resume */ |
419 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
420 |
break;
|
421 |
|
422 |
case 0xf0: /* Reset NAND Flash core */ |
423 |
onenand_reset(s, 0);
|
424 |
break;
|
425 |
case 0xf3: /* Reset OneNAND */ |
426 |
onenand_reset(s, 0);
|
427 |
break;
|
428 |
|
429 |
case 0x65: /* OTP Access */ |
430 |
s->intstatus |= ONEN_INT; |
431 |
s->bdrv_cur = 0;
|
432 |
s->current = s->otp; |
433 |
s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
434 |
s->addr[ONEN_BUF_BLOCK] = 0;
|
435 |
s->otpmode = 1;
|
436 |
break;
|
437 |
|
438 |
default:
|
439 |
s->status |= ONEN_ERR_CMD; |
440 |
s->intstatus |= ONEN_INT; |
441 |
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
442 |
__FUNCTION__, cmd); |
443 |
} |
444 |
|
445 |
onenand_intr_update(s); |
446 |
} |
447 |
|
448 |
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
449 |
{ |
450 |
struct onenand_s *s = (struct onenand_s *) opaque; |
451 |
int offset = addr >> s->shift;
|
452 |
|
453 |
switch (offset) {
|
454 |
case 0x0000 ... 0xc000: |
455 |
return lduw_le_p(s->boot[0] + addr); |
456 |
|
457 |
case 0xf000: /* Manufacturer ID */ |
458 |
return (s->id >> 16) & 0xff; |
459 |
case 0xf001: /* Device ID */ |
460 |
return (s->id >> 8) & 0xff; |
461 |
/* TODO: get the following values from a real chip! */
|
462 |
case 0xf002: /* Version ID */ |
463 |
return (s->id >> 0) & 0xff; |
464 |
case 0xf003: /* Data Buffer size */ |
465 |
return 1 << PAGE_SHIFT; |
466 |
case 0xf004: /* Boot Buffer size */ |
467 |
return 0x200; |
468 |
case 0xf005: /* Amount of buffers */ |
469 |
return 1 | (2 << 8); |
470 |
case 0xf006: /* Technology */ |
471 |
return 0; |
472 |
|
473 |
case 0xf100 ... 0xf107: /* Start addresses */ |
474 |
return s->addr[offset - 0xf100]; |
475 |
|
476 |
case 0xf200: /* Start buffer */ |
477 |
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
478 |
|
479 |
case 0xf220: /* Command */ |
480 |
return s->command;
|
481 |
case 0xf221: /* System Configuration 1 */ |
482 |
return s->config[0] & 0xffe0; |
483 |
case 0xf222: /* System Configuration 2 */ |
484 |
return s->config[1]; |
485 |
|
486 |
case 0xf240: /* Controller Status */ |
487 |
return s->status;
|
488 |
case 0xf241: /* Interrupt */ |
489 |
return s->intstatus;
|
490 |
case 0xf24c: /* Unlock Start Block Address */ |
491 |
return s->unladdr[0]; |
492 |
case 0xf24d: /* Unlock End Block Address */ |
493 |
return s->unladdr[1]; |
494 |
case 0xf24e: /* Write Protection Status */ |
495 |
return s->wpstatus;
|
496 |
|
497 |
case 0xff00: /* ECC Status */ |
498 |
return 0x00; |
499 |
case 0xff01: /* ECC Result of main area data */ |
500 |
case 0xff02: /* ECC Result of spare area data */ |
501 |
case 0xff03: /* ECC Result of main area data */ |
502 |
case 0xff04: /* ECC Result of spare area data */ |
503 |
cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
|
504 |
return 0x0000; |
505 |
} |
506 |
|
507 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
508 |
__FUNCTION__, offset); |
509 |
return 0; |
510 |
} |
511 |
|
512 |
static void onenand_write(void *opaque, target_phys_addr_t addr, |
513 |
uint32_t value) |
514 |
{ |
515 |
struct onenand_s *s = (struct onenand_s *) opaque; |
516 |
int offset = addr >> s->shift;
|
517 |
int sec;
|
518 |
|
519 |
switch (offset) {
|
520 |
case 0x0000 ... 0x01ff: |
521 |
case 0x8000 ... 0x800f: |
522 |
if (s->cycle) {
|
523 |
s->cycle = 0;
|
524 |
|
525 |
if (value == 0x0000) { |
526 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
527 |
onenand_load_main(s, sec, |
528 |
1 << (PAGE_SHIFT - 9), s->data[0][0]); |
529 |
s->addr[ONEN_BUF_PAGE] += 4;
|
530 |
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
531 |
} |
532 |
break;
|
533 |
} |
534 |
|
535 |
switch (value) {
|
536 |
case 0x00f0: /* Reset OneNAND */ |
537 |
onenand_reset(s, 0);
|
538 |
break;
|
539 |
|
540 |
case 0x00e0: /* Load Data into Buffer */ |
541 |
s->cycle = 1;
|
542 |
break;
|
543 |
|
544 |
case 0x0090: /* Read Identification Data */ |
545 |
memset(s->boot[0], 0, 3 << s->shift); |
546 |
s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
547 |
s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
548 |
s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
549 |
break;
|
550 |
|
551 |
default:
|
552 |
fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
553 |
__FUNCTION__, value); |
554 |
} |
555 |
break;
|
556 |
|
557 |
case 0xf100 ... 0xf107: /* Start addresses */ |
558 |
s->addr[offset - 0xf100] = value;
|
559 |
break;
|
560 |
|
561 |
case 0xf200: /* Start buffer */ |
562 |
s->bufaddr = (value >> 8) & 0xf; |
563 |
if (PAGE_SHIFT == 11) |
564 |
s->count = (value & 3) ?: 4; |
565 |
else if (PAGE_SHIFT == 10) |
566 |
s->count = (value & 1) ?: 2; |
567 |
break;
|
568 |
|
569 |
case 0xf220: /* Command */ |
570 |
if (s->intstatus & (1 << 15)) |
571 |
break;
|
572 |
s->command = value; |
573 |
onenand_command(s, s->command); |
574 |
break;
|
575 |
case 0xf221: /* System Configuration 1 */ |
576 |
s->config[0] = value;
|
577 |
onenand_intr_update(s); |
578 |
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
579 |
break;
|
580 |
case 0xf222: /* System Configuration 2 */ |
581 |
s->config[1] = value;
|
582 |
break;
|
583 |
|
584 |
case 0xf241: /* Interrupt */ |
585 |
s->intstatus &= value; |
586 |
if ((1 << 15) & ~s->intstatus) |
587 |
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
588 |
ONEN_ERR_PROG | ONEN_ERR_LOAD); |
589 |
onenand_intr_update(s); |
590 |
break;
|
591 |
case 0xf24c: /* Unlock Start Block Address */ |
592 |
s->unladdr[0] = value & (s->blocks - 1); |
593 |
/* For some reason we have to set the end address to by default
|
594 |
* be same as start because the software forgets to write anything
|
595 |
* in there. */
|
596 |
s->unladdr[1] = value & (s->blocks - 1); |
597 |
break;
|
598 |
case 0xf24d: /* Unlock End Block Address */ |
599 |
s->unladdr[1] = value & (s->blocks - 1); |
600 |
break;
|
601 |
|
602 |
default:
|
603 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
604 |
__FUNCTION__, offset); |
605 |
} |
606 |
} |
607 |
|
608 |
static CPUReadMemoryFunc *onenand_readfn[] = {
|
609 |
onenand_read, /* TODO */
|
610 |
onenand_read, |
611 |
onenand_read, |
612 |
}; |
613 |
|
614 |
static CPUWriteMemoryFunc *onenand_writefn[] = {
|
615 |
onenand_write, /* TODO */
|
616 |
onenand_write, |
617 |
onenand_write, |
618 |
}; |
619 |
|
620 |
void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
621 |
{ |
622 |
struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s)); |
623 |
int bdrv_index = drive_get_index(IF_MTD, 0, 0); |
624 |
uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
625 |
void *ram;
|
626 |
|
627 |
s->shift = regshift; |
628 |
s->intr = irq; |
629 |
s->rdy = 0;
|
630 |
s->id = id; |
631 |
s->blocks = size >> BLOCK_SHIFT; |
632 |
s->secs = size >> 9;
|
633 |
s->blockwp = qemu_malloc(s->blocks); |
634 |
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
635 |
s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
|
636 |
onenand_writefn, s); |
637 |
if (bdrv_index == -1) |
638 |
s->image = memset(qemu_malloc(size + (size >> 5)),
|
639 |
0xff, size + (size >> 5)); |
640 |
else
|
641 |
s->bdrv = drives_table[bdrv_index].bdrv; |
642 |
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
643 |
0xff, (64 + 2) << PAGE_SHIFT); |
644 |
s->ram = qemu_ram_alloc(0xc000 << s->shift);
|
645 |
ram = qemu_get_ram_ptr(s->ram); |
646 |
s->boot[0] = ram + (0x0000 << s->shift); |
647 |
s->boot[1] = ram + (0x8000 << s->shift); |
648 |
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
649 |
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
650 |
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
651 |
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
652 |
|
653 |
onenand_reset(s, 1);
|
654 |
|
655 |
return s;
|
656 |
} |
657 |
|
658 |
void *onenand_raw_otp(void *opaque) |
659 |
{ |
660 |
struct onenand_s *s = (struct onenand_s *) opaque; |
661 |
|
662 |
return s->otp;
|
663 |
} |