root / hw / pc.h @ 48a18b3c
History | View | Annotate | Download (7.4 kB)
1 |
#ifndef HW_PC_H
|
---|---|
2 |
#define HW_PC_H
|
3 |
|
4 |
#include "qemu-common.h" |
5 |
#include "memory.h" |
6 |
#include "ioport.h" |
7 |
#include "isa.h" |
8 |
#include "fdc.h" |
9 |
#include "net.h" |
10 |
#include "memory.h" |
11 |
#include "ioapic.h" |
12 |
|
13 |
/* PC-style peripherals (also used by other machines). */
|
14 |
|
15 |
/* serial.c */
|
16 |
|
17 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
18 |
CharDriverState *chr); |
19 |
SerialState *serial_mm_init(MemoryRegion *address_space, |
20 |
target_phys_addr_t base, int it_shift,
|
21 |
qemu_irq irq, int baudbase,
|
22 |
CharDriverState *chr, enum device_endian);
|
23 |
static inline bool serial_isa_init(ISABus *bus, int index, |
24 |
CharDriverState *chr) |
25 |
{ |
26 |
ISADevice *dev; |
27 |
|
28 |
dev = isa_try_create(bus, "isa-serial");
|
29 |
if (!dev) {
|
30 |
return false; |
31 |
} |
32 |
qdev_prop_set_uint32(&dev->qdev, "index", index);
|
33 |
qdev_prop_set_chr(&dev->qdev, "chardev", chr);
|
34 |
if (qdev_init(&dev->qdev) < 0) { |
35 |
return false; |
36 |
} |
37 |
return true; |
38 |
} |
39 |
|
40 |
void serial_set_frequency(SerialState *s, uint32_t frequency);
|
41 |
|
42 |
/* parallel.c */
|
43 |
static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) |
44 |
{ |
45 |
ISADevice *dev; |
46 |
|
47 |
dev = isa_try_create(bus, "isa-parallel");
|
48 |
if (!dev) {
|
49 |
return false; |
50 |
} |
51 |
qdev_prop_set_uint32(&dev->qdev, "index", index);
|
52 |
qdev_prop_set_chr(&dev->qdev, "chardev", chr);
|
53 |
if (qdev_init(&dev->qdev) < 0) { |
54 |
return false; |
55 |
} |
56 |
return true; |
57 |
} |
58 |
|
59 |
bool parallel_mm_init(MemoryRegion *address_space,
|
60 |
target_phys_addr_t base, int it_shift, qemu_irq irq,
|
61 |
CharDriverState *chr); |
62 |
|
63 |
/* i8259.c */
|
64 |
|
65 |
typedef struct PicState PicState; |
66 |
extern PicState *isa_pic;
|
67 |
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); |
68 |
int pic_read_irq(PicState *s);
|
69 |
int pic_get_output(PicState *s);
|
70 |
void pic_info(Monitor *mon);
|
71 |
void irq_info(Monitor *mon);
|
72 |
|
73 |
/* Global System Interrupts */
|
74 |
|
75 |
#define GSI_NUM_PINS IOAPIC_NUM_PINS
|
76 |
|
77 |
typedef struct GSIState { |
78 |
qemu_irq i8259_irq[ISA_NUM_IRQS]; |
79 |
qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; |
80 |
} GSIState; |
81 |
|
82 |
void gsi_handler(void *opaque, int n, int level); |
83 |
|
84 |
/* i8254.c */
|
85 |
|
86 |
#define PIT_FREQ 1193182 |
87 |
|
88 |
static inline ISADevice *pit_init(ISABus *bus, int base, int irq) |
89 |
{ |
90 |
ISADevice *dev; |
91 |
|
92 |
dev = isa_create(bus, "isa-pit");
|
93 |
qdev_prop_set_uint32(&dev->qdev, "iobase", base);
|
94 |
qdev_prop_set_uint32(&dev->qdev, "irq", irq);
|
95 |
qdev_init_nofail(&dev->qdev); |
96 |
|
97 |
return dev;
|
98 |
} |
99 |
|
100 |
void pit_set_gate(ISADevice *dev, int channel, int val); |
101 |
int pit_get_gate(ISADevice *dev, int channel); |
102 |
int pit_get_initial_count(ISADevice *dev, int channel); |
103 |
int pit_get_mode(ISADevice *dev, int channel); |
104 |
int pit_get_out(ISADevice *dev, int channel, int64_t current_time); |
105 |
|
106 |
void hpet_pit_disable(void); |
107 |
void hpet_pit_enable(void); |
108 |
|
109 |
/* vmport.c */
|
110 |
static inline void vmport_init(ISABus *bus) |
111 |
{ |
112 |
isa_create_simple(bus, "vmport");
|
113 |
} |
114 |
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); |
115 |
void vmmouse_get_data(uint32_t *data);
|
116 |
void vmmouse_set_data(const uint32_t *data); |
117 |
|
118 |
/* pckbd.c */
|
119 |
|
120 |
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
|
121 |
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
|
122 |
MemoryRegion *region, ram_addr_t size, |
123 |
target_phys_addr_t mask); |
124 |
void i8042_isa_mouse_fake_event(void *opaque); |
125 |
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
|
126 |
|
127 |
/* pc.c */
|
128 |
extern int fd_bootchk; |
129 |
|
130 |
void pc_register_ferr_irq(qemu_irq irq);
|
131 |
void pc_cmos_set_s3_resume(void *opaque, int irq, int level); |
132 |
void pc_acpi_smi_interrupt(void *opaque, int irq, int level); |
133 |
|
134 |
void pc_cpus_init(const char *cpu_model); |
135 |
void pc_memory_init(MemoryRegion *system_memory,
|
136 |
const char *kernel_filename, |
137 |
const char *kernel_cmdline, |
138 |
const char *initrd_filename, |
139 |
ram_addr_t below_4g_mem_size, |
140 |
ram_addr_t above_4g_mem_size, |
141 |
MemoryRegion *rom_memory, |
142 |
MemoryRegion **ram_memory); |
143 |
qemu_irq *pc_allocate_cpu_irq(void);
|
144 |
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); |
145 |
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
|
146 |
ISADevice **rtc_state, |
147 |
ISADevice **floppy, |
148 |
bool no_vmport);
|
149 |
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
|
150 |
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
|
151 |
const char *boot_device, |
152 |
ISADevice *floppy, BusState *ide0, BusState *ide1, |
153 |
ISADevice *s); |
154 |
void pc_pci_device_init(PCIBus *pci_bus);
|
155 |
|
156 |
typedef void (*cpu_set_smm_t)(int smm, void *arg); |
157 |
void cpu_smm_register(cpu_set_smm_t callback, void *arg); |
158 |
|
159 |
/* acpi.c */
|
160 |
extern int acpi_enabled; |
161 |
extern char *acpi_tables; |
162 |
extern size_t acpi_tables_len;
|
163 |
|
164 |
void acpi_bios_init(void); |
165 |
int acpi_table_add(const char *table_desc); |
166 |
|
167 |
/* acpi_piix.c */
|
168 |
|
169 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
170 |
qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, |
171 |
int kvm_enabled);
|
172 |
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
173 |
|
174 |
/* hpet.c */
|
175 |
extern int no_hpet; |
176 |
|
177 |
/* pcspk.c */
|
178 |
void pcspk_init(ISADevice *pit);
|
179 |
int pcspk_audio_init(ISABus *bus, qemu_irq *pic);
|
180 |
|
181 |
/* piix_pci.c */
|
182 |
struct PCII440FXState;
|
183 |
typedef struct PCII440FXState PCII440FXState; |
184 |
|
185 |
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
|
186 |
qemu_irq *pic, |
187 |
MemoryRegion *address_space_mem, |
188 |
MemoryRegion *address_space_io, |
189 |
ram_addr_t ram_size, |
190 |
target_phys_addr_t pci_hole_start, |
191 |
target_phys_addr_t pci_hole_size, |
192 |
target_phys_addr_t pci_hole64_start, |
193 |
target_phys_addr_t pci_hole64_size, |
194 |
MemoryRegion *pci_memory, |
195 |
MemoryRegion *ram_memory); |
196 |
|
197 |
/* piix4.c */
|
198 |
extern PCIDevice *piix4_dev;
|
199 |
int piix4_init(PCIBus *bus, int devfn); |
200 |
|
201 |
/* vga.c */
|
202 |
enum vga_retrace_method {
|
203 |
VGA_RETRACE_DUMB, |
204 |
VGA_RETRACE_PRECISE |
205 |
}; |
206 |
|
207 |
extern enum vga_retrace_method vga_retrace_method; |
208 |
|
209 |
static inline DeviceState *isa_vga_init(ISABus *bus) |
210 |
{ |
211 |
ISADevice *dev; |
212 |
|
213 |
dev = isa_try_create(bus, "isa-vga");
|
214 |
if (!dev) {
|
215 |
fprintf(stderr, "Warning: isa-vga not available\n");
|
216 |
return NULL; |
217 |
} |
218 |
qdev_init_nofail(&dev->qdev); |
219 |
return &dev->qdev;
|
220 |
} |
221 |
|
222 |
DeviceState *pci_vga_init(PCIBus *bus); |
223 |
int isa_vga_mm_init(target_phys_addr_t vram_base,
|
224 |
target_phys_addr_t ctrl_base, int it_shift,
|
225 |
MemoryRegion *address_space); |
226 |
|
227 |
/* cirrus_vga.c */
|
228 |
DeviceState *pci_cirrus_vga_init(PCIBus *bus); |
229 |
DeviceState *isa_cirrus_vga_init(MemoryRegion *address_space); |
230 |
|
231 |
/* ne2000.c */
|
232 |
static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) |
233 |
{ |
234 |
ISADevice *dev; |
235 |
|
236 |
qemu_check_nic_model(nd, "ne2k_isa");
|
237 |
|
238 |
dev = isa_try_create(bus, "ne2k_isa");
|
239 |
if (!dev) {
|
240 |
return false; |
241 |
} |
242 |
qdev_prop_set_uint32(&dev->qdev, "iobase", base);
|
243 |
qdev_prop_set_uint32(&dev->qdev, "irq", irq);
|
244 |
qdev_set_nic_properties(&dev->qdev, nd); |
245 |
qdev_init_nofail(&dev->qdev); |
246 |
return true; |
247 |
} |
248 |
|
249 |
/* e820 types */
|
250 |
#define E820_RAM 1 |
251 |
#define E820_RESERVED 2 |
252 |
#define E820_ACPI 3 |
253 |
#define E820_NVS 4 |
254 |
#define E820_UNUSABLE 5 |
255 |
|
256 |
int e820_add_entry(uint64_t, uint64_t, uint32_t);
|
257 |
|
258 |
#endif
|