root / hw / intc / arm_gic.c @ 4917cf44
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/*
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* ARM Generic/Distributed Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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|
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/* This file contains implementation code for the RealView EB interrupt
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* controller, MPCore distributed interrupt controller and ARMv7-M
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* Nested Vectored Interrupt Controller.
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* It is compiled in two ways:
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* (1) as a standalone file to produce a sysbus device which is a GIC
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* that can be used on the realview board and as one of the builtin
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* private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
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* (2) by being directly #included into armv7m_nvic.c to produce the
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* armv7m_nvic device.
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*/
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#include "hw/sysbus.h" |
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#include "gic_internal.h" |
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//#define DEBUG_GIC
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|
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#ifdef DEBUG_GIC
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while(0) |
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#endif
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static const uint8_t gic_id[] = { |
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0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 |
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}; |
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#define NUM_CPU(s) ((s)->num_cpu)
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static inline int gic_get_current_cpu(GICState *s) |
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{ |
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if (s->num_cpu > 1) { |
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return current_cpu->cpu_index;
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} |
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return 0; |
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} |
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|
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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void gic_update(GICState *s)
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{ |
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int best_irq;
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int best_prio;
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int irq;
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int level;
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int cpu;
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int cm;
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|
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for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
|
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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qemu_irq_lower(s->parent_irq[cpu]); |
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return;
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} |
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best_prio = 0x100;
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best_irq = 1023;
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for (irq = 0; irq < s->num_irq; irq++) { |
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if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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best_prio = GIC_GET_PRIORITY(irq, cpu); |
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best_irq = irq; |
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} |
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} |
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} |
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level = 0;
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if (best_prio < s->priority_mask[cpu]) {
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s->current_pending[cpu] = best_irq; |
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if (best_prio < s->running_priority[cpu]) {
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DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);
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level = 1;
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} |
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} |
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qemu_set_irq(s->parent_irq[cpu], level); |
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} |
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} |
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|
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void gic_set_pending_private(GICState *s, int cpu, int irq) |
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{ |
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int cm = 1 << cpu; |
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|
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if (GIC_TEST_PENDING(irq, cm))
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return;
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|
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DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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GIC_SET_PENDING(irq, cm); |
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gic_update(s); |
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} |
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|
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/* Process a change in an external IRQ input. */
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static void gic_set_irq(void *opaque, int irq, int level) |
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{ |
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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GICState *s = (GICState *)opaque; |
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int cm, target;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* The first external input line is internal interrupt 32. */
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cm = ALL_CPU_MASK; |
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irq += GIC_INTERNAL; |
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target = GIC_TARGET(irq); |
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} else {
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int cpu;
|
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irq -= (s->num_irq - GIC_INTERNAL); |
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cpu = irq / GIC_INTERNAL; |
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irq %= GIC_INTERNAL; |
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cm = 1 << cpu;
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target = cm; |
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} |
123 |
|
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if (level == GIC_TEST_LEVEL(irq, cm)) {
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return;
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} |
127 |
|
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if (level) {
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GIC_SET_LEVEL(irq, cm); |
130 |
if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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DPRINTF("Set %d pending mask %x\n", irq, target);
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GIC_SET_PENDING(irq, target); |
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} |
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} else {
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GIC_CLEAR_LEVEL(irq, cm); |
136 |
} |
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gic_update(s); |
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} |
139 |
|
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static void gic_set_running_irq(GICState *s, int cpu, int irq) |
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{ |
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s->running_irq[cpu] = irq; |
143 |
if (irq == 1023) { |
144 |
s->running_priority[cpu] = 0x100;
|
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} else {
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s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
147 |
} |
148 |
gic_update(s); |
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} |
150 |
|
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uint32_t gic_acknowledge_irq(GICState *s, int cpu)
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{ |
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int new_irq;
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int cm = 1 << cpu; |
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new_irq = s->current_pending[cpu]; |
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if (new_irq == 1023 |
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|| GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
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DPRINTF("ACK no pending IRQ\n");
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return 1023; |
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} |
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s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
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/* Clear pending flags for both level and edge triggered interrupts.
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Level triggered IRQs will be reasserted once they become inactive. */
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GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
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gic_set_running_irq(s, cpu, new_irq); |
166 |
DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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} |
169 |
|
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void gic_complete_irq(GICState *s, int cpu, int irq) |
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{ |
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int update = 0; |
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int cm = 1 << cpu; |
174 |
DPRINTF("EOI %d\n", irq);
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if (irq >= s->num_irq) {
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/* This handles two cases:
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* 1. If software writes the ID of a spurious interrupt [ie 1023]
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* to the GICC_EOIR, the GIC ignores that write.
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* 2. If software writes the number of a non-existent interrupt
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* this must be a subcase of "value written does not match the last
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* valid interrupt value read from the Interrupt Acknowledge
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* register" and so this is UNPREDICTABLE. We choose to ignore it.
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*/
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return;
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} |
186 |
if (s->running_irq[cpu] == 1023) |
187 |
return; /* No active IRQ. */ |
188 |
/* Mark level triggered interrupts as pending if they are still
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raised. */
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm); |
194 |
update = 1;
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} |
196 |
if (irq != s->running_irq[cpu]) {
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/* Complete an IRQ that is not currently running. */
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int tmp = s->running_irq[cpu];
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while (s->last_active[tmp][cpu] != 1023) { |
200 |
if (s->last_active[tmp][cpu] == irq) {
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s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
202 |
break;
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203 |
} |
204 |
tmp = s->last_active[tmp][cpu]; |
205 |
} |
206 |
if (update) {
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gic_update(s); |
208 |
} |
209 |
} else {
|
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/* Complete the current running IRQ. */
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gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
212 |
} |
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} |
214 |
|
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static uint32_t gic_dist_readb(void *opaque, hwaddr offset) |
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{ |
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GICState *s = (GICState *)opaque; |
218 |
uint32_t res; |
219 |
int irq;
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int i;
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int cpu;
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int cm;
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int mask;
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224 |
|
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cpu = gic_get_current_cpu(s); |
226 |
cm = 1 << cpu;
|
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if (offset < 0x100) { |
228 |
if (offset == 0) |
229 |
return s->enabled;
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if (offset == 4) |
231 |
return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
232 |
if (offset < 0x08) |
233 |
return 0; |
234 |
if (offset >= 0x80) { |
235 |
/* Interrupt Security , RAZ/WI */
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return 0; |
237 |
} |
238 |
goto bad_reg;
|
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} else if (offset < 0x200) { |
240 |
/* Interrupt Set/Clear Enable. */
|
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if (offset < 0x180) |
242 |
irq = (offset - 0x100) * 8; |
243 |
else
|
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irq = (offset - 0x180) * 8; |
245 |
irq += GIC_BASE_IRQ; |
246 |
if (irq >= s->num_irq)
|
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goto bad_reg;
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248 |
res = 0;
|
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for (i = 0; i < 8; i++) { |
250 |
if (GIC_TEST_ENABLED(irq + i, cm)) {
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res |= (1 << i);
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} |
253 |
} |
254 |
} else if (offset < 0x300) { |
255 |
/* Interrupt Set/Clear Pending. */
|
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if (offset < 0x280) |
257 |
irq = (offset - 0x200) * 8; |
258 |
else
|
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irq = (offset - 0x280) * 8; |
260 |
irq += GIC_BASE_IRQ; |
261 |
if (irq >= s->num_irq)
|
262 |
goto bad_reg;
|
263 |
res = 0;
|
264 |
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
265 |
for (i = 0; i < 8; i++) { |
266 |
if (GIC_TEST_PENDING(irq + i, mask)) {
|
267 |
res |= (1 << i);
|
268 |
} |
269 |
} |
270 |
} else if (offset < 0x400) { |
271 |
/* Interrupt Active. */
|
272 |
irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
273 |
if (irq >= s->num_irq)
|
274 |
goto bad_reg;
|
275 |
res = 0;
|
276 |
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
277 |
for (i = 0; i < 8; i++) { |
278 |
if (GIC_TEST_ACTIVE(irq + i, mask)) {
|
279 |
res |= (1 << i);
|
280 |
} |
281 |
} |
282 |
} else if (offset < 0x800) { |
283 |
/* Interrupt Priority. */
|
284 |
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
285 |
if (irq >= s->num_irq)
|
286 |
goto bad_reg;
|
287 |
res = GIC_GET_PRIORITY(irq, cpu); |
288 |
} else if (offset < 0xc00) { |
289 |
/* Interrupt CPU Target. */
|
290 |
if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { |
291 |
/* For uniprocessor GICs these RAZ/WI */
|
292 |
res = 0;
|
293 |
} else {
|
294 |
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
295 |
if (irq >= s->num_irq) {
|
296 |
goto bad_reg;
|
297 |
} |
298 |
if (irq >= 29 && irq <= 31) { |
299 |
res = cm; |
300 |
} else {
|
301 |
res = GIC_TARGET(irq); |
302 |
} |
303 |
} |
304 |
} else if (offset < 0xf00) { |
305 |
/* Interrupt Configuration. */
|
306 |
irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
307 |
if (irq >= s->num_irq)
|
308 |
goto bad_reg;
|
309 |
res = 0;
|
310 |
for (i = 0; i < 4; i++) { |
311 |
if (GIC_TEST_MODEL(irq + i))
|
312 |
res |= (1 << (i * 2)); |
313 |
if (GIC_TEST_TRIGGER(irq + i))
|
314 |
res |= (2 << (i * 2)); |
315 |
} |
316 |
} else if (offset < 0xfe0) { |
317 |
goto bad_reg;
|
318 |
} else /* offset >= 0xfe0 */ { |
319 |
if (offset & 3) { |
320 |
res = 0;
|
321 |
} else {
|
322 |
res = gic_id[(offset - 0xfe0) >> 2]; |
323 |
} |
324 |
} |
325 |
return res;
|
326 |
bad_reg:
|
327 |
qemu_log_mask(LOG_GUEST_ERROR, |
328 |
"gic_dist_readb: Bad offset %x\n", (int)offset); |
329 |
return 0; |
330 |
} |
331 |
|
332 |
static uint32_t gic_dist_readw(void *opaque, hwaddr offset) |
333 |
{ |
334 |
uint32_t val; |
335 |
val = gic_dist_readb(opaque, offset); |
336 |
val |= gic_dist_readb(opaque, offset + 1) << 8; |
337 |
return val;
|
338 |
} |
339 |
|
340 |
static uint32_t gic_dist_readl(void *opaque, hwaddr offset) |
341 |
{ |
342 |
uint32_t val; |
343 |
val = gic_dist_readw(opaque, offset); |
344 |
val |= gic_dist_readw(opaque, offset + 2) << 16; |
345 |
return val;
|
346 |
} |
347 |
|
348 |
static void gic_dist_writeb(void *opaque, hwaddr offset, |
349 |
uint32_t value) |
350 |
{ |
351 |
GICState *s = (GICState *)opaque; |
352 |
int irq;
|
353 |
int i;
|
354 |
int cpu;
|
355 |
|
356 |
cpu = gic_get_current_cpu(s); |
357 |
if (offset < 0x100) { |
358 |
if (offset == 0) { |
359 |
s->enabled = (value & 1);
|
360 |
DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
361 |
} else if (offset < 4) { |
362 |
/* ignored. */
|
363 |
} else if (offset >= 0x80) { |
364 |
/* Interrupt Security Registers, RAZ/WI */
|
365 |
} else {
|
366 |
goto bad_reg;
|
367 |
} |
368 |
} else if (offset < 0x180) { |
369 |
/* Interrupt Set Enable. */
|
370 |
irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
371 |
if (irq >= s->num_irq)
|
372 |
goto bad_reg;
|
373 |
if (irq < 16) |
374 |
value = 0xff;
|
375 |
for (i = 0; i < 8; i++) { |
376 |
if (value & (1 << i)) { |
377 |
int mask =
|
378 |
(irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
|
379 |
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
380 |
|
381 |
if (!GIC_TEST_ENABLED(irq + i, cm)) {
|
382 |
DPRINTF("Enabled IRQ %d\n", irq + i);
|
383 |
} |
384 |
GIC_SET_ENABLED(irq + i, cm); |
385 |
/* If a raised level triggered IRQ enabled then mark
|
386 |
is as pending. */
|
387 |
if (GIC_TEST_LEVEL(irq + i, mask)
|
388 |
&& !GIC_TEST_TRIGGER(irq + i)) { |
389 |
DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
390 |
GIC_SET_PENDING(irq + i, mask); |
391 |
} |
392 |
} |
393 |
} |
394 |
} else if (offset < 0x200) { |
395 |
/* Interrupt Clear Enable. */
|
396 |
irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
397 |
if (irq >= s->num_irq)
|
398 |
goto bad_reg;
|
399 |
if (irq < 16) |
400 |
value = 0;
|
401 |
for (i = 0; i < 8; i++) { |
402 |
if (value & (1 << i)) { |
403 |
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
404 |
|
405 |
if (GIC_TEST_ENABLED(irq + i, cm)) {
|
406 |
DPRINTF("Disabled IRQ %d\n", irq + i);
|
407 |
} |
408 |
GIC_CLEAR_ENABLED(irq + i, cm); |
409 |
} |
410 |
} |
411 |
} else if (offset < 0x280) { |
412 |
/* Interrupt Set Pending. */
|
413 |
irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
414 |
if (irq >= s->num_irq)
|
415 |
goto bad_reg;
|
416 |
if (irq < 16) |
417 |
irq = 0;
|
418 |
|
419 |
for (i = 0; i < 8; i++) { |
420 |
if (value & (1 << i)) { |
421 |
GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); |
422 |
} |
423 |
} |
424 |
} else if (offset < 0x300) { |
425 |
/* Interrupt Clear Pending. */
|
426 |
irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
427 |
if (irq >= s->num_irq)
|
428 |
goto bad_reg;
|
429 |
for (i = 0; i < 8; i++) { |
430 |
/* ??? This currently clears the pending bit for all CPUs, even
|
431 |
for per-CPU interrupts. It's unclear whether this is the
|
432 |
corect behavior. */
|
433 |
if (value & (1 << i)) { |
434 |
GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
435 |
} |
436 |
} |
437 |
} else if (offset < 0x400) { |
438 |
/* Interrupt Active. */
|
439 |
goto bad_reg;
|
440 |
} else if (offset < 0x800) { |
441 |
/* Interrupt Priority. */
|
442 |
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
443 |
if (irq >= s->num_irq)
|
444 |
goto bad_reg;
|
445 |
if (irq < GIC_INTERNAL) {
|
446 |
s->priority1[irq][cpu] = value; |
447 |
} else {
|
448 |
s->priority2[irq - GIC_INTERNAL] = value; |
449 |
} |
450 |
} else if (offset < 0xc00) { |
451 |
/* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
|
452 |
* annoying exception of the 11MPCore's GIC.
|
453 |
*/
|
454 |
if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { |
455 |
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
456 |
if (irq >= s->num_irq) {
|
457 |
goto bad_reg;
|
458 |
} |
459 |
if (irq < 29) { |
460 |
value = 0;
|
461 |
} else if (irq < GIC_INTERNAL) { |
462 |
value = ALL_CPU_MASK; |
463 |
} |
464 |
s->irq_target[irq] = value & ALL_CPU_MASK; |
465 |
} |
466 |
} else if (offset < 0xf00) { |
467 |
/* Interrupt Configuration. */
|
468 |
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
469 |
if (irq >= s->num_irq)
|
470 |
goto bad_reg;
|
471 |
if (irq < GIC_INTERNAL)
|
472 |
value |= 0xaa;
|
473 |
for (i = 0; i < 4; i++) { |
474 |
if (value & (1 << (i * 2))) { |
475 |
GIC_SET_MODEL(irq + i); |
476 |
} else {
|
477 |
GIC_CLEAR_MODEL(irq + i); |
478 |
} |
479 |
if (value & (2 << (i * 2))) { |
480 |
GIC_SET_TRIGGER(irq + i); |
481 |
} else {
|
482 |
GIC_CLEAR_TRIGGER(irq + i); |
483 |
} |
484 |
} |
485 |
} else {
|
486 |
/* 0xf00 is only handled for 32-bit writes. */
|
487 |
goto bad_reg;
|
488 |
} |
489 |
gic_update(s); |
490 |
return;
|
491 |
bad_reg:
|
492 |
qemu_log_mask(LOG_GUEST_ERROR, |
493 |
"gic_dist_writeb: Bad offset %x\n", (int)offset); |
494 |
} |
495 |
|
496 |
static void gic_dist_writew(void *opaque, hwaddr offset, |
497 |
uint32_t value) |
498 |
{ |
499 |
gic_dist_writeb(opaque, offset, value & 0xff);
|
500 |
gic_dist_writeb(opaque, offset + 1, value >> 8); |
501 |
} |
502 |
|
503 |
static void gic_dist_writel(void *opaque, hwaddr offset, |
504 |
uint32_t value) |
505 |
{ |
506 |
GICState *s = (GICState *)opaque; |
507 |
if (offset == 0xf00) { |
508 |
int cpu;
|
509 |
int irq;
|
510 |
int mask;
|
511 |
|
512 |
cpu = gic_get_current_cpu(s); |
513 |
irq = value & 0x3ff;
|
514 |
switch ((value >> 24) & 3) { |
515 |
case 0: |
516 |
mask = (value >> 16) & ALL_CPU_MASK;
|
517 |
break;
|
518 |
case 1: |
519 |
mask = ALL_CPU_MASK ^ (1 << cpu);
|
520 |
break;
|
521 |
case 2: |
522 |
mask = 1 << cpu;
|
523 |
break;
|
524 |
default:
|
525 |
DPRINTF("Bad Soft Int target filter\n");
|
526 |
mask = ALL_CPU_MASK; |
527 |
break;
|
528 |
} |
529 |
GIC_SET_PENDING(irq, mask); |
530 |
gic_update(s); |
531 |
return;
|
532 |
} |
533 |
gic_dist_writew(opaque, offset, value & 0xffff);
|
534 |
gic_dist_writew(opaque, offset + 2, value >> 16); |
535 |
} |
536 |
|
537 |
static const MemoryRegionOps gic_dist_ops = { |
538 |
.old_mmio = { |
539 |
.read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, |
540 |
.write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, |
541 |
}, |
542 |
.endianness = DEVICE_NATIVE_ENDIAN, |
543 |
}; |
544 |
|
545 |
static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) |
546 |
{ |
547 |
switch (offset) {
|
548 |
case 0x00: /* Control */ |
549 |
return s->cpu_enabled[cpu];
|
550 |
case 0x04: /* Priority mask */ |
551 |
return s->priority_mask[cpu];
|
552 |
case 0x08: /* Binary Point */ |
553 |
/* ??? Not implemented. */
|
554 |
return 0; |
555 |
case 0x0c: /* Acknowledge */ |
556 |
return gic_acknowledge_irq(s, cpu);
|
557 |
case 0x14: /* Running Priority */ |
558 |
return s->running_priority[cpu];
|
559 |
case 0x18: /* Highest Pending Interrupt */ |
560 |
return s->current_pending[cpu];
|
561 |
default:
|
562 |
qemu_log_mask(LOG_GUEST_ERROR, |
563 |
"gic_cpu_read: Bad offset %x\n", (int)offset); |
564 |
return 0; |
565 |
} |
566 |
} |
567 |
|
568 |
static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) |
569 |
{ |
570 |
switch (offset) {
|
571 |
case 0x00: /* Control */ |
572 |
s->cpu_enabled[cpu] = (value & 1);
|
573 |
DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis"); |
574 |
break;
|
575 |
case 0x04: /* Priority mask */ |
576 |
s->priority_mask[cpu] = (value & 0xff);
|
577 |
break;
|
578 |
case 0x08: /* Binary Point */ |
579 |
/* ??? Not implemented. */
|
580 |
break;
|
581 |
case 0x10: /* End Of Interrupt */ |
582 |
return gic_complete_irq(s, cpu, value & 0x3ff); |
583 |
default:
|
584 |
qemu_log_mask(LOG_GUEST_ERROR, |
585 |
"gic_cpu_write: Bad offset %x\n", (int)offset); |
586 |
return;
|
587 |
} |
588 |
gic_update(s); |
589 |
} |
590 |
|
591 |
/* Wrappers to read/write the GIC CPU interface for the current CPU */
|
592 |
static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr, |
593 |
unsigned size)
|
594 |
{ |
595 |
GICState *s = (GICState *)opaque; |
596 |
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
|
597 |
} |
598 |
|
599 |
static void gic_thiscpu_write(void *opaque, hwaddr addr, |
600 |
uint64_t value, unsigned size)
|
601 |
{ |
602 |
GICState *s = (GICState *)opaque; |
603 |
gic_cpu_write(s, gic_get_current_cpu(s), addr, value); |
604 |
} |
605 |
|
606 |
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
607 |
* These just decode the opaque pointer into GICState* + cpu id.
|
608 |
*/
|
609 |
static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr, |
610 |
unsigned size)
|
611 |
{ |
612 |
GICState **backref = (GICState **)opaque; |
613 |
GICState *s = *backref; |
614 |
int id = (backref - s->backref);
|
615 |
return gic_cpu_read(s, id, addr);
|
616 |
} |
617 |
|
618 |
static void gic_do_cpu_write(void *opaque, hwaddr addr, |
619 |
uint64_t value, unsigned size)
|
620 |
{ |
621 |
GICState **backref = (GICState **)opaque; |
622 |
GICState *s = *backref; |
623 |
int id = (backref - s->backref);
|
624 |
gic_cpu_write(s, id, addr, value); |
625 |
} |
626 |
|
627 |
static const MemoryRegionOps gic_thiscpu_ops = { |
628 |
.read = gic_thiscpu_read, |
629 |
.write = gic_thiscpu_write, |
630 |
.endianness = DEVICE_NATIVE_ENDIAN, |
631 |
}; |
632 |
|
633 |
static const MemoryRegionOps gic_cpu_ops = { |
634 |
.read = gic_do_cpu_read, |
635 |
.write = gic_do_cpu_write, |
636 |
.endianness = DEVICE_NATIVE_ENDIAN, |
637 |
}; |
638 |
|
639 |
void gic_init_irqs_and_distributor(GICState *s, int num_irq) |
640 |
{ |
641 |
int i;
|
642 |
|
643 |
i = s->num_irq - GIC_INTERNAL; |
644 |
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
|
645 |
* GPIO array layout is thus:
|
646 |
* [0..N-1] SPIs
|
647 |
* [N..N+31] PPIs for CPU 0
|
648 |
* [N+32..N+63] PPIs for CPU 1
|
649 |
* ...
|
650 |
*/
|
651 |
if (s->revision != REV_NVIC) {
|
652 |
i += (GIC_INTERNAL * s->num_cpu); |
653 |
} |
654 |
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); |
655 |
for (i = 0; i < NUM_CPU(s); i++) { |
656 |
sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
657 |
} |
658 |
memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, |
659 |
"gic_dist", 0x1000); |
660 |
} |
661 |
|
662 |
static void arm_gic_realize(DeviceState *dev, Error **errp) |
663 |
{ |
664 |
/* Device instance realize function for the GIC sysbus device */
|
665 |
int i;
|
666 |
GICState *s = ARM_GIC(dev); |
667 |
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
668 |
ARMGICClass *agc = ARM_GIC_GET_CLASS(s); |
669 |
|
670 |
agc->parent_realize(dev, errp); |
671 |
if (error_is_set(errp)) {
|
672 |
return;
|
673 |
} |
674 |
|
675 |
gic_init_irqs_and_distributor(s, s->num_irq); |
676 |
|
677 |
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
|
678 |
* a region for "CPU interface for this core", then a region for
|
679 |
* "CPU interface for core 0", "for core 1", ...
|
680 |
* NB that the memory region size of 0x100 applies for the 11MPCore
|
681 |
* and also cores following the GIC v1 spec (ie A9).
|
682 |
* GIC v2 defines a larger memory region (0x1000) so this will need
|
683 |
* to be extended when we implement A15.
|
684 |
*/
|
685 |
memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s,
|
686 |
"gic_cpu", 0x100); |
687 |
for (i = 0; i < NUM_CPU(s); i++) { |
688 |
s->backref[i] = s; |
689 |
memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
|
690 |
&s->backref[i], "gic_cpu", 0x100); |
691 |
} |
692 |
/* Distributor */
|
693 |
sysbus_init_mmio(sbd, &s->iomem); |
694 |
/* cpu interfaces (one for "current cpu" plus one per cpu) */
|
695 |
for (i = 0; i <= NUM_CPU(s); i++) { |
696 |
sysbus_init_mmio(sbd, &s->cpuiomem[i]); |
697 |
} |
698 |
} |
699 |
|
700 |
static void arm_gic_class_init(ObjectClass *klass, void *data) |
701 |
{ |
702 |
DeviceClass *dc = DEVICE_CLASS(klass); |
703 |
ARMGICClass *agc = ARM_GIC_CLASS(klass); |
704 |
|
705 |
dc->no_user = 1;
|
706 |
agc->parent_realize = dc->realize; |
707 |
dc->realize = arm_gic_realize; |
708 |
} |
709 |
|
710 |
static const TypeInfo arm_gic_info = { |
711 |
.name = TYPE_ARM_GIC, |
712 |
.parent = TYPE_ARM_GIC_COMMON, |
713 |
.instance_size = sizeof(GICState),
|
714 |
.class_init = arm_gic_class_init, |
715 |
.class_size = sizeof(ARMGICClass),
|
716 |
}; |
717 |
|
718 |
static void arm_gic_register_types(void) |
719 |
{ |
720 |
type_register_static(&arm_gic_info); |
721 |
} |
722 |
|
723 |
type_init(arm_gic_register_types) |