root / target-ppc / mmu-hash32.c @ 496272a7
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/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "helper.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "mmu-hash32.h" |
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|
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//#define DEBUG_MMU
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|
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0) |
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#else
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# define LOG_MMU(...) do { } while (0) |
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# define LOG_MMU_STATE(...) do { } while (0) |
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#endif
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|
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#define PTE_PTEM_MASK 0x7FFFFFBF |
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
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|
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static int ppc_hash32_pp_check(int key, int pp, int nx) |
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{
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int access;
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|
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/* Compute access rights */
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access = 0;
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if (key == 0) { |
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switch (pp) {
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case 0x0: |
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case 0x1: |
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case 0x2: |
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access |= PAGE_WRITE; |
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/* No break here */
|
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case 0x3: |
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access |= PAGE_READ; |
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break;
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} |
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} else {
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switch (pp) {
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case 0x0: |
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access = 0;
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break;
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case 0x1: |
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case 0x3: |
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access = PAGE_READ; |
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break;
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case 0x2: |
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access = PAGE_READ | PAGE_WRITE; |
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break;
|
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} |
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} |
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if (nx == 0) { |
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access |= PAGE_EXEC; |
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} |
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|
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return access;
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} |
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|
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static int ppc_hash32_check_prot(int prot, int rw, int access_type) |
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{
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int ret;
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|
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if (access_type == ACCESS_CODE) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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ret = -2;
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} |
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} else if (rw) { |
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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} |
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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} |
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} |
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|
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return ret;
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} |
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|
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static inline int pte_is_valid_hash32(target_ulong pte0) |
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{
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return pte0 & 0x80000000 ? 1 : 0; |
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} |
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|
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static int pte_check_hash32(mmu_ctx_t *ctx, target_ulong pte0, |
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target_ulong pte1, int h, int rw, int type) |
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{
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target_ulong ptem, mmask; |
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int access, ret, pteh, ptev, pp;
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ret = -1;
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/* Check validity and table match */
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ptev = pte_is_valid_hash32(pte0); |
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pteh = (pte0 >> 6) & 1; |
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if (ptev && h == pteh) {
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/* Check vsid & api */
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ptem = pte0 & PTE_PTEM_MASK; |
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mmask = PTE_CHECK_MASK; |
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pp = pte1 & 0x00000003;
|
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if (ptem == ctx->ptem) {
|
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if (ctx->raddr != (hwaddr)-1ULL) { |
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/* all matches should have equal RPN, WIMG & PP */
|
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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return -3; |
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} |
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} |
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/* Compute access rights */
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access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx); |
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/* Keep the matching PTE informations */
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ctx->raddr = pte1; |
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ctx->prot = access; |
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ret = ppc_hash32_check_prot(ctx->prot, rw, type); |
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if (ret == 0) { |
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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} |
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} |
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} |
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return ret;
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} |
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|
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static int ppc_hash32_pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, |
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int ret, int rw) |
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{
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int store = 0; |
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/* Update page flags */
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if (!(*pte1p & 0x00000100)) { |
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/* Update accessed flag */
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*pte1p |= 0x00000100;
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store = 1;
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} |
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if (!(*pte1p & 0x00000080)) { |
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if (rw == 1 && ret == 0) { |
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/* Update changed flag */
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*pte1p |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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ctx->prot &= ~PAGE_WRITE; |
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} |
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} |
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return store;
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} |
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|
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/* PTE table lookup */
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static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h, |
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int rw, int type, int target_page_bits) |
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{
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hwaddr pteg_off; |
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target_ulong pte0, pte1; |
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int i, good = -1; |
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int ret, r;
|
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ret = -1; /* No entry found */ |
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pteg_off = get_pteg_offset(env, ctx->hash[h], HASH_PTE_SIZE_32); |
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for (i = 0; i < 8; i++) { |
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if (env->external_htab) {
|
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pte0 = ldl_p(env->external_htab + pteg_off + (i * 8));
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pte1 = ldl_p(env->external_htab + pteg_off + (i * 8) + 4); |
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} else {
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pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
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pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4); |
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} |
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r = pte_check_hash32(ctx, pte0, pte1, h, rw, type); |
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LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " " |
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TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
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pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, |
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(int)((pte0 >> 6) & 1), ctx->ptem); |
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switch (r) {
|
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case -3: |
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/* PTE inconsistency */
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return -1; |
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case -2: |
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/* Access violation */
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ret = -2;
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good = i; |
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break;
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case -1: |
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default:
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/* No PTE match */
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break;
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case 0: |
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/* access granted */
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/* XXX: we should go on looping to check all PTEs consistency
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* but if we can speed-up the whole thing as the
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* result would be undefined if PTEs are not consistent.
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*/
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ret = 0;
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good = i; |
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goto done;
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} |
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} |
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if (good != -1) { |
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done:
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LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n", |
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ctx->raddr, ctx->prot, ret); |
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/* Update page flags */
|
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pte1 = ctx->raddr; |
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if (ppc_hash32_pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
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if (env->external_htab) {
|
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stl_p(env->external_htab + pteg_off + (good * 8) + 4, |
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pte1); |
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} else {
|
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stl_phys_notdirty(env->htab_base + pteg_off + |
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(good * 8) + 4, pte1); |
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} |
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} |
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} |
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|
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
|
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if (target_page_bits != TARGET_PAGE_BITS) {
|
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ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1)) |
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& TARGET_PAGE_MASK; |
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} |
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return ret;
|
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} |
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|
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static int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx, |
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target_ulong eaddr, int rw, int type) |
| 253 |
{
|
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hwaddr hash; |
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target_ulong vsid; |
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int ds, pr, target_page_bits;
|
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int ret, ret2;
|
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target_ulong sr, pgidx; |
| 259 |
|
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pr = msr_pr; |
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ctx->eaddr = eaddr; |
| 262 |
|
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sr = env->sr[eaddr >> 28];
|
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ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
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((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
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ds = sr & 0x80000000 ? 1 : 0; |
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ctx->nx = sr & 0x10000000 ? 1 : 0; |
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vsid = sr & 0x00FFFFFF;
|
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target_page_bits = TARGET_PAGE_BITS; |
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" |
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
|
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" ir=%d dr=%d pr=%d %d t=%d\n",
|
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, |
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(int)msr_dr, pr != 0 ? 1 : 0, rw, type); |
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits; |
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hash = vsid ^ pgidx; |
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ctx->ptem = (vsid << 7) | (pgidx >> 10); |
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|
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LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", |
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ctx->key, ds, ctx->nx, vsid); |
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ret = -1;
|
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if (!ds) {
|
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/* Check if instruction fetch is allowed, if needed */
|
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if (type != ACCESS_CODE || ctx->nx == 0) { |
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/* Page address translation */
|
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx |
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" hash " TARGET_FMT_plx "\n", |
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env->htab_base, env->htab_mask, hash); |
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ctx->hash[0] = hash;
|
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ctx->hash[1] = ~hash;
|
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|
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/* Initialize real address with an invalid value */
|
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ctx->raddr = (hwaddr)-1ULL;
|
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
| 295 |
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
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" hash=" TARGET_FMT_plx "\n", |
| 297 |
env->htab_base, env->htab_mask, vsid, ctx->ptem, |
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ctx->hash[0]);
|
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/* Primary table lookup */
|
| 300 |
ret = find_pte32(env, ctx, 0, rw, type, target_page_bits);
|
| 301 |
if (ret < 0) { |
| 302 |
/* Secondary table lookup */
|
| 303 |
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx |
| 304 |
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
| 305 |
" hash=" TARGET_FMT_plx "\n", env->htab_base, |
| 306 |
env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
|
| 307 |
ret2 = find_pte32(env, ctx, 1, rw, type,
|
| 308 |
target_page_bits); |
| 309 |
if (ret2 != -1) { |
| 310 |
ret = ret2; |
| 311 |
} |
| 312 |
} |
| 313 |
#if defined(DUMP_PAGE_TABLES)
|
| 314 |
if (qemu_log_enabled()) {
|
| 315 |
hwaddr curaddr; |
| 316 |
uint32_t a0, a1, a2, a3; |
| 317 |
|
| 318 |
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx |
| 319 |
"\n", sdr, mask + 0x80); |
| 320 |
for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
| 321 |
curaddr += 16) {
|
| 322 |
a0 = ldl_phys(curaddr); |
| 323 |
a1 = ldl_phys(curaddr + 4);
|
| 324 |
a2 = ldl_phys(curaddr + 8);
|
| 325 |
a3 = ldl_phys(curaddr + 12);
|
| 326 |
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
| 327 |
qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
|
| 328 |
curaddr, a0, a1, a2, a3); |
| 329 |
} |
| 330 |
} |
| 331 |
} |
| 332 |
#endif
|
| 333 |
} else {
|
| 334 |
LOG_MMU("No access allowed\n");
|
| 335 |
ret = -3;
|
| 336 |
} |
| 337 |
} else {
|
| 338 |
target_ulong sr; |
| 339 |
|
| 340 |
LOG_MMU("direct store...\n");
|
| 341 |
/* Direct-store segment : absolutely *BUGGY* for now */
|
| 342 |
|
| 343 |
/* Direct-store implies a 32-bit MMU.
|
| 344 |
* Check the Segment Register's bus unit ID (BUID).
|
| 345 |
*/
|
| 346 |
sr = env->sr[eaddr >> 28];
|
| 347 |
if ((sr & 0x1FF00000) >> 20 == 0x07f) { |
| 348 |
/* Memory-forced I/O controller interface access */
|
| 349 |
/* If T=1 and BUID=x'07F', the 601 performs a memory access
|
| 350 |
* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
|
| 351 |
*/
|
| 352 |
ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); |
| 353 |
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 354 |
return 0; |
| 355 |
} |
| 356 |
|
| 357 |
switch (type) {
|
| 358 |
case ACCESS_INT:
|
| 359 |
/* Integer load/store : only access allowed */
|
| 360 |
break;
|
| 361 |
case ACCESS_CODE:
|
| 362 |
/* No code fetch is allowed in direct-store areas */
|
| 363 |
return -4; |
| 364 |
case ACCESS_FLOAT:
|
| 365 |
/* Floating point load/store */
|
| 366 |
return -4; |
| 367 |
case ACCESS_RES:
|
| 368 |
/* lwarx, ldarx or srwcx. */
|
| 369 |
return -4; |
| 370 |
case ACCESS_CACHE:
|
| 371 |
/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
| 372 |
/* Should make the instruction do no-op.
|
| 373 |
* As it already do no-op, it's quite easy :-)
|
| 374 |
*/
|
| 375 |
ctx->raddr = eaddr; |
| 376 |
return 0; |
| 377 |
case ACCESS_EXT:
|
| 378 |
/* eciwx or ecowx */
|
| 379 |
return -4; |
| 380 |
default:
|
| 381 |
qemu_log("ERROR: instruction should not need "
|
| 382 |
"address translation\n");
|
| 383 |
return -4; |
| 384 |
} |
| 385 |
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
| 386 |
ctx->raddr = eaddr; |
| 387 |
ret = 2;
|
| 388 |
} else {
|
| 389 |
ret = -2;
|
| 390 |
} |
| 391 |
} |
| 392 |
|
| 393 |
return ret;
|
| 394 |
} |
| 395 |
|
| 396 |
|
| 397 |
static int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, |
| 398 |
target_ulong eaddr, int rw,
|
| 399 |
int access_type)
|
| 400 |
{
|
| 401 |
bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) |
| 402 |
|| (access_type != ACCESS_CODE && msr_dr == 0);
|
| 403 |
|
| 404 |
if (real_mode) {
|
| 405 |
ctx->raddr = eaddr; |
| 406 |
ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; |
| 407 |
return 0; |
| 408 |
} else {
|
| 409 |
int ret = -1; |
| 410 |
|
| 411 |
/* Try to find a BAT */
|
| 412 |
if (env->nb_BATs != 0) { |
| 413 |
ret = get_bat(env, ctx, eaddr, rw, access_type); |
| 414 |
} |
| 415 |
if (ret < 0) { |
| 416 |
/* We didn't match any BAT entry or don't have BATs */
|
| 417 |
ret = get_segment32(env, ctx, eaddr, rw, access_type); |
| 418 |
} |
| 419 |
return ret;
|
| 420 |
} |
| 421 |
} |
| 422 |
|
| 423 |
hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr) |
| 424 |
{
|
| 425 |
mmu_ctx_t ctx; |
| 426 |
|
| 427 |
if (unlikely(ppc_hash32_get_physical_address(env, &ctx, addr, 0, ACCESS_INT) |
| 428 |
!= 0)) {
|
| 429 |
return -1; |
| 430 |
} |
| 431 |
|
| 432 |
return ctx.raddr & TARGET_PAGE_MASK;
|
| 433 |
} |
| 434 |
|
| 435 |
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, |
| 436 |
int mmu_idx)
|
| 437 |
{
|
| 438 |
mmu_ctx_t ctx; |
| 439 |
int access_type;
|
| 440 |
int ret = 0; |
| 441 |
|
| 442 |
if (rw == 2) { |
| 443 |
/* code access */
|
| 444 |
rw = 0;
|
| 445 |
access_type = ACCESS_CODE; |
| 446 |
} else {
|
| 447 |
/* data access */
|
| 448 |
access_type = env->access_type; |
| 449 |
} |
| 450 |
ret = ppc_hash32_get_physical_address(env, &ctx, address, rw, access_type); |
| 451 |
if (ret == 0) { |
| 452 |
tlb_set_page(env, address & TARGET_PAGE_MASK, |
| 453 |
ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
| 454 |
mmu_idx, TARGET_PAGE_SIZE); |
| 455 |
ret = 0;
|
| 456 |
} else if (ret < 0) { |
| 457 |
LOG_MMU_STATE(env); |
| 458 |
if (access_type == ACCESS_CODE) {
|
| 459 |
switch (ret) {
|
| 460 |
case -1: |
| 461 |
/* No matches in page tables or TLB */
|
| 462 |
env->exception_index = POWERPC_EXCP_ISI; |
| 463 |
env->error_code = 0x40000000;
|
| 464 |
break;
|
| 465 |
case -2: |
| 466 |
/* Access rights violation */
|
| 467 |
env->exception_index = POWERPC_EXCP_ISI; |
| 468 |
env->error_code = 0x08000000;
|
| 469 |
break;
|
| 470 |
case -3: |
| 471 |
/* No execute protection violation */
|
| 472 |
env->exception_index = POWERPC_EXCP_ISI; |
| 473 |
env->error_code = 0x10000000;
|
| 474 |
break;
|
| 475 |
case -4: |
| 476 |
/* Direct store exception */
|
| 477 |
/* No code fetch is allowed in direct-store areas */
|
| 478 |
env->exception_index = POWERPC_EXCP_ISI; |
| 479 |
env->error_code = 0x10000000;
|
| 480 |
break;
|
| 481 |
} |
| 482 |
} else {
|
| 483 |
switch (ret) {
|
| 484 |
case -1: |
| 485 |
/* No matches in page tables or TLB */
|
| 486 |
env->exception_index = POWERPC_EXCP_DSI; |
| 487 |
env->error_code = 0;
|
| 488 |
env->spr[SPR_DAR] = address; |
| 489 |
if (rw == 1) { |
| 490 |
env->spr[SPR_DSISR] = 0x42000000;
|
| 491 |
} else {
|
| 492 |
env->spr[SPR_DSISR] = 0x40000000;
|
| 493 |
} |
| 494 |
break;
|
| 495 |
case -2: |
| 496 |
/* Access rights violation */
|
| 497 |
env->exception_index = POWERPC_EXCP_DSI; |
| 498 |
env->error_code = 0;
|
| 499 |
env->spr[SPR_DAR] = address; |
| 500 |
if (rw == 1) { |
| 501 |
env->spr[SPR_DSISR] = 0x0A000000;
|
| 502 |
} else {
|
| 503 |
env->spr[SPR_DSISR] = 0x08000000;
|
| 504 |
} |
| 505 |
break;
|
| 506 |
case -4: |
| 507 |
/* Direct store exception */
|
| 508 |
switch (access_type) {
|
| 509 |
case ACCESS_FLOAT:
|
| 510 |
/* Floating point load/store */
|
| 511 |
env->exception_index = POWERPC_EXCP_ALIGN; |
| 512 |
env->error_code = POWERPC_EXCP_ALIGN_FP; |
| 513 |
env->spr[SPR_DAR] = address; |
| 514 |
break;
|
| 515 |
case ACCESS_RES:
|
| 516 |
/* lwarx, ldarx or stwcx. */
|
| 517 |
env->exception_index = POWERPC_EXCP_DSI; |
| 518 |
env->error_code = 0;
|
| 519 |
env->spr[SPR_DAR] = address; |
| 520 |
if (rw == 1) { |
| 521 |
env->spr[SPR_DSISR] = 0x06000000;
|
| 522 |
} else {
|
| 523 |
env->spr[SPR_DSISR] = 0x04000000;
|
| 524 |
} |
| 525 |
break;
|
| 526 |
case ACCESS_EXT:
|
| 527 |
/* eciwx or ecowx */
|
| 528 |
env->exception_index = POWERPC_EXCP_DSI; |
| 529 |
env->error_code = 0;
|
| 530 |
env->spr[SPR_DAR] = address; |
| 531 |
if (rw == 1) { |
| 532 |
env->spr[SPR_DSISR] = 0x06100000;
|
| 533 |
} else {
|
| 534 |
env->spr[SPR_DSISR] = 0x04100000;
|
| 535 |
} |
| 536 |
break;
|
| 537 |
default:
|
| 538 |
printf("DSI: invalid exception (%d)\n", ret);
|
| 539 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
| 540 |
env->error_code = |
| 541 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
| 542 |
env->spr[SPR_DAR] = address; |
| 543 |
break;
|
| 544 |
} |
| 545 |
break;
|
| 546 |
} |
| 547 |
} |
| 548 |
#if 0
|
| 549 |
printf("%s: set exception to %d %02x\n", __func__,
|
| 550 |
env->exception, env->error_code);
|
| 551 |
#endif
|
| 552 |
ret = 1;
|
| 553 |
} |
| 554 |
|
| 555 |
return ret;
|
| 556 |
} |