root / hw / display / cirrus_vga.c @ 49ab747f
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1 | e6e5ad80 | bellard | /*
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2 | aeb3c85f | bellard | * QEMU Cirrus CLGD 54xx VGA Emulator.
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3 | 5fafdf24 | ths | *
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4 | e6e5ad80 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | aeb3c85f | bellard | * Copyright (c) 2004 Makoto Suzuki (suzu)
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6 | 5fafdf24 | ths | *
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7 | e6e5ad80 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | e6e5ad80 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | e6e5ad80 | bellard | * in the Software without restriction, including without limitation the rights
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10 | e6e5ad80 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | e6e5ad80 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | e6e5ad80 | bellard | * furnished to do so, subject to the following conditions:
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13 | e6e5ad80 | bellard | *
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14 | e6e5ad80 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | e6e5ad80 | bellard | * all copies or substantial portions of the Software.
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16 | e6e5ad80 | bellard | *
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17 | e6e5ad80 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | e6e5ad80 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | e6e5ad80 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | e6e5ad80 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | e6e5ad80 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | e6e5ad80 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | e6e5ad80 | bellard | * THE SOFTWARE.
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24 | e6e5ad80 | bellard | */
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25 | aeb3c85f | bellard | /*
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26 | aeb3c85f | bellard | * Reference: Finn Thogersons' VGADOC4b
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27 | aeb3c85f | bellard | * available at http://home.worldonline.dk/~finth/
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28 | aeb3c85f | bellard | */
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29 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci.h" |
31 | 28ecbaee | Paolo Bonzini | #include "ui/console.h" |
32 | 83c9f4ca | Paolo Bonzini | #include "hw/vga_int.h" |
33 | 83c9f4ca | Paolo Bonzini | #include "hw/loader.h" |
34 | e6e5ad80 | bellard | |
35 | a5082316 | bellard | /*
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36 | a5082316 | bellard | * TODO:
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37 | ad81218e | bellard | * - destination write mask support not complete (bits 5..7)
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38 | a5082316 | bellard | * - optimize linear mappings
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39 | a5082316 | bellard | * - optimize bitblt functions
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40 | a5082316 | bellard | */
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41 | a5082316 | bellard | |
42 | e36f36e1 | bellard | //#define DEBUG_CIRRUS
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43 | a21ae81d | bellard | //#define DEBUG_BITBLT
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44 | e36f36e1 | bellard | |
45 | e6e5ad80 | bellard | /***************************************
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46 | e6e5ad80 | bellard | *
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47 | e6e5ad80 | bellard | * definitions
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48 | e6e5ad80 | bellard | *
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49 | e6e5ad80 | bellard | ***************************************/
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50 | e6e5ad80 | bellard | |
51 | e6e5ad80 | bellard | // ID
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52 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5422 (0x23<<2) |
53 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5426 (0x24<<2) |
54 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5424 (0x25<<2) |
55 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5428 (0x26<<2) |
56 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5430 (0x28<<2) |
57 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5434 (0x2A<<2) |
58 | a21ae81d | bellard | #define CIRRUS_ID_CLGD5436 (0x2B<<2) |
59 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
60 | e6e5ad80 | bellard | |
61 | e6e5ad80 | bellard | // sequencer 0x07
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62 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_VGA 0x00 |
63 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_SVGA 0x01 |
64 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_MASK 0x0e |
65 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_8 0x00 |
66 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
67 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_24 0x04 |
68 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16 0x06 |
69 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_32 0x08 |
70 | e6e5ad80 | bellard | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
71 | e6e5ad80 | bellard | |
72 | e6e5ad80 | bellard | // sequencer 0x0f
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73 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_512k 0x08 |
74 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_1M 0x10 |
75 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_2M 0x18 |
76 | e6e5ad80 | bellard | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
77 | e6e5ad80 | bellard | |
78 | e6e5ad80 | bellard | // sequencer 0x12
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79 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_SHOW 0x01 |
80 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_HIDDENPEL 0x02 |
81 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
82 | e6e5ad80 | bellard | |
83 | e6e5ad80 | bellard | // sequencer 0x17
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84 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBFAST 0x10 |
85 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_PCI 0x20 |
86 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
87 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_ISA 0x38 |
88 | e6e5ad80 | bellard | #define CIRRUS_MMIO_ENABLE 0x04 |
89 | e6e5ad80 | bellard | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
90 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
91 | e6e5ad80 | bellard | |
92 | e6e5ad80 | bellard | // control 0x0b
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93 | e6e5ad80 | bellard | #define CIRRUS_BANKING_DUAL 0x01 |
94 | e6e5ad80 | bellard | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
95 | e6e5ad80 | bellard | |
96 | e6e5ad80 | bellard | // control 0x30
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97 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_BACKWARDS 0x01 |
98 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
99 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
100 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
101 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
102 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
103 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
104 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
105 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
106 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
107 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
108 | e6e5ad80 | bellard | |
109 | e6e5ad80 | bellard | // control 0x31
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110 | e6e5ad80 | bellard | #define CIRRUS_BLT_BUSY 0x01 |
111 | e6e5ad80 | bellard | #define CIRRUS_BLT_START 0x02 |
112 | e6e5ad80 | bellard | #define CIRRUS_BLT_RESET 0x04 |
113 | e6e5ad80 | bellard | #define CIRRUS_BLT_FIFOUSED 0x10 |
114 | a5082316 | bellard | #define CIRRUS_BLT_AUTOSTART 0x80 |
115 | e6e5ad80 | bellard | |
116 | e6e5ad80 | bellard | // control 0x32
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117 | e6e5ad80 | bellard | #define CIRRUS_ROP_0 0x00 |
118 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_DST 0x05 |
119 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOP 0x06 |
120 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
121 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTDST 0x0b |
122 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC 0x0d |
123 | e6e5ad80 | bellard | #define CIRRUS_ROP_1 0x0e |
124 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
125 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_XOR_DST 0x59 |
126 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_DST 0x6d |
127 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
128 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
129 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
130 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC 0xd0 |
131 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
132 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
133 | e6e5ad80 | bellard | |
134 | a5082316 | bellard | #define CIRRUS_ROP_NOP_INDEX 2 |
135 | a5082316 | bellard | #define CIRRUS_ROP_SRC_INDEX 5 |
136 | a5082316 | bellard | |
137 | a21ae81d | bellard | // control 0x33
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138 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
139 | 4c8732d7 | bellard | #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
140 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
141 | a21ae81d | bellard | |
142 | e6e5ad80 | bellard | // memory-mapped IO
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143 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
144 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
145 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
146 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
147 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
148 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
149 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
150 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
151 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
152 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODE 0x18 // byte |
153 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTROP 0x1a // byte |
154 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
155 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
156 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
157 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
158 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
159 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
160 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
161 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
162 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
163 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
164 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
165 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
166 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
167 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
168 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
169 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
170 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
171 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
172 | e6e5ad80 | bellard | |
173 | a21ae81d | bellard | #define CIRRUS_PNPMMIO_SIZE 0x1000 |
174 | e6e5ad80 | bellard | |
175 | b2eb849d | aurel32 | #define BLTUNSAFE(s) \
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176 | b2eb849d | aurel32 | ( \ |
177 | b2eb849d | aurel32 | ( /* check dst is within bounds */ \
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178 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ |
179 | b2eb849d | aurel32 | + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ |
180 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
181 | b2eb849d | aurel32 | ) || \ |
182 | b2eb849d | aurel32 | ( /* check src is within bounds */ \
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183 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ |
184 | b2eb849d | aurel32 | + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ |
185 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
186 | b2eb849d | aurel32 | ) \ |
187 | b2eb849d | aurel32 | ) |
188 | b2eb849d | aurel32 | |
189 | a5082316 | bellard | struct CirrusVGAState;
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190 | a5082316 | bellard | typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, |
191 | a5082316 | bellard | uint8_t * dst, const uint8_t * src,
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192 | e6e5ad80 | bellard | int dstpitch, int srcpitch, |
193 | e6e5ad80 | bellard | int bltwidth, int bltheight); |
194 | a5082316 | bellard | typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
195 | a5082316 | bellard | uint8_t *dst, int dst_pitch, int width, int height); |
196 | e6e5ad80 | bellard | |
197 | e6e5ad80 | bellard | typedef struct CirrusVGAState { |
198 | 4e12cd94 | Avi Kivity | VGACommonState vga; |
199 | e6e5ad80 | bellard | |
200 | c75e6d8e | Julien Grall | MemoryRegion cirrus_vga_io; |
201 | b1950430 | Avi Kivity | MemoryRegion cirrus_linear_io; |
202 | b1950430 | Avi Kivity | MemoryRegion cirrus_linear_bitblt_io; |
203 | b1950430 | Avi Kivity | MemoryRegion cirrus_mmio_io; |
204 | b1950430 | Avi Kivity | MemoryRegion pci_bar; |
205 | b1950430 | Avi Kivity | bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ |
206 | b1950430 | Avi Kivity | MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
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207 | b1950430 | Avi Kivity | MemoryRegion low_mem; /* always mapped, overridden by: */
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208 | 7969d9ed | Avi Kivity | MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ |
209 | e6e5ad80 | bellard | uint32_t cirrus_addr_mask; |
210 | 78e127ef | bellard | uint32_t linear_mmio_mask; |
211 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr0; |
212 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr1; |
213 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_lockindex; |
214 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_data; |
215 | e6e5ad80 | bellard | uint32_t cirrus_bank_base[2];
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216 | e6e5ad80 | bellard | uint32_t cirrus_bank_limit[2];
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217 | e6e5ad80 | bellard | uint8_t cirrus_hidden_palette[48];
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218 | a5082316 | bellard | uint32_t hw_cursor_x; |
219 | a5082316 | bellard | uint32_t hw_cursor_y; |
220 | e6e5ad80 | bellard | int cirrus_blt_pixelwidth;
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221 | e6e5ad80 | bellard | int cirrus_blt_width;
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222 | e6e5ad80 | bellard | int cirrus_blt_height;
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223 | e6e5ad80 | bellard | int cirrus_blt_dstpitch;
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224 | e6e5ad80 | bellard | int cirrus_blt_srcpitch;
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225 | a5082316 | bellard | uint32_t cirrus_blt_fgcol; |
226 | a5082316 | bellard | uint32_t cirrus_blt_bgcol; |
227 | e6e5ad80 | bellard | uint32_t cirrus_blt_dstaddr; |
228 | e6e5ad80 | bellard | uint32_t cirrus_blt_srcaddr; |
229 | e6e5ad80 | bellard | uint8_t cirrus_blt_mode; |
230 | a5082316 | bellard | uint8_t cirrus_blt_modeext; |
231 | e6e5ad80 | bellard | cirrus_bitblt_rop_t cirrus_rop; |
232 | a5082316 | bellard | #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
233 | e6e5ad80 | bellard | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
234 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr; |
235 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr_end; |
236 | e6e5ad80 | bellard | uint32_t cirrus_srccounter; |
237 | a5082316 | bellard | /* hwcursor display state */
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238 | a5082316 | bellard | int last_hw_cursor_size;
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239 | a5082316 | bellard | int last_hw_cursor_x;
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240 | a5082316 | bellard | int last_hw_cursor_y;
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241 | a5082316 | bellard | int last_hw_cursor_y_start;
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242 | a5082316 | bellard | int last_hw_cursor_y_end;
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243 | 78e127ef | bellard | int real_vram_size; /* XXX: suppress that */ |
244 | 4abc796d | blueswir1 | int device_id;
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245 | 4abc796d | blueswir1 | int bustype;
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246 | e6e5ad80 | bellard | } CirrusVGAState; |
247 | e6e5ad80 | bellard | |
248 | e6e5ad80 | bellard | typedef struct PCICirrusVGAState { |
249 | e6e5ad80 | bellard | PCIDevice dev; |
250 | e6e5ad80 | bellard | CirrusVGAState cirrus_vga; |
251 | e6e5ad80 | bellard | } PCICirrusVGAState; |
252 | e6e5ad80 | bellard | |
253 | 3d402831 | Blue Swirl | typedef struct ISACirrusVGAState { |
254 | 3d402831 | Blue Swirl | ISADevice dev; |
255 | 3d402831 | Blue Swirl | CirrusVGAState cirrus_vga; |
256 | 3d402831 | Blue Swirl | } ISACirrusVGAState; |
257 | 3d402831 | Blue Swirl | |
258 | a5082316 | bellard | static uint8_t rop_to_index[256]; |
259 | 3b46e624 | ths | |
260 | e6e5ad80 | bellard | /***************************************
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261 | e6e5ad80 | bellard | *
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262 | e6e5ad80 | bellard | * prototypes.
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263 | e6e5ad80 | bellard | *
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264 | e6e5ad80 | bellard | ***************************************/
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265 | e6e5ad80 | bellard | |
266 | e6e5ad80 | bellard | |
267 | 8926b517 | bellard | static void cirrus_bitblt_reset(CirrusVGAState *s); |
268 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s); |
269 | e6e5ad80 | bellard | |
270 | e6e5ad80 | bellard | /***************************************
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271 | e6e5ad80 | bellard | *
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272 | e6e5ad80 | bellard | * raster operations
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273 | e6e5ad80 | bellard | *
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274 | e6e5ad80 | bellard | ***************************************/
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275 | e6e5ad80 | bellard | |
276 | a5082316 | bellard | static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
277 | a5082316 | bellard | uint8_t *dst,const uint8_t *src,
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278 | a5082316 | bellard | int dstpitch,int srcpitch, |
279 | a5082316 | bellard | int bltwidth,int bltheight) |
280 | a5082316 | bellard | { |
281 | e6e5ad80 | bellard | } |
282 | e6e5ad80 | bellard | |
283 | a5082316 | bellard | static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
284 | a5082316 | bellard | uint8_t *dst, |
285 | a5082316 | bellard | int dstpitch, int bltwidth,int bltheight) |
286 | e6e5ad80 | bellard | { |
287 | a5082316 | bellard | } |
288 | e6e5ad80 | bellard | |
289 | a5082316 | bellard | #define ROP_NAME 0 |
290 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) 0 |
291 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
292 | e6e5ad80 | bellard | |
293 | a5082316 | bellard | #define ROP_NAME src_and_dst
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294 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) & (d)
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295 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
296 | e6e5ad80 | bellard | |
297 | a5082316 | bellard | #define ROP_NAME src_and_notdst
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298 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) & (~(d))
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299 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
300 | e6e5ad80 | bellard | |
301 | a5082316 | bellard | #define ROP_NAME notdst
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302 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~(d)
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303 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
304 | e6e5ad80 | bellard | |
305 | a5082316 | bellard | #define ROP_NAME src
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306 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) s
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307 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
308 | e6e5ad80 | bellard | |
309 | a5082316 | bellard | #define ROP_NAME 1 |
310 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~0 |
311 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
312 | a5082316 | bellard | |
313 | a5082316 | bellard | #define ROP_NAME notsrc_and_dst
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314 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) & (d)
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315 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
316 | a5082316 | bellard | |
317 | a5082316 | bellard | #define ROP_NAME src_xor_dst
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318 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) ^ (d)
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319 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
320 | a5082316 | bellard | |
321 | a5082316 | bellard | #define ROP_NAME src_or_dst
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322 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) | (d)
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323 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
324 | a5082316 | bellard | |
325 | a5082316 | bellard | #define ROP_NAME notsrc_or_notdst
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326 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) | (~(d))
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327 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
328 | a5082316 | bellard | |
329 | a5082316 | bellard | #define ROP_NAME src_notxor_dst
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330 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~((s) ^ (d))
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331 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
332 | e6e5ad80 | bellard | |
333 | a5082316 | bellard | #define ROP_NAME src_or_notdst
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334 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) | (~(d))
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335 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
336 | a5082316 | bellard | |
337 | a5082316 | bellard | #define ROP_NAME notsrc
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338 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s))
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339 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
340 | a5082316 | bellard | |
341 | a5082316 | bellard | #define ROP_NAME notsrc_or_dst
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342 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) | (d)
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343 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
344 | a5082316 | bellard | |
345 | a5082316 | bellard | #define ROP_NAME notsrc_and_notdst
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346 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) & (~(d))
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347 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_rop.h" |
348 | a5082316 | bellard | |
349 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { |
350 | a5082316 | bellard | cirrus_bitblt_rop_fwd_0, |
351 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_dst, |
352 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
353 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_notdst, |
354 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notdst, |
355 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src, |
356 | a5082316 | bellard | cirrus_bitblt_rop_fwd_1, |
357 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_dst, |
358 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_xor_dst, |
359 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_dst, |
360 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_notdst, |
361 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_notxor_dst, |
362 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_notdst, |
363 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc, |
364 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_dst, |
365 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_notdst, |
366 | a5082316 | bellard | }; |
367 | a5082316 | bellard | |
368 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { |
369 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_0, |
370 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_dst, |
371 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
372 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_notdst, |
373 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notdst, |
374 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src, |
375 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_1, |
376 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_dst, |
377 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_xor_dst, |
378 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_dst, |
379 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_notdst, |
380 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_notxor_dst, |
381 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_notdst, |
382 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc, |
383 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_dst, |
384 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_notdst, |
385 | a5082316 | bellard | }; |
386 | 96cf2df8 | ths | |
387 | 96cf2df8 | ths | #define TRANSP_ROP(name) {\
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388 | 96cf2df8 | ths | name ## _8,\ |
389 | 96cf2df8 | ths | name ## _16,\ |
390 | 96cf2df8 | ths | } |
391 | 96cf2df8 | ths | #define TRANSP_NOP(func) {\
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392 | 96cf2df8 | ths | func,\ |
393 | 96cf2df8 | ths | func,\ |
394 | 96cf2df8 | ths | } |
395 | 96cf2df8 | ths | |
396 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { |
397 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), |
398 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), |
399 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
400 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), |
401 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), |
402 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), |
403 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), |
404 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), |
405 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), |
406 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), |
407 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), |
408 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), |
409 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), |
410 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), |
411 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), |
412 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), |
413 | 96cf2df8 | ths | }; |
414 | 96cf2df8 | ths | |
415 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { |
416 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), |
417 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), |
418 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
419 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), |
420 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), |
421 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), |
422 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), |
423 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), |
424 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), |
425 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), |
426 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), |
427 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), |
428 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), |
429 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), |
430 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), |
431 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), |
432 | 96cf2df8 | ths | }; |
433 | 96cf2df8 | ths | |
434 | a5082316 | bellard | #define ROP2(name) {\
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435 | a5082316 | bellard | name ## _8,\ |
436 | a5082316 | bellard | name ## _16,\ |
437 | a5082316 | bellard | name ## _24,\ |
438 | a5082316 | bellard | name ## _32,\ |
439 | a5082316 | bellard | } |
440 | a5082316 | bellard | |
441 | a5082316 | bellard | #define ROP_NOP2(func) {\
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442 | a5082316 | bellard | func,\ |
443 | a5082316 | bellard | func,\ |
444 | a5082316 | bellard | func,\ |
445 | a5082316 | bellard | func,\ |
446 | a5082316 | bellard | } |
447 | a5082316 | bellard | |
448 | e69390ce | bellard | static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
449 | e69390ce | bellard | ROP2(cirrus_patternfill_0), |
450 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_dst), |
451 | e69390ce | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
452 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_notdst), |
453 | e69390ce | bellard | ROP2(cirrus_patternfill_notdst), |
454 | e69390ce | bellard | ROP2(cirrus_patternfill_src), |
455 | e69390ce | bellard | ROP2(cirrus_patternfill_1), |
456 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_dst), |
457 | e69390ce | bellard | ROP2(cirrus_patternfill_src_xor_dst), |
458 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_dst), |
459 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_notdst), |
460 | e69390ce | bellard | ROP2(cirrus_patternfill_src_notxor_dst), |
461 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_notdst), |
462 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc), |
463 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_dst), |
464 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_notdst), |
465 | e69390ce | bellard | }; |
466 | e69390ce | bellard | |
467 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
468 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_0), |
469 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_dst), |
470 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
471 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_notdst), |
472 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notdst), |
473 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src), |
474 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_1), |
475 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_dst), |
476 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_xor_dst), |
477 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_dst), |
478 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), |
479 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_notxor_dst), |
480 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_notdst), |
481 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc), |
482 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_dst), |
483 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
484 | a5082316 | bellard | }; |
485 | a5082316 | bellard | |
486 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
487 | a5082316 | bellard | ROP2(cirrus_colorexpand_0), |
488 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_dst), |
489 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
490 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_notdst), |
491 | a5082316 | bellard | ROP2(cirrus_colorexpand_notdst), |
492 | a5082316 | bellard | ROP2(cirrus_colorexpand_src), |
493 | a5082316 | bellard | ROP2(cirrus_colorexpand_1), |
494 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_dst), |
495 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_xor_dst), |
496 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_dst), |
497 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_notdst), |
498 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_notxor_dst), |
499 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_notdst), |
500 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc), |
501 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_dst), |
502 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_notdst), |
503 | a5082316 | bellard | }; |
504 | a5082316 | bellard | |
505 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
506 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_0), |
507 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
508 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
509 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
510 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notdst), |
511 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src), |
512 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_1), |
513 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
514 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
515 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
516 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
517 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
518 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
519 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
520 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
521 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
522 | b30d4608 | bellard | }; |
523 | b30d4608 | bellard | |
524 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
525 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_0), |
526 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_dst), |
527 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
528 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
529 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notdst), |
530 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src), |
531 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_1), |
532 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
533 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
534 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_dst), |
535 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
536 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
537 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
538 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc), |
539 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
540 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
541 | b30d4608 | bellard | }; |
542 | b30d4608 | bellard | |
543 | a5082316 | bellard | static const cirrus_fill_t cirrus_fill[16][4] = { |
544 | a5082316 | bellard | ROP2(cirrus_fill_0), |
545 | a5082316 | bellard | ROP2(cirrus_fill_src_and_dst), |
546 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_fill_nop), |
547 | a5082316 | bellard | ROP2(cirrus_fill_src_and_notdst), |
548 | a5082316 | bellard | ROP2(cirrus_fill_notdst), |
549 | a5082316 | bellard | ROP2(cirrus_fill_src), |
550 | a5082316 | bellard | ROP2(cirrus_fill_1), |
551 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_dst), |
552 | a5082316 | bellard | ROP2(cirrus_fill_src_xor_dst), |
553 | a5082316 | bellard | ROP2(cirrus_fill_src_or_dst), |
554 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_notdst), |
555 | a5082316 | bellard | ROP2(cirrus_fill_src_notxor_dst), |
556 | a5082316 | bellard | ROP2(cirrus_fill_src_or_notdst), |
557 | a5082316 | bellard | ROP2(cirrus_fill_notsrc), |
558 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_dst), |
559 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_notdst), |
560 | a5082316 | bellard | }; |
561 | a5082316 | bellard | |
562 | a5082316 | bellard | static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) |
563 | e6e5ad80 | bellard | { |
564 | a5082316 | bellard | unsigned int color; |
565 | a5082316 | bellard | switch (s->cirrus_blt_pixelwidth) {
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566 | a5082316 | bellard | case 1: |
567 | a5082316 | bellard | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; |
568 | a5082316 | bellard | break;
|
569 | a5082316 | bellard | case 2: |
570 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); |
571 | a5082316 | bellard | s->cirrus_blt_fgcol = le16_to_cpu(color); |
572 | a5082316 | bellard | break;
|
573 | a5082316 | bellard | case 3: |
574 | 5fafdf24 | ths | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
575 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); |
576 | a5082316 | bellard | break;
|
577 | a5082316 | bellard | default:
|
578 | a5082316 | bellard | case 4: |
579 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | |
580 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); |
581 | a5082316 | bellard | s->cirrus_blt_fgcol = le32_to_cpu(color); |
582 | a5082316 | bellard | break;
|
583 | e6e5ad80 | bellard | } |
584 | e6e5ad80 | bellard | } |
585 | e6e5ad80 | bellard | |
586 | a5082316 | bellard | static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
587 | e6e5ad80 | bellard | { |
588 | a5082316 | bellard | unsigned int color; |
589 | e6e5ad80 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
590 | e6e5ad80 | bellard | case 1: |
591 | a5082316 | bellard | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
592 | a5082316 | bellard | break;
|
593 | e6e5ad80 | bellard | case 2: |
594 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); |
595 | a5082316 | bellard | s->cirrus_blt_bgcol = le16_to_cpu(color); |
596 | a5082316 | bellard | break;
|
597 | e6e5ad80 | bellard | case 3: |
598 | 5fafdf24 | ths | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
599 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); |
600 | a5082316 | bellard | break;
|
601 | e6e5ad80 | bellard | default:
|
602 | a5082316 | bellard | case 4: |
603 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | |
604 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); |
605 | a5082316 | bellard | s->cirrus_blt_bgcol = le32_to_cpu(color); |
606 | a5082316 | bellard | break;
|
607 | e6e5ad80 | bellard | } |
608 | e6e5ad80 | bellard | } |
609 | e6e5ad80 | bellard | |
610 | e6e5ad80 | bellard | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
611 | e6e5ad80 | bellard | int off_pitch, int bytesperline, |
612 | e6e5ad80 | bellard | int lines)
|
613 | e6e5ad80 | bellard | { |
614 | e6e5ad80 | bellard | int y;
|
615 | e6e5ad80 | bellard | int off_cur;
|
616 | e6e5ad80 | bellard | int off_cur_end;
|
617 | e6e5ad80 | bellard | |
618 | e6e5ad80 | bellard | for (y = 0; y < lines; y++) { |
619 | e6e5ad80 | bellard | off_cur = off_begin; |
620 | b2eb849d | aurel32 | off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; |
621 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); |
622 | e6e5ad80 | bellard | off_begin += off_pitch; |
623 | e6e5ad80 | bellard | } |
624 | e6e5ad80 | bellard | } |
625 | e6e5ad80 | bellard | |
626 | e6e5ad80 | bellard | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
627 | e6e5ad80 | bellard | const uint8_t * src)
|
628 | e6e5ad80 | bellard | { |
629 | e6e5ad80 | bellard | uint8_t *dst; |
630 | e6e5ad80 | bellard | |
631 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); |
632 | b2eb849d | aurel32 | |
633 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
634 | b2eb849d | aurel32 | return 0; |
635 | b2eb849d | aurel32 | |
636 | e69390ce | bellard | (*s->cirrus_rop) (s, dst, src, |
637 | 5fafdf24 | ths | s->cirrus_blt_dstpitch, 0,
|
638 | e69390ce | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
639 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
640 | e69390ce | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
641 | e69390ce | bellard | s->cirrus_blt_height); |
642 | e6e5ad80 | bellard | return 1; |
643 | e6e5ad80 | bellard | } |
644 | e6e5ad80 | bellard | |
645 | a21ae81d | bellard | /* fill */
|
646 | a21ae81d | bellard | |
647 | a5082316 | bellard | static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
648 | a21ae81d | bellard | { |
649 | a5082316 | bellard | cirrus_fill_t rop_func; |
650 | a21ae81d | bellard | |
651 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
652 | b2eb849d | aurel32 | return 0; |
653 | a5082316 | bellard | rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
654 | 4e12cd94 | Avi Kivity | rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
655 | a5082316 | bellard | s->cirrus_blt_dstpitch, |
656 | a5082316 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
657 | a21ae81d | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
658 | a21ae81d | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
659 | a21ae81d | bellard | s->cirrus_blt_height); |
660 | a21ae81d | bellard | cirrus_bitblt_reset(s); |
661 | a21ae81d | bellard | return 1; |
662 | a21ae81d | bellard | } |
663 | a21ae81d | bellard | |
664 | e6e5ad80 | bellard | /***************************************
|
665 | e6e5ad80 | bellard | *
|
666 | e6e5ad80 | bellard | * bitblt (video-to-video)
|
667 | e6e5ad80 | bellard | *
|
668 | e6e5ad80 | bellard | ***************************************/
|
669 | e6e5ad80 | bellard | |
670 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
671 | e6e5ad80 | bellard | { |
672 | e6e5ad80 | bellard | return cirrus_bitblt_common_patterncopy(s,
|
673 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
|
674 | b2eb849d | aurel32 | s->cirrus_addr_mask)); |
675 | e6e5ad80 | bellard | } |
676 | e6e5ad80 | bellard | |
677 | 24236869 | bellard | static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) |
678 | e6e5ad80 | bellard | { |
679 | 78935c4a | Aurelien Jarno | int sx = 0, sy = 0; |
680 | 78935c4a | Aurelien Jarno | int dx = 0, dy = 0; |
681 | 78935c4a | Aurelien Jarno | int depth = 0; |
682 | 24236869 | bellard | int notify = 0; |
683 | 24236869 | bellard | |
684 | 92d675d1 | Aurelien Jarno | /* make sure to only copy if it's a plain copy ROP */
|
685 | 92d675d1 | Aurelien Jarno | if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
|
686 | 92d675d1 | Aurelien Jarno | *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { |
687 | 24236869 | bellard | |
688 | 92d675d1 | Aurelien Jarno | int width, height;
|
689 | 92d675d1 | Aurelien Jarno | |
690 | 92d675d1 | Aurelien Jarno | depth = s->vga.get_bpp(&s->vga) / 8;
|
691 | 92d675d1 | Aurelien Jarno | s->vga.get_resolution(&s->vga, &width, &height); |
692 | 92d675d1 | Aurelien Jarno | |
693 | 92d675d1 | Aurelien Jarno | /* extra x, y */
|
694 | 92d675d1 | Aurelien Jarno | sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; |
695 | 92d675d1 | Aurelien Jarno | sy = (src / ABS(s->cirrus_blt_srcpitch)); |
696 | 92d675d1 | Aurelien Jarno | dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; |
697 | 92d675d1 | Aurelien Jarno | dy = (dst / ABS(s->cirrus_blt_dstpitch)); |
698 | 24236869 | bellard | |
699 | 92d675d1 | Aurelien Jarno | /* normalize width */
|
700 | 92d675d1 | Aurelien Jarno | w /= depth; |
701 | 24236869 | bellard | |
702 | 92d675d1 | Aurelien Jarno | /* if we're doing a backward copy, we have to adjust
|
703 | 92d675d1 | Aurelien Jarno | our x/y to be the upper left corner (instead of the lower
|
704 | 92d675d1 | Aurelien Jarno | right corner) */
|
705 | 92d675d1 | Aurelien Jarno | if (s->cirrus_blt_dstpitch < 0) { |
706 | 92d675d1 | Aurelien Jarno | sx -= (s->cirrus_blt_width / depth) - 1;
|
707 | 92d675d1 | Aurelien Jarno | dx -= (s->cirrus_blt_width / depth) - 1;
|
708 | 92d675d1 | Aurelien Jarno | sy -= s->cirrus_blt_height - 1;
|
709 | 92d675d1 | Aurelien Jarno | dy -= s->cirrus_blt_height - 1;
|
710 | 92d675d1 | Aurelien Jarno | } |
711 | 92d675d1 | Aurelien Jarno | |
712 | 92d675d1 | Aurelien Jarno | /* are we in the visible portion of memory? */
|
713 | 92d675d1 | Aurelien Jarno | if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && |
714 | 92d675d1 | Aurelien Jarno | (sx + w) <= width && (sy + h) <= height && |
715 | 92d675d1 | Aurelien Jarno | (dx + w) <= width && (dy + h) <= height) { |
716 | 92d675d1 | Aurelien Jarno | notify = 1;
|
717 | 92d675d1 | Aurelien Jarno | } |
718 | 92d675d1 | Aurelien Jarno | } |
719 | 24236869 | bellard | |
720 | 24236869 | bellard | /* we have to flush all pending changes so that the copy
|
721 | 24236869 | bellard | is generated at the appropriate moment in time */
|
722 | 24236869 | bellard | if (notify)
|
723 | 24236869 | bellard | vga_hw_update(); |
724 | 24236869 | bellard | |
725 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop) (s, s->vga.vram_ptr + |
726 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
727 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + |
728 | b2eb849d | aurel32 | (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), |
729 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
730 | e6e5ad80 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
731 | 24236869 | bellard | |
732 | c78f7137 | Gerd Hoffmann | if (notify) {
|
733 | c78f7137 | Gerd Hoffmann | qemu_console_copy(s->vga.con, |
734 | 38334f76 | balrog | sx, sy, dx, dy, |
735 | 38334f76 | balrog | s->cirrus_blt_width / depth, |
736 | 38334f76 | balrog | s->cirrus_blt_height); |
737 | c78f7137 | Gerd Hoffmann | } |
738 | 24236869 | bellard | |
739 | 24236869 | bellard | /* we don't have to notify the display that this portion has
|
740 | 38334f76 | balrog | changed since qemu_console_copy implies this */
|
741 | 24236869 | bellard | |
742 | 31c05501 | aliguori | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
743 | 31c05501 | aliguori | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
744 | 31c05501 | aliguori | s->cirrus_blt_height); |
745 | 24236869 | bellard | } |
746 | 24236869 | bellard | |
747 | 24236869 | bellard | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
748 | 24236869 | bellard | { |
749 | 65d35a09 | aurel32 | if (BLTUNSAFE(s))
|
750 | 65d35a09 | aurel32 | return 0; |
751 | 65d35a09 | aurel32 | |
752 | 4e12cd94 | Avi Kivity | cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, |
753 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcaddr - s->vga.start_addr, |
754 | 7d957bd8 | aliguori | s->cirrus_blt_width, s->cirrus_blt_height); |
755 | 24236869 | bellard | |
756 | e6e5ad80 | bellard | return 1; |
757 | e6e5ad80 | bellard | } |
758 | e6e5ad80 | bellard | |
759 | e6e5ad80 | bellard | /***************************************
|
760 | e6e5ad80 | bellard | *
|
761 | e6e5ad80 | bellard | * bitblt (cpu-to-video)
|
762 | e6e5ad80 | bellard | *
|
763 | e6e5ad80 | bellard | ***************************************/
|
764 | e6e5ad80 | bellard | |
765 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
766 | e6e5ad80 | bellard | { |
767 | e6e5ad80 | bellard | int copy_count;
|
768 | a5082316 | bellard | uint8_t *end_ptr; |
769 | 3b46e624 | ths | |
770 | e6e5ad80 | bellard | if (s->cirrus_srccounter > 0) { |
771 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
772 | a5082316 | bellard | cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); |
773 | a5082316 | bellard | the_end:
|
774 | a5082316 | bellard | s->cirrus_srccounter = 0;
|
775 | a5082316 | bellard | cirrus_bitblt_reset(s); |
776 | a5082316 | bellard | } else {
|
777 | a5082316 | bellard | /* at least one scan line */
|
778 | a5082316 | bellard | do {
|
779 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop)(s, s->vga.vram_ptr + |
780 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
781 | b2eb849d | aurel32 | s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); |
782 | a5082316 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
783 | a5082316 | bellard | s->cirrus_blt_width, 1);
|
784 | a5082316 | bellard | s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; |
785 | a5082316 | bellard | s->cirrus_srccounter -= s->cirrus_blt_srcpitch; |
786 | a5082316 | bellard | if (s->cirrus_srccounter <= 0) |
787 | a5082316 | bellard | goto the_end;
|
788 | 66a0a2cb | Dong Xu Wang | /* more bytes than needed can be transferred because of
|
789 | a5082316 | bellard | word alignment, so we keep them for the next line */
|
790 | a5082316 | bellard | /* XXX: keep alignment to speed up transfer */
|
791 | a5082316 | bellard | end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
792 | a5082316 | bellard | copy_count = s->cirrus_srcptr_end - end_ptr; |
793 | a5082316 | bellard | memmove(s->cirrus_bltbuf, end_ptr, copy_count); |
794 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; |
795 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
796 | a5082316 | bellard | } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
|
797 | a5082316 | bellard | } |
798 | e6e5ad80 | bellard | } |
799 | e6e5ad80 | bellard | } |
800 | e6e5ad80 | bellard | |
801 | e6e5ad80 | bellard | /***************************************
|
802 | e6e5ad80 | bellard | *
|
803 | e6e5ad80 | bellard | * bitblt wrapper
|
804 | e6e5ad80 | bellard | *
|
805 | e6e5ad80 | bellard | ***************************************/
|
806 | e6e5ad80 | bellard | |
807 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s) |
808 | e6e5ad80 | bellard | { |
809 | f8b237af | aliguori | int need_update;
|
810 | f8b237af | aliguori | |
811 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] &=
|
812 | e6e5ad80 | bellard | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
813 | f8b237af | aliguori | need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
|
814 | f8b237af | aliguori | || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
|
815 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
816 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
817 | e6e5ad80 | bellard | s->cirrus_srccounter = 0;
|
818 | f8b237af | aliguori | if (!need_update)
|
819 | f8b237af | aliguori | return;
|
820 | 8926b517 | bellard | cirrus_update_memory_access(s); |
821 | e6e5ad80 | bellard | } |
822 | e6e5ad80 | bellard | |
823 | e6e5ad80 | bellard | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
824 | e6e5ad80 | bellard | { |
825 | a5082316 | bellard | int w;
|
826 | a5082316 | bellard | |
827 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
828 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
829 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
830 | e6e5ad80 | bellard | |
831 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
832 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
833 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8;
|
834 | e6e5ad80 | bellard | } else {
|
835 | b30d4608 | bellard | /* XXX: check for 24 bpp */
|
836 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
837 | e6e5ad80 | bellard | } |
838 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
839 | e6e5ad80 | bellard | } else {
|
840 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
841 | a5082316 | bellard | w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
842 | 5fafdf24 | ths | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
|
843 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
844 | a5082316 | bellard | else
|
845 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 7) >> 3); |
846 | e6e5ad80 | bellard | } else {
|
847 | c9c0eae8 | bellard | /* always align input size to 32 bits */
|
848 | c9c0eae8 | bellard | s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; |
849 | e6e5ad80 | bellard | } |
850 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
851 | e6e5ad80 | bellard | } |
852 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf; |
853 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
854 | 8926b517 | bellard | cirrus_update_memory_access(s); |
855 | e6e5ad80 | bellard | return 1; |
856 | e6e5ad80 | bellard | } |
857 | e6e5ad80 | bellard | |
858 | e6e5ad80 | bellard | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
859 | e6e5ad80 | bellard | { |
860 | e6e5ad80 | bellard | /* XXX */
|
861 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
862 | e6e5ad80 | bellard | printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
863 | e6e5ad80 | bellard | #endif
|
864 | e6e5ad80 | bellard | return 0; |
865 | e6e5ad80 | bellard | } |
866 | e6e5ad80 | bellard | |
867 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
868 | e6e5ad80 | bellard | { |
869 | e6e5ad80 | bellard | int ret;
|
870 | e6e5ad80 | bellard | |
871 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
872 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_patterncopy(s); |
873 | e6e5ad80 | bellard | } else {
|
874 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_copy(s); |
875 | e6e5ad80 | bellard | } |
876 | e6e5ad80 | bellard | if (ret)
|
877 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
878 | e6e5ad80 | bellard | return ret;
|
879 | e6e5ad80 | bellard | } |
880 | e6e5ad80 | bellard | |
881 | e6e5ad80 | bellard | static void cirrus_bitblt_start(CirrusVGAState * s) |
882 | e6e5ad80 | bellard | { |
883 | e6e5ad80 | bellard | uint8_t blt_rop; |
884 | e6e5ad80 | bellard | |
885 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
|
886 | a5082316 | bellard | |
887 | 4e12cd94 | Avi Kivity | s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; |
888 | 4e12cd94 | Avi Kivity | s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; |
889 | 4e12cd94 | Avi Kivity | s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); |
890 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); |
891 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr = |
892 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); |
893 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr = |
894 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); |
895 | 4e12cd94 | Avi Kivity | s->cirrus_blt_mode = s->vga.gr[0x30];
|
896 | 4e12cd94 | Avi Kivity | s->cirrus_blt_modeext = s->vga.gr[0x33];
|
897 | 4e12cd94 | Avi Kivity | blt_rop = s->vga.gr[0x32];
|
898 | e6e5ad80 | bellard | |
899 | a21ae81d | bellard | #ifdef DEBUG_BITBLT
|
900 | 0b74ed78 | bellard | printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
|
901 | 5fafdf24 | ths | blt_rop, |
902 | a21ae81d | bellard | s->cirrus_blt_mode, |
903 | a5082316 | bellard | s->cirrus_blt_modeext, |
904 | a21ae81d | bellard | s->cirrus_blt_width, |
905 | a21ae81d | bellard | s->cirrus_blt_height, |
906 | a21ae81d | bellard | s->cirrus_blt_dstpitch, |
907 | a21ae81d | bellard | s->cirrus_blt_srcpitch, |
908 | a21ae81d | bellard | s->cirrus_blt_dstaddr, |
909 | a5082316 | bellard | s->cirrus_blt_srcaddr, |
910 | 4e12cd94 | Avi Kivity | s->vga.gr[0x2f]);
|
911 | a21ae81d | bellard | #endif
|
912 | a21ae81d | bellard | |
913 | e6e5ad80 | bellard | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
914 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH8:
|
915 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 1;
|
916 | e6e5ad80 | bellard | break;
|
917 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH16:
|
918 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 2;
|
919 | e6e5ad80 | bellard | break;
|
920 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH24:
|
921 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 3;
|
922 | e6e5ad80 | bellard | break;
|
923 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH32:
|
924 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 4;
|
925 | e6e5ad80 | bellard | break;
|
926 | e6e5ad80 | bellard | default:
|
927 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
928 | e6e5ad80 | bellard | printf("cirrus: bitblt - pixel width is unknown\n");
|
929 | e6e5ad80 | bellard | #endif
|
930 | e6e5ad80 | bellard | goto bitblt_ignore;
|
931 | e6e5ad80 | bellard | } |
932 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
933 | e6e5ad80 | bellard | |
934 | e6e5ad80 | bellard | if ((s->
|
935 | e6e5ad80 | bellard | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
936 | e6e5ad80 | bellard | CIRRUS_BLTMODE_MEMSYSDEST)) |
937 | e6e5ad80 | bellard | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
938 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
939 | e6e5ad80 | bellard | printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
940 | e6e5ad80 | bellard | #endif
|
941 | e6e5ad80 | bellard | goto bitblt_ignore;
|
942 | e6e5ad80 | bellard | } |
943 | e6e5ad80 | bellard | |
944 | a5082316 | bellard | if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
|
945 | 5fafdf24 | ths | (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
946 | a21ae81d | bellard | CIRRUS_BLTMODE_TRANSPARENTCOMP | |
947 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY | |
948 | 5fafdf24 | ths | CIRRUS_BLTMODE_COLOREXPAND)) == |
949 | a21ae81d | bellard | (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { |
950 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
951 | a5082316 | bellard | cirrus_bitblt_solidfill(s, blt_rop); |
952 | e6e5ad80 | bellard | } else {
|
953 | 5fafdf24 | ths | if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
|
954 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY)) == |
955 | a5082316 | bellard | CIRRUS_BLTMODE_COLOREXPAND) { |
956 | a5082316 | bellard | |
957 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
958 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
959 | 4c8732d7 | bellard | cirrus_bitblt_bgcol(s); |
960 | b30d4608 | bellard | else
|
961 | 4c8732d7 | bellard | cirrus_bitblt_fgcol(s); |
962 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
963 | a5082316 | bellard | } else {
|
964 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
965 | a5082316 | bellard | cirrus_bitblt_bgcol(s); |
966 | a5082316 | bellard | s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
967 | a5082316 | bellard | } |
968 | e69390ce | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
969 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
970 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
971 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
972 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
973 | b30d4608 | bellard | else
|
974 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
975 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
976 | b30d4608 | bellard | } else {
|
977 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
978 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
979 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
980 | b30d4608 | bellard | } |
981 | b30d4608 | bellard | } else {
|
982 | b30d4608 | bellard | s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
983 | b30d4608 | bellard | } |
984 | a21ae81d | bellard | } else {
|
985 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
986 | 96cf2df8 | ths | if (s->cirrus_blt_pixelwidth > 2) { |
987 | 96cf2df8 | ths | printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
|
988 | 96cf2df8 | ths | goto bitblt_ignore;
|
989 | 96cf2df8 | ths | } |
990 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
991 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
992 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
993 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
994 | 96cf2df8 | ths | } else {
|
995 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
996 | 96cf2df8 | ths | } |
997 | 96cf2df8 | ths | } else {
|
998 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
999 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
1000 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
1001 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; |
1002 | 96cf2df8 | ths | } else {
|
1003 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; |
1004 | 96cf2df8 | ths | } |
1005 | 96cf2df8 | ths | } |
1006 | 96cf2df8 | ths | } |
1007 | a21ae81d | bellard | // setup bitblt engine.
|
1008 | a21ae81d | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
1009 | a21ae81d | bellard | if (!cirrus_bitblt_cputovideo(s))
|
1010 | a21ae81d | bellard | goto bitblt_ignore;
|
1011 | a21ae81d | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
1012 | a21ae81d | bellard | if (!cirrus_bitblt_videotocpu(s))
|
1013 | a21ae81d | bellard | goto bitblt_ignore;
|
1014 | a21ae81d | bellard | } else {
|
1015 | a21ae81d | bellard | if (!cirrus_bitblt_videotovideo(s))
|
1016 | a21ae81d | bellard | goto bitblt_ignore;
|
1017 | a21ae81d | bellard | } |
1018 | e6e5ad80 | bellard | } |
1019 | e6e5ad80 | bellard | return;
|
1020 | e6e5ad80 | bellard | bitblt_ignore:;
|
1021 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1022 | e6e5ad80 | bellard | } |
1023 | e6e5ad80 | bellard | |
1024 | e6e5ad80 | bellard | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
1025 | e6e5ad80 | bellard | { |
1026 | e6e5ad80 | bellard | unsigned old_value;
|
1027 | e6e5ad80 | bellard | |
1028 | 4e12cd94 | Avi Kivity | old_value = s->vga.gr[0x31];
|
1029 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] = reg_value;
|
1030 | e6e5ad80 | bellard | |
1031 | e6e5ad80 | bellard | if (((old_value & CIRRUS_BLT_RESET) != 0) && |
1032 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
1033 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1034 | e6e5ad80 | bellard | } else if (((old_value & CIRRUS_BLT_START) == 0) && |
1035 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_START) != 0)) {
|
1036 | e6e5ad80 | bellard | cirrus_bitblt_start(s); |
1037 | e6e5ad80 | bellard | } |
1038 | e6e5ad80 | bellard | } |
1039 | e6e5ad80 | bellard | |
1040 | e6e5ad80 | bellard | |
1041 | e6e5ad80 | bellard | /***************************************
|
1042 | e6e5ad80 | bellard | *
|
1043 | e6e5ad80 | bellard | * basic parameters
|
1044 | e6e5ad80 | bellard | *
|
1045 | e6e5ad80 | bellard | ***************************************/
|
1046 | e6e5ad80 | bellard | |
1047 | a4a2f59c | Juan Quintela | static void cirrus_get_offsets(VGACommonState *s1, |
1048 | 83acc96b | bellard | uint32_t *pline_offset, |
1049 | 83acc96b | bellard | uint32_t *pstart_addr, |
1050 | 83acc96b | bellard | uint32_t *pline_compare) |
1051 | e6e5ad80 | bellard | { |
1052 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1053 | 83acc96b | bellard | uint32_t start_addr, line_offset, line_compare; |
1054 | e6e5ad80 | bellard | |
1055 | 4e12cd94 | Avi Kivity | line_offset = s->vga.cr[0x13]
|
1056 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x10) << 4); |
1057 | e6e5ad80 | bellard | line_offset <<= 3;
|
1058 | e6e5ad80 | bellard | *pline_offset = line_offset; |
1059 | e6e5ad80 | bellard | |
1060 | 4e12cd94 | Avi Kivity | start_addr = (s->vga.cr[0x0c] << 8) |
1061 | 4e12cd94 | Avi Kivity | | s->vga.cr[0x0d]
|
1062 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x01) << 16) |
1063 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x0c) << 15) |
1064 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1d] & 0x80) << 12); |
1065 | e6e5ad80 | bellard | *pstart_addr = start_addr; |
1066 | 83acc96b | bellard | |
1067 | 4e12cd94 | Avi Kivity | line_compare = s->vga.cr[0x18] |
|
1068 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x07] & 0x10) << 4) | |
1069 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x09] & 0x40) << 3); |
1070 | 83acc96b | bellard | *pline_compare = line_compare; |
1071 | e6e5ad80 | bellard | } |
1072 | e6e5ad80 | bellard | |
1073 | e6e5ad80 | bellard | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
1074 | e6e5ad80 | bellard | { |
1075 | e6e5ad80 | bellard | uint32_t ret = 16;
|
1076 | e6e5ad80 | bellard | |
1077 | e6e5ad80 | bellard | switch (s->cirrus_hidden_dac_data & 0xf) { |
1078 | e6e5ad80 | bellard | case 0: |
1079 | e6e5ad80 | bellard | ret = 15;
|
1080 | e6e5ad80 | bellard | break; /* Sierra HiColor */ |
1081 | e6e5ad80 | bellard | case 1: |
1082 | e6e5ad80 | bellard | ret = 16;
|
1083 | e6e5ad80 | bellard | break; /* XGA HiColor */ |
1084 | e6e5ad80 | bellard | default:
|
1085 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1086 | e6e5ad80 | bellard | printf("cirrus: invalid DAC value %x in 16bpp\n",
|
1087 | e6e5ad80 | bellard | (s->cirrus_hidden_dac_data & 0xf));
|
1088 | e6e5ad80 | bellard | #endif
|
1089 | e6e5ad80 | bellard | ret = 15; /* XXX */ |
1090 | e6e5ad80 | bellard | break;
|
1091 | e6e5ad80 | bellard | } |
1092 | e6e5ad80 | bellard | return ret;
|
1093 | e6e5ad80 | bellard | } |
1094 | e6e5ad80 | bellard | |
1095 | a4a2f59c | Juan Quintela | static int cirrus_get_bpp(VGACommonState *s1) |
1096 | e6e5ad80 | bellard | { |
1097 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1098 | e6e5ad80 | bellard | uint32_t ret = 8;
|
1099 | e6e5ad80 | bellard | |
1100 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) != 0) { |
1101 | e6e5ad80 | bellard | /* Cirrus SVGA */
|
1102 | 4e12cd94 | Avi Kivity | switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
1103 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_8:
|
1104 | e6e5ad80 | bellard | ret = 8;
|
1105 | e6e5ad80 | bellard | break;
|
1106 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
1107 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1108 | e6e5ad80 | bellard | break;
|
1109 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_24:
|
1110 | e6e5ad80 | bellard | ret = 24;
|
1111 | e6e5ad80 | bellard | break;
|
1112 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16:
|
1113 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1114 | e6e5ad80 | bellard | break;
|
1115 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_32:
|
1116 | e6e5ad80 | bellard | ret = 32;
|
1117 | e6e5ad80 | bellard | break;
|
1118 | e6e5ad80 | bellard | default:
|
1119 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1120 | 4e12cd94 | Avi Kivity | printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); |
1121 | e6e5ad80 | bellard | #endif
|
1122 | e6e5ad80 | bellard | ret = 8;
|
1123 | e6e5ad80 | bellard | break;
|
1124 | e6e5ad80 | bellard | } |
1125 | e6e5ad80 | bellard | } else {
|
1126 | e6e5ad80 | bellard | /* VGA */
|
1127 | aeb3c85f | bellard | ret = 0;
|
1128 | e6e5ad80 | bellard | } |
1129 | e6e5ad80 | bellard | |
1130 | e6e5ad80 | bellard | return ret;
|
1131 | e6e5ad80 | bellard | } |
1132 | e6e5ad80 | bellard | |
1133 | a4a2f59c | Juan Quintela | static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
1134 | 78e127ef | bellard | { |
1135 | 78e127ef | bellard | int width, height;
|
1136 | 3b46e624 | ths | |
1137 | 78e127ef | bellard | width = (s->cr[0x01] + 1) * 8; |
1138 | 5fafdf24 | ths | height = s->cr[0x12] |
|
1139 | 5fafdf24 | ths | ((s->cr[0x07] & 0x02) << 7) | |
1140 | 78e127ef | bellard | ((s->cr[0x07] & 0x40) << 3); |
1141 | 78e127ef | bellard | height = (height + 1);
|
1142 | 78e127ef | bellard | /* interlace support */
|
1143 | 78e127ef | bellard | if (s->cr[0x1a] & 0x01) |
1144 | 78e127ef | bellard | height = height * 2;
|
1145 | 78e127ef | bellard | *pwidth = width; |
1146 | 78e127ef | bellard | *pheight = height; |
1147 | 78e127ef | bellard | } |
1148 | 78e127ef | bellard | |
1149 | e6e5ad80 | bellard | /***************************************
|
1150 | e6e5ad80 | bellard | *
|
1151 | e6e5ad80 | bellard | * bank memory
|
1152 | e6e5ad80 | bellard | *
|
1153 | e6e5ad80 | bellard | ***************************************/
|
1154 | e6e5ad80 | bellard | |
1155 | e6e5ad80 | bellard | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1156 | e6e5ad80 | bellard | { |
1157 | e6e5ad80 | bellard | unsigned offset;
|
1158 | e6e5ad80 | bellard | unsigned limit;
|
1159 | e6e5ad80 | bellard | |
1160 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ |
1161 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09 + bank_index];
|
1162 | e6e5ad80 | bellard | else /* single bank */ |
1163 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09];
|
1164 | e6e5ad80 | bellard | |
1165 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x20) != 0) |
1166 | e6e5ad80 | bellard | offset <<= 14;
|
1167 | e6e5ad80 | bellard | else
|
1168 | e6e5ad80 | bellard | offset <<= 12;
|
1169 | e6e5ad80 | bellard | |
1170 | e3a4e4b6 | bellard | if (s->real_vram_size <= offset)
|
1171 | e6e5ad80 | bellard | limit = 0;
|
1172 | e6e5ad80 | bellard | else
|
1173 | e3a4e4b6 | bellard | limit = s->real_vram_size - offset; |
1174 | e6e5ad80 | bellard | |
1175 | 4e12cd94 | Avi Kivity | if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1176 | e6e5ad80 | bellard | if (limit > 0x8000) { |
1177 | e6e5ad80 | bellard | offset += 0x8000;
|
1178 | e6e5ad80 | bellard | limit -= 0x8000;
|
1179 | e6e5ad80 | bellard | } else {
|
1180 | e6e5ad80 | bellard | limit = 0;
|
1181 | e6e5ad80 | bellard | } |
1182 | e6e5ad80 | bellard | } |
1183 | e6e5ad80 | bellard | |
1184 | e6e5ad80 | bellard | if (limit > 0) { |
1185 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = offset; |
1186 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = limit; |
1187 | e6e5ad80 | bellard | } else {
|
1188 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = 0;
|
1189 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = 0;
|
1190 | e6e5ad80 | bellard | } |
1191 | e6e5ad80 | bellard | } |
1192 | e6e5ad80 | bellard | |
1193 | e6e5ad80 | bellard | /***************************************
|
1194 | e6e5ad80 | bellard | *
|
1195 | e6e5ad80 | bellard | * I/O access between 0x3c4-0x3c5
|
1196 | e6e5ad80 | bellard | *
|
1197 | e6e5ad80 | bellard | ***************************************/
|
1198 | e6e5ad80 | bellard | |
1199 | 8a82c322 | Juan Quintela | static int cirrus_vga_read_sr(CirrusVGAState * s) |
1200 | e6e5ad80 | bellard | { |
1201 | 8a82c322 | Juan Quintela | switch (s->vga.sr_index) {
|
1202 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1203 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1204 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1205 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1206 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1207 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1208 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1209 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1210 | e6e5ad80 | bellard | case 0x10: |
1211 | e6e5ad80 | bellard | case 0x30: |
1212 | e6e5ad80 | bellard | case 0x50: |
1213 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1214 | e6e5ad80 | bellard | case 0x90: |
1215 | e6e5ad80 | bellard | case 0xb0: |
1216 | e6e5ad80 | bellard | case 0xd0: |
1217 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1218 | 8a82c322 | Juan Quintela | return s->vga.sr[0x10]; |
1219 | e6e5ad80 | bellard | case 0x11: |
1220 | e6e5ad80 | bellard | case 0x31: |
1221 | e6e5ad80 | bellard | case 0x51: |
1222 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1223 | e6e5ad80 | bellard | case 0x91: |
1224 | e6e5ad80 | bellard | case 0xb1: |
1225 | e6e5ad80 | bellard | case 0xd1: |
1226 | a5082316 | bellard | case 0xf1: // Graphics Cursor Y |
1227 | 8a82c322 | Juan Quintela | return s->vga.sr[0x11]; |
1228 | aeb3c85f | bellard | case 0x05: // ??? |
1229 | aeb3c85f | bellard | case 0x07: // Extended Sequencer Mode |
1230 | aeb3c85f | bellard | case 0x08: // EEPROM Control |
1231 | aeb3c85f | bellard | case 0x09: // Scratch Register 0 |
1232 | aeb3c85f | bellard | case 0x0a: // Scratch Register 1 |
1233 | aeb3c85f | bellard | case 0x0b: // VCLK 0 |
1234 | aeb3c85f | bellard | case 0x0c: // VCLK 1 |
1235 | aeb3c85f | bellard | case 0x0d: // VCLK 2 |
1236 | aeb3c85f | bellard | case 0x0e: // VCLK 3 |
1237 | aeb3c85f | bellard | case 0x0f: // DRAM Control |
1238 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1239 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1240 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1241 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1242 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1243 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1244 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1245 | e6e5ad80 | bellard | case 0x19: // Signal Generator Result |
1246 | e6e5ad80 | bellard | case 0x1a: // Signal Generator Result |
1247 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1248 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1249 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1250 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1251 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1252 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1253 | 8a82c322 | Juan Quintela | printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
|
1254 | e6e5ad80 | bellard | #endif
|
1255 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1256 | e6e5ad80 | bellard | default:
|
1257 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1258 | 8a82c322 | Juan Quintela | printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
|
1259 | e6e5ad80 | bellard | #endif
|
1260 | 8a82c322 | Juan Quintela | return 0xff; |
1261 | e6e5ad80 | bellard | break;
|
1262 | e6e5ad80 | bellard | } |
1263 | e6e5ad80 | bellard | } |
1264 | e6e5ad80 | bellard | |
1265 | 31c63201 | Juan Quintela | static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
1266 | e6e5ad80 | bellard | { |
1267 | 31c63201 | Juan Quintela | switch (s->vga.sr_index) {
|
1268 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1269 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1270 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1271 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1272 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1273 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
1274 | 31c63201 | Juan Quintela | if (s->vga.sr_index == 1) |
1275 | 31c63201 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1276 | 31c63201 | Juan Quintela | break;
|
1277 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1278 | 31c63201 | Juan Quintela | val &= 0x17;
|
1279 | 31c63201 | Juan Quintela | if (val == 0x12) { |
1280 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x12;
|
1281 | e6e5ad80 | bellard | } else {
|
1282 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x0f;
|
1283 | e6e5ad80 | bellard | } |
1284 | e6e5ad80 | bellard | break;
|
1285 | e6e5ad80 | bellard | case 0x10: |
1286 | e6e5ad80 | bellard | case 0x30: |
1287 | e6e5ad80 | bellard | case 0x50: |
1288 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1289 | e6e5ad80 | bellard | case 0x90: |
1290 | e6e5ad80 | bellard | case 0xb0: |
1291 | e6e5ad80 | bellard | case 0xd0: |
1292 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1293 | 31c63201 | Juan Quintela | s->vga.sr[0x10] = val;
|
1294 | 31c63201 | Juan Quintela | s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); |
1295 | e6e5ad80 | bellard | break;
|
1296 | e6e5ad80 | bellard | case 0x11: |
1297 | e6e5ad80 | bellard | case 0x31: |
1298 | e6e5ad80 | bellard | case 0x51: |
1299 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1300 | e6e5ad80 | bellard | case 0x91: |
1301 | e6e5ad80 | bellard | case 0xb1: |
1302 | e6e5ad80 | bellard | case 0xd1: |
1303 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1304 | 31c63201 | Juan Quintela | s->vga.sr[0x11] = val;
|
1305 | 31c63201 | Juan Quintela | s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); |
1306 | e6e5ad80 | bellard | break;
|
1307 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1308 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1309 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1310 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1311 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1312 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1313 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1314 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1315 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1316 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1317 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1318 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1319 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1320 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1321 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1322 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1323 | e6e5ad80 | bellard | case 0x19: // Signature Generator Result |
1324 | e6e5ad80 | bellard | case 0x1a: // Signature Generator Result |
1325 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1326 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1327 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1328 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1329 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1330 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val; |
1331 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1332 | e6e5ad80 | bellard | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1333 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1334 | e6e5ad80 | bellard | #endif
|
1335 | e6e5ad80 | bellard | break;
|
1336 | 8926b517 | bellard | case 0x17: // Configuration Readback and Extended Control |
1337 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
|
1338 | 31c63201 | Juan Quintela | | (val & 0xc7);
|
1339 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1340 | 8926b517 | bellard | break;
|
1341 | e6e5ad80 | bellard | default:
|
1342 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1343 | 31c63201 | Juan Quintela | printf("cirrus: outport sr_index %02x, sr_value %02x\n",
|
1344 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1345 | e6e5ad80 | bellard | #endif
|
1346 | e6e5ad80 | bellard | break;
|
1347 | e6e5ad80 | bellard | } |
1348 | e6e5ad80 | bellard | } |
1349 | e6e5ad80 | bellard | |
1350 | e6e5ad80 | bellard | /***************************************
|
1351 | e6e5ad80 | bellard | *
|
1352 | e6e5ad80 | bellard | * I/O access at 0x3c6
|
1353 | e6e5ad80 | bellard | *
|
1354 | e6e5ad80 | bellard | ***************************************/
|
1355 | e6e5ad80 | bellard | |
1356 | 957c9db5 | Juan Quintela | static int cirrus_read_hidden_dac(CirrusVGAState * s) |
1357 | e6e5ad80 | bellard | { |
1358 | a21ae81d | bellard | if (++s->cirrus_hidden_dac_lockindex == 5) { |
1359 | 957c9db5 | Juan Quintela | s->cirrus_hidden_dac_lockindex = 0;
|
1360 | 957c9db5 | Juan Quintela | return s->cirrus_hidden_dac_data;
|
1361 | e6e5ad80 | bellard | } |
1362 | 957c9db5 | Juan Quintela | return 0xff; |
1363 | e6e5ad80 | bellard | } |
1364 | e6e5ad80 | bellard | |
1365 | e6e5ad80 | bellard | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1366 | e6e5ad80 | bellard | { |
1367 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1368 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = reg_value; |
1369 | a21ae81d | bellard | #if defined(DEBUG_CIRRUS)
|
1370 | e6e5ad80 | bellard | printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1371 | e6e5ad80 | bellard | #endif
|
1372 | e6e5ad80 | bellard | } |
1373 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1374 | e6e5ad80 | bellard | } |
1375 | e6e5ad80 | bellard | |
1376 | e6e5ad80 | bellard | /***************************************
|
1377 | e6e5ad80 | bellard | *
|
1378 | e6e5ad80 | bellard | * I/O access at 0x3c9
|
1379 | e6e5ad80 | bellard | *
|
1380 | e6e5ad80 | bellard | ***************************************/
|
1381 | e6e5ad80 | bellard | |
1382 | 5deaeee3 | Juan Quintela | static int cirrus_vga_read_palette(CirrusVGAState * s) |
1383 | e6e5ad80 | bellard | { |
1384 | 5deaeee3 | Juan Quintela | int val;
|
1385 | 5deaeee3 | Juan Quintela | |
1386 | 5deaeee3 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1387 | 5deaeee3 | Juan Quintela | val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + |
1388 | 5deaeee3 | Juan Quintela | s->vga.dac_sub_index]; |
1389 | 5deaeee3 | Juan Quintela | } else {
|
1390 | 5deaeee3 | Juan Quintela | val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
|
1391 | 5deaeee3 | Juan Quintela | } |
1392 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1393 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1394 | 4e12cd94 | Avi Kivity | s->vga.dac_read_index++; |
1395 | e6e5ad80 | bellard | } |
1396 | 5deaeee3 | Juan Quintela | return val;
|
1397 | e6e5ad80 | bellard | } |
1398 | e6e5ad80 | bellard | |
1399 | 86948bb1 | Juan Quintela | static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) |
1400 | e6e5ad80 | bellard | { |
1401 | 4e12cd94 | Avi Kivity | s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; |
1402 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1403 | 86948bb1 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1404 | 86948bb1 | Juan Quintela | memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], |
1405 | 86948bb1 | Juan Quintela | s->vga.dac_cache, 3);
|
1406 | 86948bb1 | Juan Quintela | } else {
|
1407 | 86948bb1 | Juan Quintela | memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); |
1408 | 86948bb1 | Juan Quintela | } |
1409 | a5082316 | bellard | /* XXX update cursor */
|
1410 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1411 | 4e12cd94 | Avi Kivity | s->vga.dac_write_index++; |
1412 | e6e5ad80 | bellard | } |
1413 | e6e5ad80 | bellard | } |
1414 | e6e5ad80 | bellard | |
1415 | e6e5ad80 | bellard | /***************************************
|
1416 | e6e5ad80 | bellard | *
|
1417 | e6e5ad80 | bellard | * I/O access between 0x3ce-0x3cf
|
1418 | e6e5ad80 | bellard | *
|
1419 | e6e5ad80 | bellard | ***************************************/
|
1420 | e6e5ad80 | bellard | |
1421 | f705db9d | Juan Quintela | static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) |
1422 | e6e5ad80 | bellard | { |
1423 | e6e5ad80 | bellard | switch (reg_index) {
|
1424 | aeb3c85f | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1425 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr0;
|
1426 | aeb3c85f | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1427 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr1;
|
1428 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1429 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1430 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1431 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1432 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1433 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1434 | f705db9d | Juan Quintela | return s->vga.gr[s->vga.gr_index];
|
1435 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1436 | e6e5ad80 | bellard | default:
|
1437 | e6e5ad80 | bellard | break;
|
1438 | e6e5ad80 | bellard | } |
1439 | e6e5ad80 | bellard | |
1440 | e6e5ad80 | bellard | if (reg_index < 0x3a) { |
1441 | f705db9d | Juan Quintela | return s->vga.gr[reg_index];
|
1442 | e6e5ad80 | bellard | } else {
|
1443 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1444 | e6e5ad80 | bellard | printf("cirrus: inport gr_index %02x\n", reg_index);
|
1445 | e6e5ad80 | bellard | #endif
|
1446 | f705db9d | Juan Quintela | return 0xff; |
1447 | e6e5ad80 | bellard | } |
1448 | e6e5ad80 | bellard | } |
1449 | e6e5ad80 | bellard | |
1450 | 22286bc6 | Juan Quintela | static void |
1451 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1452 | e6e5ad80 | bellard | { |
1453 | a5082316 | bellard | #if defined(DEBUG_BITBLT) && 0 |
1454 | a5082316 | bellard | printf("gr%02x: %02x\n", reg_index, reg_value);
|
1455 | a5082316 | bellard | #endif
|
1456 | e6e5ad80 | bellard | switch (reg_index) {
|
1457 | e6e5ad80 | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1458 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1459 | aeb3c85f | bellard | s->cirrus_shadow_gr0 = reg_value; |
1460 | 22286bc6 | Juan Quintela | break;
|
1461 | e6e5ad80 | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1462 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1463 | aeb3c85f | bellard | s->cirrus_shadow_gr1 = reg_value; |
1464 | 22286bc6 | Juan Quintela | break;
|
1465 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1466 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1467 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1468 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1469 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1470 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1471 | 22286bc6 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1472 | 22286bc6 | Juan Quintela | break;
|
1473 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1474 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x7f;
|
1475 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1476 | e6e5ad80 | bellard | break;
|
1477 | e6e5ad80 | bellard | case 0x09: // bank offset #0 |
1478 | e6e5ad80 | bellard | case 0x0A: // bank offset #1 |
1479 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1480 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 0);
|
1481 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 1);
|
1482 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1483 | 8926b517 | bellard | break;
|
1484 | e6e5ad80 | bellard | case 0x0B: |
1485 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1486 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 0);
|
1487 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 1);
|
1488 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1489 | e6e5ad80 | bellard | break;
|
1490 | e6e5ad80 | bellard | case 0x10: // BGCOLOR 0x0000ff00 |
1491 | e6e5ad80 | bellard | case 0x11: // FGCOLOR 0x0000ff00 |
1492 | e6e5ad80 | bellard | case 0x12: // BGCOLOR 0x00ff0000 |
1493 | e6e5ad80 | bellard | case 0x13: // FGCOLOR 0x00ff0000 |
1494 | e6e5ad80 | bellard | case 0x14: // BGCOLOR 0xff000000 |
1495 | e6e5ad80 | bellard | case 0x15: // FGCOLOR 0xff000000 |
1496 | e6e5ad80 | bellard | case 0x20: // BLT WIDTH 0x0000ff |
1497 | e6e5ad80 | bellard | case 0x22: // BLT HEIGHT 0x0000ff |
1498 | e6e5ad80 | bellard | case 0x24: // BLT DEST PITCH 0x0000ff |
1499 | e6e5ad80 | bellard | case 0x26: // BLT SRC PITCH 0x0000ff |
1500 | e6e5ad80 | bellard | case 0x28: // BLT DEST ADDR 0x0000ff |
1501 | e6e5ad80 | bellard | case 0x29: // BLT DEST ADDR 0x00ff00 |
1502 | e6e5ad80 | bellard | case 0x2c: // BLT SRC ADDR 0x0000ff |
1503 | e6e5ad80 | bellard | case 0x2d: // BLT SRC ADDR 0x00ff00 |
1504 | a5082316 | bellard | case 0x2f: // BLT WRITEMASK |
1505 | e6e5ad80 | bellard | case 0x30: // BLT MODE |
1506 | e6e5ad80 | bellard | case 0x32: // RASTER OP |
1507 | a21ae81d | bellard | case 0x33: // BLT MODEEXT |
1508 | e6e5ad80 | bellard | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1509 | e6e5ad80 | bellard | case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1510 | e6e5ad80 | bellard | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1511 | e6e5ad80 | bellard | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1512 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1513 | e6e5ad80 | bellard | break;
|
1514 | e6e5ad80 | bellard | case 0x21: // BLT WIDTH 0x001f00 |
1515 | e6e5ad80 | bellard | case 0x23: // BLT HEIGHT 0x001f00 |
1516 | e6e5ad80 | bellard | case 0x25: // BLT DEST PITCH 0x001f00 |
1517 | e6e5ad80 | bellard | case 0x27: // BLT SRC PITCH 0x001f00 |
1518 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x1f;
|
1519 | e6e5ad80 | bellard | break;
|
1520 | e6e5ad80 | bellard | case 0x2a: // BLT DEST ADDR 0x3f0000 |
1521 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1522 | a5082316 | bellard | /* if auto start mode, starts bit blt now */
|
1523 | 4e12cd94 | Avi Kivity | if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
1524 | a5082316 | bellard | cirrus_bitblt_start(s); |
1525 | a5082316 | bellard | } |
1526 | a5082316 | bellard | break;
|
1527 | e6e5ad80 | bellard | case 0x2e: // BLT SRC ADDR 0x3f0000 |
1528 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1529 | e6e5ad80 | bellard | break;
|
1530 | e6e5ad80 | bellard | case 0x31: // BLT STATUS/START |
1531 | e6e5ad80 | bellard | cirrus_write_bitblt(s, reg_value); |
1532 | e6e5ad80 | bellard | break;
|
1533 | e6e5ad80 | bellard | default:
|
1534 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1535 | e6e5ad80 | bellard | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1536 | e6e5ad80 | bellard | reg_value); |
1537 | e6e5ad80 | bellard | #endif
|
1538 | e6e5ad80 | bellard | break;
|
1539 | e6e5ad80 | bellard | } |
1540 | e6e5ad80 | bellard | } |
1541 | e6e5ad80 | bellard | |
1542 | e6e5ad80 | bellard | /***************************************
|
1543 | e6e5ad80 | bellard | *
|
1544 | e6e5ad80 | bellard | * I/O access between 0x3d4-0x3d5
|
1545 | e6e5ad80 | bellard | *
|
1546 | e6e5ad80 | bellard | ***************************************/
|
1547 | e6e5ad80 | bellard | |
1548 | b863d514 | Juan Quintela | static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) |
1549 | e6e5ad80 | bellard | { |
1550 | e6e5ad80 | bellard | switch (reg_index) {
|
1551 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1552 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1553 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1554 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1555 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1556 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1557 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1558 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1559 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1560 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1561 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1562 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1563 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1564 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1565 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1566 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1567 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1568 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1569 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1570 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1571 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1572 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1573 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1574 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1575 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1576 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1577 | ca896ef3 | aurel32 | case 0x24: // Attribute Controller Toggle Readback (R) |
1578 | b863d514 | Juan Quintela | return (s->vga.ar_flip_flop << 7); |
1579 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1580 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1581 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1582 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1583 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1584 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1585 | e6e5ad80 | bellard | case 0x25: // Part Status |
1586 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1587 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1588 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1589 | b863d514 | Juan Quintela | return s->vga.ar_index & 0x3f; |
1590 | e6e5ad80 | bellard | break;
|
1591 | e6e5ad80 | bellard | default:
|
1592 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1593 | e6e5ad80 | bellard | printf("cirrus: inport cr_index %02x\n", reg_index);
|
1594 | e6e5ad80 | bellard | #endif
|
1595 | b863d514 | Juan Quintela | return 0xff; |
1596 | e6e5ad80 | bellard | } |
1597 | e6e5ad80 | bellard | } |
1598 | e6e5ad80 | bellard | |
1599 | 4ec1ce04 | Juan Quintela | static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) |
1600 | e6e5ad80 | bellard | { |
1601 | 4ec1ce04 | Juan Quintela | switch (s->vga.cr_index) {
|
1602 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1603 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1604 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1605 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1606 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1607 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1608 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1609 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1610 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1611 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1612 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1613 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1614 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1615 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1616 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1617 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1618 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1619 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1620 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1621 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1622 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1623 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1624 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1625 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1626 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1627 | 4ec1ce04 | Juan Quintela | /* handle CR0-7 protection */
|
1628 | 4ec1ce04 | Juan Quintela | if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { |
1629 | 4ec1ce04 | Juan Quintela | /* can always write bit 4 of CR7 */
|
1630 | 4ec1ce04 | Juan Quintela | if (s->vga.cr_index == 7) |
1631 | 4ec1ce04 | Juan Quintela | s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); |
1632 | 4ec1ce04 | Juan Quintela | return;
|
1633 | 4ec1ce04 | Juan Quintela | } |
1634 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1635 | 4ec1ce04 | Juan Quintela | switch(s->vga.cr_index) {
|
1636 | 4ec1ce04 | Juan Quintela | case 0x00: |
1637 | 4ec1ce04 | Juan Quintela | case 0x04: |
1638 | 4ec1ce04 | Juan Quintela | case 0x05: |
1639 | 4ec1ce04 | Juan Quintela | case 0x06: |
1640 | 4ec1ce04 | Juan Quintela | case 0x07: |
1641 | 4ec1ce04 | Juan Quintela | case 0x11: |
1642 | 4ec1ce04 | Juan Quintela | case 0x17: |
1643 | 4ec1ce04 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1644 | 4ec1ce04 | Juan Quintela | break;
|
1645 | 4ec1ce04 | Juan Quintela | } |
1646 | 4ec1ce04 | Juan Quintela | break;
|
1647 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1648 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1649 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1650 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1651 | ae184e4a | bellard | case 0x1d: // Overlay Extended Control |
1652 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1653 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1654 | e6e5ad80 | bellard | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1655 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1656 | e6e5ad80 | bellard | #endif
|
1657 | e6e5ad80 | bellard | break;
|
1658 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1659 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1660 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1661 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1662 | e6e5ad80 | bellard | break;
|
1663 | e6e5ad80 | bellard | case 0x25: // Part Status |
1664 | e6e5ad80 | bellard | default:
|
1665 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1666 | 4ec1ce04 | Juan Quintela | printf("cirrus: outport cr_index %02x, cr_value %02x\n",
|
1667 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1668 | e6e5ad80 | bellard | #endif
|
1669 | e6e5ad80 | bellard | break;
|
1670 | e6e5ad80 | bellard | } |
1671 | e6e5ad80 | bellard | } |
1672 | e6e5ad80 | bellard | |
1673 | e6e5ad80 | bellard | /***************************************
|
1674 | e6e5ad80 | bellard | *
|
1675 | e6e5ad80 | bellard | * memory-mapped I/O (bitblt)
|
1676 | e6e5ad80 | bellard | *
|
1677 | e6e5ad80 | bellard | ***************************************/
|
1678 | e6e5ad80 | bellard | |
1679 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1680 | e6e5ad80 | bellard | { |
1681 | e6e5ad80 | bellard | int value = 0xff; |
1682 | e6e5ad80 | bellard | |
1683 | e6e5ad80 | bellard | switch (address) {
|
1684 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1685 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x00);
|
1686 | e6e5ad80 | bellard | break;
|
1687 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1688 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x10);
|
1689 | e6e5ad80 | bellard | break;
|
1690 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1691 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x12);
|
1692 | e6e5ad80 | bellard | break;
|
1693 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1694 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x14);
|
1695 | e6e5ad80 | bellard | break;
|
1696 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1697 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x01);
|
1698 | e6e5ad80 | bellard | break;
|
1699 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1700 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x11);
|
1701 | e6e5ad80 | bellard | break;
|
1702 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1703 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x13);
|
1704 | e6e5ad80 | bellard | break;
|
1705 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1706 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x15);
|
1707 | e6e5ad80 | bellard | break;
|
1708 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1709 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x20);
|
1710 | e6e5ad80 | bellard | break;
|
1711 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1712 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x21);
|
1713 | e6e5ad80 | bellard | break;
|
1714 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1715 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x22);
|
1716 | e6e5ad80 | bellard | break;
|
1717 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1718 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x23);
|
1719 | e6e5ad80 | bellard | break;
|
1720 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1721 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x24);
|
1722 | e6e5ad80 | bellard | break;
|
1723 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1724 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x25);
|
1725 | e6e5ad80 | bellard | break;
|
1726 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1727 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x26);
|
1728 | e6e5ad80 | bellard | break;
|
1729 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1730 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x27);
|
1731 | e6e5ad80 | bellard | break;
|
1732 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1733 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x28);
|
1734 | e6e5ad80 | bellard | break;
|
1735 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1736 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x29);
|
1737 | e6e5ad80 | bellard | break;
|
1738 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1739 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2a);
|
1740 | e6e5ad80 | bellard | break;
|
1741 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1742 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2c);
|
1743 | e6e5ad80 | bellard | break;
|
1744 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1745 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2d);
|
1746 | e6e5ad80 | bellard | break;
|
1747 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1748 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2e);
|
1749 | e6e5ad80 | bellard | break;
|
1750 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1751 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2f);
|
1752 | e6e5ad80 | bellard | break;
|
1753 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1754 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x30);
|
1755 | e6e5ad80 | bellard | break;
|
1756 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1757 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x32);
|
1758 | e6e5ad80 | bellard | break;
|
1759 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1760 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x33);
|
1761 | a21ae81d | bellard | break;
|
1762 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1763 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x34);
|
1764 | e6e5ad80 | bellard | break;
|
1765 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1766 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x35);
|
1767 | e6e5ad80 | bellard | break;
|
1768 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1769 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x38);
|
1770 | e6e5ad80 | bellard | break;
|
1771 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1772 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x39);
|
1773 | e6e5ad80 | bellard | break;
|
1774 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1775 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x31);
|
1776 | e6e5ad80 | bellard | break;
|
1777 | e6e5ad80 | bellard | default:
|
1778 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1779 | e6e5ad80 | bellard | printf("cirrus: mmio read - address 0x%04x\n", address);
|
1780 | e6e5ad80 | bellard | #endif
|
1781 | e6e5ad80 | bellard | break;
|
1782 | e6e5ad80 | bellard | } |
1783 | e6e5ad80 | bellard | |
1784 | e6e5ad80 | bellard | return (uint8_t) value;
|
1785 | e6e5ad80 | bellard | } |
1786 | e6e5ad80 | bellard | |
1787 | e6e5ad80 | bellard | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1788 | e6e5ad80 | bellard | uint8_t value) |
1789 | e6e5ad80 | bellard | { |
1790 | e6e5ad80 | bellard | switch (address) {
|
1791 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1792 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x00, value);
|
1793 | e6e5ad80 | bellard | break;
|
1794 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1795 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x10, value);
|
1796 | e6e5ad80 | bellard | break;
|
1797 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1798 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x12, value);
|
1799 | e6e5ad80 | bellard | break;
|
1800 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1801 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x14, value);
|
1802 | e6e5ad80 | bellard | break;
|
1803 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1804 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x01, value);
|
1805 | e6e5ad80 | bellard | break;
|
1806 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1807 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x11, value);
|
1808 | e6e5ad80 | bellard | break;
|
1809 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1810 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x13, value);
|
1811 | e6e5ad80 | bellard | break;
|
1812 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1813 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x15, value);
|
1814 | e6e5ad80 | bellard | break;
|
1815 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1816 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x20, value);
|
1817 | e6e5ad80 | bellard | break;
|
1818 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1819 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x21, value);
|
1820 | e6e5ad80 | bellard | break;
|
1821 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1822 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x22, value);
|
1823 | e6e5ad80 | bellard | break;
|
1824 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1825 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x23, value);
|
1826 | e6e5ad80 | bellard | break;
|
1827 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1828 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x24, value);
|
1829 | e6e5ad80 | bellard | break;
|
1830 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1831 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x25, value);
|
1832 | e6e5ad80 | bellard | break;
|
1833 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1834 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x26, value);
|
1835 | e6e5ad80 | bellard | break;
|
1836 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1837 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x27, value);
|
1838 | e6e5ad80 | bellard | break;
|
1839 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1840 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x28, value);
|
1841 | e6e5ad80 | bellard | break;
|
1842 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1843 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x29, value);
|
1844 | e6e5ad80 | bellard | break;
|
1845 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1846 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2a, value);
|
1847 | e6e5ad80 | bellard | break;
|
1848 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1849 | e6e5ad80 | bellard | /* ignored */
|
1850 | e6e5ad80 | bellard | break;
|
1851 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1852 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2c, value);
|
1853 | e6e5ad80 | bellard | break;
|
1854 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1855 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2d, value);
|
1856 | e6e5ad80 | bellard | break;
|
1857 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1858 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2e, value);
|
1859 | e6e5ad80 | bellard | break;
|
1860 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1861 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2f, value);
|
1862 | e6e5ad80 | bellard | break;
|
1863 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1864 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x30, value);
|
1865 | e6e5ad80 | bellard | break;
|
1866 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1867 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x32, value);
|
1868 | e6e5ad80 | bellard | break;
|
1869 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1870 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x33, value);
|
1871 | a21ae81d | bellard | break;
|
1872 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1873 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x34, value);
|
1874 | e6e5ad80 | bellard | break;
|
1875 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1876 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x35, value);
|
1877 | e6e5ad80 | bellard | break;
|
1878 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1879 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x38, value);
|
1880 | e6e5ad80 | bellard | break;
|
1881 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1882 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x39, value);
|
1883 | e6e5ad80 | bellard | break;
|
1884 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1885 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x31, value);
|
1886 | e6e5ad80 | bellard | break;
|
1887 | e6e5ad80 | bellard | default:
|
1888 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1889 | e6e5ad80 | bellard | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1890 | e6e5ad80 | bellard | address, value); |
1891 | e6e5ad80 | bellard | #endif
|
1892 | e6e5ad80 | bellard | break;
|
1893 | e6e5ad80 | bellard | } |
1894 | e6e5ad80 | bellard | } |
1895 | e6e5ad80 | bellard | |
1896 | e6e5ad80 | bellard | /***************************************
|
1897 | e6e5ad80 | bellard | *
|
1898 | e6e5ad80 | bellard | * write mode 4/5
|
1899 | e6e5ad80 | bellard | *
|
1900 | e6e5ad80 | bellard | ***************************************/
|
1901 | e6e5ad80 | bellard | |
1902 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1903 | e6e5ad80 | bellard | unsigned mode,
|
1904 | e6e5ad80 | bellard | unsigned offset,
|
1905 | e6e5ad80 | bellard | uint32_t mem_value) |
1906 | e6e5ad80 | bellard | { |
1907 | e6e5ad80 | bellard | int x;
|
1908 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1909 | e6e5ad80 | bellard | uint8_t *dst; |
1910 | e6e5ad80 | bellard | |
1911 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1912 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1913 | e6e5ad80 | bellard | if (val & 0x80) { |
1914 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1915 | e6e5ad80 | bellard | } else if (mode == 5) { |
1916 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1917 | e6e5ad80 | bellard | } |
1918 | e6e5ad80 | bellard | val <<= 1;
|
1919 | 0b74ed78 | bellard | dst++; |
1920 | e6e5ad80 | bellard | } |
1921 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, offset, 8);
|
1922 | e6e5ad80 | bellard | } |
1923 | e6e5ad80 | bellard | |
1924 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1925 | e6e5ad80 | bellard | unsigned mode,
|
1926 | e6e5ad80 | bellard | unsigned offset,
|
1927 | e6e5ad80 | bellard | uint32_t mem_value) |
1928 | e6e5ad80 | bellard | { |
1929 | e6e5ad80 | bellard | int x;
|
1930 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1931 | e6e5ad80 | bellard | uint8_t *dst; |
1932 | e6e5ad80 | bellard | |
1933 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1934 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1935 | e6e5ad80 | bellard | if (val & 0x80) { |
1936 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1937 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x11]; |
1938 | e6e5ad80 | bellard | } else if (mode == 5) { |
1939 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1940 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x10]; |
1941 | e6e5ad80 | bellard | } |
1942 | e6e5ad80 | bellard | val <<= 1;
|
1943 | 0b74ed78 | bellard | dst += 2;
|
1944 | e6e5ad80 | bellard | } |
1945 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, offset, 16);
|
1946 | e6e5ad80 | bellard | } |
1947 | e6e5ad80 | bellard | |
1948 | e6e5ad80 | bellard | /***************************************
|
1949 | e6e5ad80 | bellard | *
|
1950 | e6e5ad80 | bellard | * memory access between 0xa0000-0xbffff
|
1951 | e6e5ad80 | bellard | *
|
1952 | e6e5ad80 | bellard | ***************************************/
|
1953 | e6e5ad80 | bellard | |
1954 | a815b166 | Avi Kivity | static uint64_t cirrus_vga_mem_read(void *opaque, |
1955 | a8170e5e | Avi Kivity | hwaddr addr, |
1956 | a815b166 | Avi Kivity | uint32_t size) |
1957 | e6e5ad80 | bellard | { |
1958 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1959 | e6e5ad80 | bellard | unsigned bank_index;
|
1960 | e6e5ad80 | bellard | unsigned bank_offset;
|
1961 | e6e5ad80 | bellard | uint32_t val; |
1962 | e6e5ad80 | bellard | |
1963 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
1964 | b2a5e761 | Avi Kivity | return vga_mem_readb(&s->vga, addr);
|
1965 | e6e5ad80 | bellard | } |
1966 | e6e5ad80 | bellard | |
1967 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1968 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
1969 | e6e5ad80 | bellard | /* video memory */
|
1970 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
1971 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
1972 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1973 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
1974 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
1975 | e6e5ad80 | bellard | bank_offset <<= 4;
|
1976 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
1977 | e6e5ad80 | bellard | bank_offset <<= 3;
|
1978 | e6e5ad80 | bellard | } |
1979 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
1980 | 4e12cd94 | Avi Kivity | val = *(s->vga.vram_ptr + bank_offset); |
1981 | e6e5ad80 | bellard | } else
|
1982 | e6e5ad80 | bellard | val = 0xff;
|
1983 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
1984 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
1985 | e6e5ad80 | bellard | val = 0xff;
|
1986 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
1987 | e6e5ad80 | bellard | val = cirrus_mmio_blt_read(s, addr & 0xff);
|
1988 | e6e5ad80 | bellard | } |
1989 | e6e5ad80 | bellard | } else {
|
1990 | e6e5ad80 | bellard | val = 0xff;
|
1991 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1992 | 0bf9e31a | Blue Swirl | printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); |
1993 | e6e5ad80 | bellard | #endif
|
1994 | e6e5ad80 | bellard | } |
1995 | e6e5ad80 | bellard | return val;
|
1996 | e6e5ad80 | bellard | } |
1997 | e6e5ad80 | bellard | |
1998 | a815b166 | Avi Kivity | static void cirrus_vga_mem_write(void *opaque, |
1999 | a8170e5e | Avi Kivity | hwaddr addr, |
2000 | a815b166 | Avi Kivity | uint64_t mem_value, |
2001 | a815b166 | Avi Kivity | uint32_t size) |
2002 | e6e5ad80 | bellard | { |
2003 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2004 | e6e5ad80 | bellard | unsigned bank_index;
|
2005 | e6e5ad80 | bellard | unsigned bank_offset;
|
2006 | e6e5ad80 | bellard | unsigned mode;
|
2007 | e6e5ad80 | bellard | |
2008 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
2009 | b2a5e761 | Avi Kivity | vga_mem_writeb(&s->vga, addr, mem_value); |
2010 | e6e5ad80 | bellard | return;
|
2011 | e6e5ad80 | bellard | } |
2012 | e6e5ad80 | bellard | |
2013 | e6e5ad80 | bellard | if (addr < 0x10000) { |
2014 | e6e5ad80 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2015 | e6e5ad80 | bellard | /* bitblt */
|
2016 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) mem_value; |
2017 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2018 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2019 | e6e5ad80 | bellard | } |
2020 | e6e5ad80 | bellard | } else {
|
2021 | e6e5ad80 | bellard | /* video memory */
|
2022 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
2023 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
2024 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
2025 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
2026 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2027 | e6e5ad80 | bellard | bank_offset <<= 4;
|
2028 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2029 | e6e5ad80 | bellard | bank_offset <<= 3;
|
2030 | e6e5ad80 | bellard | } |
2031 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
2032 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2033 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2034 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + bank_offset) = mem_value; |
2035 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, bank_offset, |
2036 | fd4aa979 | Blue Swirl | sizeof(mem_value));
|
2037 | e6e5ad80 | bellard | } else {
|
2038 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2039 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
2040 | e6e5ad80 | bellard | bank_offset, |
2041 | e6e5ad80 | bellard | mem_value); |
2042 | e6e5ad80 | bellard | } else {
|
2043 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
2044 | e6e5ad80 | bellard | bank_offset, |
2045 | e6e5ad80 | bellard | mem_value); |
2046 | e6e5ad80 | bellard | } |
2047 | e6e5ad80 | bellard | } |
2048 | e6e5ad80 | bellard | } |
2049 | e6e5ad80 | bellard | } |
2050 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
2051 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2052 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
2053 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
2054 | e6e5ad80 | bellard | } |
2055 | e6e5ad80 | bellard | } else {
|
2056 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
2057 | 08406b03 | malc | printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr, |
2058 | 08406b03 | malc | mem_value); |
2059 | e6e5ad80 | bellard | #endif
|
2060 | e6e5ad80 | bellard | } |
2061 | e6e5ad80 | bellard | } |
2062 | e6e5ad80 | bellard | |
2063 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_vga_mem_ops = { |
2064 | b1950430 | Avi Kivity | .read = cirrus_vga_mem_read, |
2065 | b1950430 | Avi Kivity | .write = cirrus_vga_mem_write, |
2066 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2067 | a815b166 | Avi Kivity | .impl = { |
2068 | a815b166 | Avi Kivity | .min_access_size = 1,
|
2069 | a815b166 | Avi Kivity | .max_access_size = 1,
|
2070 | a815b166 | Avi Kivity | }, |
2071 | e6e5ad80 | bellard | }; |
2072 | e6e5ad80 | bellard | |
2073 | e6e5ad80 | bellard | /***************************************
|
2074 | e6e5ad80 | bellard | *
|
2075 | a5082316 | bellard | * hardware cursor
|
2076 | a5082316 | bellard | *
|
2077 | a5082316 | bellard | ***************************************/
|
2078 | a5082316 | bellard | |
2079 | a5082316 | bellard | static inline void invalidate_cursor1(CirrusVGAState *s) |
2080 | a5082316 | bellard | { |
2081 | a5082316 | bellard | if (s->last_hw_cursor_size) {
|
2082 | 4e12cd94 | Avi Kivity | vga_invalidate_scanlines(&s->vga, |
2083 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
2084 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_end); |
2085 | a5082316 | bellard | } |
2086 | a5082316 | bellard | } |
2087 | a5082316 | bellard | |
2088 | a5082316 | bellard | static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) |
2089 | a5082316 | bellard | { |
2090 | a5082316 | bellard | const uint8_t *src;
|
2091 | a5082316 | bellard | uint32_t content; |
2092 | a5082316 | bellard | int y, y_min, y_max;
|
2093 | a5082316 | bellard | |
2094 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2095 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2096 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2097 | a5082316 | bellard | y_min = 64;
|
2098 | a5082316 | bellard | y_max = -1;
|
2099 | a5082316 | bellard | for(y = 0; y < 64; y++) { |
2100 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2101 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2102 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2103 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2104 | a5082316 | bellard | if (content) {
|
2105 | a5082316 | bellard | if (y < y_min)
|
2106 | a5082316 | bellard | y_min = y; |
2107 | a5082316 | bellard | if (y > y_max)
|
2108 | a5082316 | bellard | y_max = y; |
2109 | a5082316 | bellard | } |
2110 | a5082316 | bellard | src += 16;
|
2111 | a5082316 | bellard | } |
2112 | a5082316 | bellard | } else {
|
2113 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2114 | a5082316 | bellard | y_min = 32;
|
2115 | a5082316 | bellard | y_max = -1;
|
2116 | a5082316 | bellard | for(y = 0; y < 32; y++) { |
2117 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2118 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2119 | a5082316 | bellard | if (content) {
|
2120 | a5082316 | bellard | if (y < y_min)
|
2121 | a5082316 | bellard | y_min = y; |
2122 | a5082316 | bellard | if (y > y_max)
|
2123 | a5082316 | bellard | y_max = y; |
2124 | a5082316 | bellard | } |
2125 | a5082316 | bellard | src += 4;
|
2126 | a5082316 | bellard | } |
2127 | a5082316 | bellard | } |
2128 | a5082316 | bellard | if (y_min > y_max) {
|
2129 | a5082316 | bellard | s->last_hw_cursor_y_start = 0;
|
2130 | a5082316 | bellard | s->last_hw_cursor_y_end = 0;
|
2131 | a5082316 | bellard | } else {
|
2132 | a5082316 | bellard | s->last_hw_cursor_y_start = y_min; |
2133 | a5082316 | bellard | s->last_hw_cursor_y_end = y_max + 1;
|
2134 | a5082316 | bellard | } |
2135 | a5082316 | bellard | } |
2136 | a5082316 | bellard | |
2137 | a5082316 | bellard | /* NOTE: we do not currently handle the cursor bitmap change, so we
|
2138 | a5082316 | bellard | update the cursor only if it moves. */
|
2139 | a4a2f59c | Juan Quintela | static void cirrus_cursor_invalidate(VGACommonState *s1) |
2140 | a5082316 | bellard | { |
2141 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2142 | a5082316 | bellard | int size;
|
2143 | a5082316 | bellard | |
2144 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { |
2145 | a5082316 | bellard | size = 0;
|
2146 | a5082316 | bellard | } else {
|
2147 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) |
2148 | a5082316 | bellard | size = 64;
|
2149 | a5082316 | bellard | else
|
2150 | a5082316 | bellard | size = 32;
|
2151 | a5082316 | bellard | } |
2152 | a5082316 | bellard | /* invalidate last cursor and new cursor if any change */
|
2153 | a5082316 | bellard | if (s->last_hw_cursor_size != size ||
|
2154 | a5082316 | bellard | s->last_hw_cursor_x != s->hw_cursor_x || |
2155 | a5082316 | bellard | s->last_hw_cursor_y != s->hw_cursor_y) { |
2156 | a5082316 | bellard | |
2157 | a5082316 | bellard | invalidate_cursor1(s); |
2158 | 3b46e624 | ths | |
2159 | a5082316 | bellard | s->last_hw_cursor_size = size; |
2160 | a5082316 | bellard | s->last_hw_cursor_x = s->hw_cursor_x; |
2161 | a5082316 | bellard | s->last_hw_cursor_y = s->hw_cursor_y; |
2162 | a5082316 | bellard | /* compute the real cursor min and max y */
|
2163 | a5082316 | bellard | cirrus_cursor_compute_yrange(s); |
2164 | a5082316 | bellard | invalidate_cursor1(s); |
2165 | a5082316 | bellard | } |
2166 | a5082316 | bellard | } |
2167 | a5082316 | bellard | |
2168 | 94d7b483 | Blue Swirl | #define DEPTH 8 |
2169 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_template.h" |
2170 | 94d7b483 | Blue Swirl | |
2171 | 94d7b483 | Blue Swirl | #define DEPTH 16 |
2172 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_template.h" |
2173 | 94d7b483 | Blue Swirl | |
2174 | 94d7b483 | Blue Swirl | #define DEPTH 32 |
2175 | 83c9f4ca | Paolo Bonzini | #include "hw/cirrus_vga_template.h" |
2176 | 94d7b483 | Blue Swirl | |
2177 | a4a2f59c | Juan Quintela | static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) |
2178 | a5082316 | bellard | { |
2179 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2180 | c78f7137 | Gerd Hoffmann | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
2181 | a5082316 | bellard | int w, h, bpp, x1, x2, poffset;
|
2182 | a5082316 | bellard | unsigned int color0, color1; |
2183 | a5082316 | bellard | const uint8_t *palette, *src;
|
2184 | a5082316 | bellard | uint32_t content; |
2185 | 3b46e624 | ths | |
2186 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) |
2187 | a5082316 | bellard | return;
|
2188 | a5082316 | bellard | /* fast test to see if the cursor intersects with the scan line */
|
2189 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2190 | a5082316 | bellard | h = 64;
|
2191 | a5082316 | bellard | } else {
|
2192 | a5082316 | bellard | h = 32;
|
2193 | a5082316 | bellard | } |
2194 | a5082316 | bellard | if (scr_y < s->hw_cursor_y ||
|
2195 | a5082316 | bellard | scr_y >= (s->hw_cursor_y + h)) |
2196 | a5082316 | bellard | return;
|
2197 | 3b46e624 | ths | |
2198 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2199 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2200 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2201 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 16;
|
2202 | a5082316 | bellard | poffset = 8;
|
2203 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2204 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2205 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2206 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2207 | a5082316 | bellard | } else {
|
2208 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2209 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 4;
|
2210 | a5082316 | bellard | poffset = 128;
|
2211 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2212 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2213 | a5082316 | bellard | } |
2214 | a5082316 | bellard | /* if nothing to draw, no need to continue */
|
2215 | a5082316 | bellard | if (!content)
|
2216 | a5082316 | bellard | return;
|
2217 | a5082316 | bellard | w = h; |
2218 | a5082316 | bellard | |
2219 | a5082316 | bellard | x1 = s->hw_cursor_x; |
2220 | 4e12cd94 | Avi Kivity | if (x1 >= s->vga.last_scr_width)
|
2221 | a5082316 | bellard | return;
|
2222 | a5082316 | bellard | x2 = s->hw_cursor_x + w; |
2223 | 4e12cd94 | Avi Kivity | if (x2 > s->vga.last_scr_width)
|
2224 | 4e12cd94 | Avi Kivity | x2 = s->vga.last_scr_width; |
2225 | a5082316 | bellard | w = x2 - x1; |
2226 | a5082316 | bellard | palette = s->cirrus_hidden_palette; |
2227 | 4e12cd94 | Avi Kivity | color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
2228 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 1]), |
2229 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 2])); |
2230 | 4e12cd94 | Avi Kivity | color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]), |
2231 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 1]), |
2232 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 2])); |
2233 | c78f7137 | Gerd Hoffmann | bpp = surface_bytes_per_pixel(surface); |
2234 | a5082316 | bellard | d1 += x1 * bpp; |
2235 | c78f7137 | Gerd Hoffmann | switch (surface_bits_per_pixel(surface)) {
|
2236 | a5082316 | bellard | default:
|
2237 | a5082316 | bellard | break;
|
2238 | a5082316 | bellard | case 8: |
2239 | a5082316 | bellard | vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
|
2240 | a5082316 | bellard | break;
|
2241 | a5082316 | bellard | case 15: |
2242 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
|
2243 | a5082316 | bellard | break;
|
2244 | a5082316 | bellard | case 16: |
2245 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
|
2246 | a5082316 | bellard | break;
|
2247 | a5082316 | bellard | case 32: |
2248 | a5082316 | bellard | vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
|
2249 | a5082316 | bellard | break;
|
2250 | a5082316 | bellard | } |
2251 | a5082316 | bellard | } |
2252 | a5082316 | bellard | |
2253 | a5082316 | bellard | /***************************************
|
2254 | a5082316 | bellard | *
|
2255 | e6e5ad80 | bellard | * LFB memory access
|
2256 | e6e5ad80 | bellard | *
|
2257 | e6e5ad80 | bellard | ***************************************/
|
2258 | e6e5ad80 | bellard | |
2259 | a8170e5e | Avi Kivity | static uint64_t cirrus_linear_read(void *opaque, hwaddr addr, |
2260 | 899adf81 | Avi Kivity | unsigned size)
|
2261 | e6e5ad80 | bellard | { |
2262 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2263 | e6e5ad80 | bellard | uint32_t ret; |
2264 | e6e5ad80 | bellard | |
2265 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2266 | e6e5ad80 | bellard | |
2267 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2268 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2269 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2270 | e6e5ad80 | bellard | ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2271 | e6e5ad80 | bellard | } else if (0) { |
2272 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2273 | e6e5ad80 | bellard | ret = 0xff;
|
2274 | e6e5ad80 | bellard | } else {
|
2275 | e6e5ad80 | bellard | /* video memory */
|
2276 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2277 | e6e5ad80 | bellard | addr <<= 4;
|
2278 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2279 | e6e5ad80 | bellard | addr <<= 3;
|
2280 | e6e5ad80 | bellard | } |
2281 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2282 | 4e12cd94 | Avi Kivity | ret = *(s->vga.vram_ptr + addr); |
2283 | e6e5ad80 | bellard | } |
2284 | e6e5ad80 | bellard | |
2285 | e6e5ad80 | bellard | return ret;
|
2286 | e6e5ad80 | bellard | } |
2287 | e6e5ad80 | bellard | |
2288 | a8170e5e | Avi Kivity | static void cirrus_linear_write(void *opaque, hwaddr addr, |
2289 | 899adf81 | Avi Kivity | uint64_t val, unsigned size)
|
2290 | e6e5ad80 | bellard | { |
2291 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2292 | e6e5ad80 | bellard | unsigned mode;
|
2293 | e6e5ad80 | bellard | |
2294 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2295 | 3b46e624 | ths | |
2296 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2297 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2298 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2299 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2300 | e6e5ad80 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2301 | e6e5ad80 | bellard | /* bitblt */
|
2302 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2303 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2304 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2305 | e6e5ad80 | bellard | } |
2306 | e6e5ad80 | bellard | } else {
|
2307 | e6e5ad80 | bellard | /* video memory */
|
2308 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2309 | e6e5ad80 | bellard | addr <<= 4;
|
2310 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2311 | e6e5ad80 | bellard | addr <<= 3;
|
2312 | e6e5ad80 | bellard | } |
2313 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2314 | e6e5ad80 | bellard | |
2315 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2316 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2317 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + addr) = (uint8_t) val; |
2318 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, addr, 1);
|
2319 | e6e5ad80 | bellard | } else {
|
2320 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2321 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2322 | e6e5ad80 | bellard | } else {
|
2323 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2324 | e6e5ad80 | bellard | } |
2325 | e6e5ad80 | bellard | } |
2326 | e6e5ad80 | bellard | } |
2327 | e6e5ad80 | bellard | } |
2328 | e6e5ad80 | bellard | |
2329 | a5082316 | bellard | /***************************************
|
2330 | a5082316 | bellard | *
|
2331 | a5082316 | bellard | * system to screen memory access
|
2332 | a5082316 | bellard | *
|
2333 | a5082316 | bellard | ***************************************/
|
2334 | a5082316 | bellard | |
2335 | a5082316 | bellard | |
2336 | 4e56f089 | Avi Kivity | static uint64_t cirrus_linear_bitblt_read(void *opaque, |
2337 | a8170e5e | Avi Kivity | hwaddr addr, |
2338 | 4e56f089 | Avi Kivity | unsigned size)
|
2339 | a5082316 | bellard | { |
2340 | 4e56f089 | Avi Kivity | CirrusVGAState *s = opaque; |
2341 | a5082316 | bellard | uint32_t ret; |
2342 | a5082316 | bellard | |
2343 | a5082316 | bellard | /* XXX handle bitblt */
|
2344 | 4e56f089 | Avi Kivity | (void)s;
|
2345 | a5082316 | bellard | ret = 0xff;
|
2346 | a5082316 | bellard | return ret;
|
2347 | a5082316 | bellard | } |
2348 | a5082316 | bellard | |
2349 | 4e56f089 | Avi Kivity | static void cirrus_linear_bitblt_write(void *opaque, |
2350 | a8170e5e | Avi Kivity | hwaddr addr, |
2351 | 4e56f089 | Avi Kivity | uint64_t val, |
2352 | 4e56f089 | Avi Kivity | unsigned size)
|
2353 | a5082316 | bellard | { |
2354 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2355 | a5082316 | bellard | |
2356 | a5082316 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2357 | a5082316 | bellard | /* bitblt */
|
2358 | a5082316 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2359 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2360 | a5082316 | bellard | cirrus_bitblt_cputovideo_next(s); |
2361 | a5082316 | bellard | } |
2362 | a5082316 | bellard | } |
2363 | a5082316 | bellard | } |
2364 | a5082316 | bellard | |
2365 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { |
2366 | b1950430 | Avi Kivity | .read = cirrus_linear_bitblt_read, |
2367 | b1950430 | Avi Kivity | .write = cirrus_linear_bitblt_write, |
2368 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2369 | 4e56f089 | Avi Kivity | .impl = { |
2370 | 4e56f089 | Avi Kivity | .min_access_size = 1,
|
2371 | 4e56f089 | Avi Kivity | .max_access_size = 1,
|
2372 | 4e56f089 | Avi Kivity | }, |
2373 | a5082316 | bellard | }; |
2374 | a5082316 | bellard | |
2375 | b1950430 | Avi Kivity | static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) |
2376 | b1950430 | Avi Kivity | { |
2377 | 7969d9ed | Avi Kivity | MemoryRegion *mr = &s->cirrus_bank[bank]; |
2378 | 7969d9ed | Avi Kivity | bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
|
2379 | 4e12cd94 | Avi Kivity | && !((s->vga.sr[0x07] & 0x01) == 0) |
2380 | 4e12cd94 | Avi Kivity | && !((s->vga.gr[0x0B] & 0x14) == 0x14) |
2381 | 7969d9ed | Avi Kivity | && !(s->vga.gr[0x0B] & 0x02); |
2382 | 7969d9ed | Avi Kivity | |
2383 | 7969d9ed | Avi Kivity | memory_region_set_enabled(mr, enabled); |
2384 | 7969d9ed | Avi Kivity | memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); |
2385 | b1950430 | Avi Kivity | } |
2386 | 2bec46dc | aliguori | |
2387 | b1950430 | Avi Kivity | static void map_linear_vram(CirrusVGAState *s) |
2388 | b1950430 | Avi Kivity | { |
2389 | 4c08fd1e | Jan Kiszka | if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
|
2390 | b1950430 | Avi Kivity | s->linear_vram = true;
|
2391 | b1950430 | Avi Kivity | memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); |
2392 | b1950430 | Avi Kivity | } |
2393 | b1950430 | Avi Kivity | map_linear_vram_bank(s, 0);
|
2394 | b1950430 | Avi Kivity | map_linear_vram_bank(s, 1);
|
2395 | 2bec46dc | aliguori | } |
2396 | 2bec46dc | aliguori | |
2397 | 2bec46dc | aliguori | static void unmap_linear_vram(CirrusVGAState *s) |
2398 | 2bec46dc | aliguori | { |
2399 | 4c08fd1e | Jan Kiszka | if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
|
2400 | b1950430 | Avi Kivity | s->linear_vram = false;
|
2401 | b1950430 | Avi Kivity | memory_region_del_subregion(&s->pci_bar, &s->vga.vram); |
2402 | 4516e45f | Jan Kiszka | } |
2403 | 7969d9ed | Avi Kivity | memory_region_set_enabled(&s->cirrus_bank[0], false); |
2404 | 7969d9ed | Avi Kivity | memory_region_set_enabled(&s->cirrus_bank[1], false); |
2405 | 2bec46dc | aliguori | } |
2406 | 2bec46dc | aliguori | |
2407 | 8926b517 | bellard | /* Compute the memory access functions */
|
2408 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s) |
2409 | 8926b517 | bellard | { |
2410 | 8926b517 | bellard | unsigned mode;
|
2411 | 8926b517 | bellard | |
2412 | 64c048f4 | Avi Kivity | memory_region_transaction_begin(); |
2413 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x44) { |
2414 | 8926b517 | bellard | goto generic_io;
|
2415 | 8926b517 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2416 | 8926b517 | bellard | goto generic_io;
|
2417 | 8926b517 | bellard | } else {
|
2418 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2419 | 8926b517 | bellard | goto generic_io;
|
2420 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2421 | 8926b517 | bellard | goto generic_io;
|
2422 | 8926b517 | bellard | } |
2423 | 3b46e624 | ths | |
2424 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2425 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2426 | 2bec46dc | aliguori | map_linear_vram(s); |
2427 | 8926b517 | bellard | } else {
|
2428 | 8926b517 | bellard | generic_io:
|
2429 | 2bec46dc | aliguori | unmap_linear_vram(s); |
2430 | 8926b517 | bellard | } |
2431 | 8926b517 | bellard | } |
2432 | 64c048f4 | Avi Kivity | memory_region_transaction_commit(); |
2433 | 8926b517 | bellard | } |
2434 | 8926b517 | bellard | |
2435 | 8926b517 | bellard | |
2436 | e6e5ad80 | bellard | /* I/O ports */
|
2437 | e6e5ad80 | bellard | |
2438 | c75e6d8e | Julien Grall | static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr, |
2439 | c75e6d8e | Julien Grall | unsigned size)
|
2440 | e6e5ad80 | bellard | { |
2441 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2442 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2443 | e6e5ad80 | bellard | int val, index;
|
2444 | e6e5ad80 | bellard | |
2445 | bd8f2f5d | Jan Kiszka | qemu_flush_coalesced_mmio_buffer(); |
2446 | c75e6d8e | Julien Grall | addr += 0x3b0;
|
2447 | bd8f2f5d | Jan Kiszka | |
2448 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2449 | e6e5ad80 | bellard | val = 0xff;
|
2450 | e6e5ad80 | bellard | } else {
|
2451 | e6e5ad80 | bellard | switch (addr) {
|
2452 | e6e5ad80 | bellard | case 0x3c0: |
2453 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2454 | b6343073 | Juan Quintela | val = s->ar_index; |
2455 | e6e5ad80 | bellard | } else {
|
2456 | e6e5ad80 | bellard | val = 0;
|
2457 | e6e5ad80 | bellard | } |
2458 | e6e5ad80 | bellard | break;
|
2459 | e6e5ad80 | bellard | case 0x3c1: |
2460 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2461 | e6e5ad80 | bellard | if (index < 21) |
2462 | b6343073 | Juan Quintela | val = s->ar[index]; |
2463 | e6e5ad80 | bellard | else
|
2464 | e6e5ad80 | bellard | val = 0;
|
2465 | e6e5ad80 | bellard | break;
|
2466 | e6e5ad80 | bellard | case 0x3c2: |
2467 | b6343073 | Juan Quintela | val = s->st00; |
2468 | e6e5ad80 | bellard | break;
|
2469 | e6e5ad80 | bellard | case 0x3c4: |
2470 | b6343073 | Juan Quintela | val = s->sr_index; |
2471 | e6e5ad80 | bellard | break;
|
2472 | e6e5ad80 | bellard | case 0x3c5: |
2473 | 8a82c322 | Juan Quintela | val = cirrus_vga_read_sr(c); |
2474 | 8a82c322 | Juan Quintela | break;
|
2475 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2476 | b6343073 | Juan Quintela | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2477 | e6e5ad80 | bellard | #endif
|
2478 | e6e5ad80 | bellard | break;
|
2479 | e6e5ad80 | bellard | case 0x3c6: |
2480 | 957c9db5 | Juan Quintela | val = cirrus_read_hidden_dac(c); |
2481 | e6e5ad80 | bellard | break;
|
2482 | e6e5ad80 | bellard | case 0x3c7: |
2483 | b6343073 | Juan Quintela | val = s->dac_state; |
2484 | e6e5ad80 | bellard | break;
|
2485 | ae184e4a | bellard | case 0x3c8: |
2486 | b6343073 | Juan Quintela | val = s->dac_write_index; |
2487 | b6343073 | Juan Quintela | c->cirrus_hidden_dac_lockindex = 0;
|
2488 | ae184e4a | bellard | break;
|
2489 | ae184e4a | bellard | case 0x3c9: |
2490 | 5deaeee3 | Juan Quintela | val = cirrus_vga_read_palette(c); |
2491 | 5deaeee3 | Juan Quintela | break;
|
2492 | e6e5ad80 | bellard | case 0x3ca: |
2493 | b6343073 | Juan Quintela | val = s->fcr; |
2494 | e6e5ad80 | bellard | break;
|
2495 | e6e5ad80 | bellard | case 0x3cc: |
2496 | b6343073 | Juan Quintela | val = s->msr; |
2497 | e6e5ad80 | bellard | break;
|
2498 | e6e5ad80 | bellard | case 0x3ce: |
2499 | b6343073 | Juan Quintela | val = s->gr_index; |
2500 | e6e5ad80 | bellard | break;
|
2501 | e6e5ad80 | bellard | case 0x3cf: |
2502 | f705db9d | Juan Quintela | val = cirrus_vga_read_gr(c, s->gr_index); |
2503 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2504 | b6343073 | Juan Quintela | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2505 | e6e5ad80 | bellard | #endif
|
2506 | e6e5ad80 | bellard | break;
|
2507 | e6e5ad80 | bellard | case 0x3b4: |
2508 | e6e5ad80 | bellard | case 0x3d4: |
2509 | b6343073 | Juan Quintela | val = s->cr_index; |
2510 | e6e5ad80 | bellard | break;
|
2511 | e6e5ad80 | bellard | case 0x3b5: |
2512 | e6e5ad80 | bellard | case 0x3d5: |
2513 | b863d514 | Juan Quintela | val = cirrus_vga_read_cr(c, s->cr_index); |
2514 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2515 | b6343073 | Juan Quintela | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2516 | e6e5ad80 | bellard | #endif
|
2517 | e6e5ad80 | bellard | break;
|
2518 | e6e5ad80 | bellard | case 0x3ba: |
2519 | e6e5ad80 | bellard | case 0x3da: |
2520 | e6e5ad80 | bellard | /* just toggle to fool polling */
|
2521 | b6343073 | Juan Quintela | val = s->st01 = s->retrace(s); |
2522 | b6343073 | Juan Quintela | s->ar_flip_flop = 0;
|
2523 | e6e5ad80 | bellard | break;
|
2524 | e6e5ad80 | bellard | default:
|
2525 | e6e5ad80 | bellard | val = 0x00;
|
2526 | e6e5ad80 | bellard | break;
|
2527 | e6e5ad80 | bellard | } |
2528 | e6e5ad80 | bellard | } |
2529 | e6e5ad80 | bellard | #if defined(DEBUG_VGA)
|
2530 | e6e5ad80 | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2531 | e6e5ad80 | bellard | #endif
|
2532 | e6e5ad80 | bellard | return val;
|
2533 | e6e5ad80 | bellard | } |
2534 | e6e5ad80 | bellard | |
2535 | c75e6d8e | Julien Grall | static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
2536 | c75e6d8e | Julien Grall | unsigned size)
|
2537 | e6e5ad80 | bellard | { |
2538 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2539 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2540 | e6e5ad80 | bellard | int index;
|
2541 | e6e5ad80 | bellard | |
2542 | bd8f2f5d | Jan Kiszka | qemu_flush_coalesced_mmio_buffer(); |
2543 | c75e6d8e | Julien Grall | addr += 0x3b0;
|
2544 | bd8f2f5d | Jan Kiszka | |
2545 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2546 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2547 | e6e5ad80 | bellard | return;
|
2548 | 25a18cbd | Juan Quintela | } |
2549 | e6e5ad80 | bellard | #ifdef DEBUG_VGA
|
2550 | e6e5ad80 | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2551 | e6e5ad80 | bellard | #endif
|
2552 | e6e5ad80 | bellard | |
2553 | e6e5ad80 | bellard | switch (addr) {
|
2554 | e6e5ad80 | bellard | case 0x3c0: |
2555 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2556 | e6e5ad80 | bellard | val &= 0x3f;
|
2557 | b6343073 | Juan Quintela | s->ar_index = val; |
2558 | e6e5ad80 | bellard | } else {
|
2559 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2560 | e6e5ad80 | bellard | switch (index) {
|
2561 | e6e5ad80 | bellard | case 0x00 ... 0x0f: |
2562 | b6343073 | Juan Quintela | s->ar[index] = val & 0x3f;
|
2563 | e6e5ad80 | bellard | break;
|
2564 | e6e5ad80 | bellard | case 0x10: |
2565 | b6343073 | Juan Quintela | s->ar[index] = val & ~0x10;
|
2566 | e6e5ad80 | bellard | break;
|
2567 | e6e5ad80 | bellard | case 0x11: |
2568 | b6343073 | Juan Quintela | s->ar[index] = val; |
2569 | e6e5ad80 | bellard | break;
|
2570 | e6e5ad80 | bellard | case 0x12: |
2571 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xc0;
|
2572 | e6e5ad80 | bellard | break;
|
2573 | e6e5ad80 | bellard | case 0x13: |
2574 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2575 | e6e5ad80 | bellard | break;
|
2576 | e6e5ad80 | bellard | case 0x14: |
2577 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2578 | e6e5ad80 | bellard | break;
|
2579 | e6e5ad80 | bellard | default:
|
2580 | e6e5ad80 | bellard | break;
|
2581 | e6e5ad80 | bellard | } |
2582 | e6e5ad80 | bellard | } |
2583 | b6343073 | Juan Quintela | s->ar_flip_flop ^= 1;
|
2584 | e6e5ad80 | bellard | break;
|
2585 | e6e5ad80 | bellard | case 0x3c2: |
2586 | b6343073 | Juan Quintela | s->msr = val & ~0x10;
|
2587 | b6343073 | Juan Quintela | s->update_retrace_info(s); |
2588 | e6e5ad80 | bellard | break;
|
2589 | e6e5ad80 | bellard | case 0x3c4: |
2590 | b6343073 | Juan Quintela | s->sr_index = val; |
2591 | e6e5ad80 | bellard | break;
|
2592 | e6e5ad80 | bellard | case 0x3c5: |
2593 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2594 | b6343073 | Juan Quintela | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2595 | e6e5ad80 | bellard | #endif
|
2596 | 31c63201 | Juan Quintela | cirrus_vga_write_sr(c, val); |
2597 | 31c63201 | Juan Quintela | break;
|
2598 | e6e5ad80 | bellard | break;
|
2599 | e6e5ad80 | bellard | case 0x3c6: |
2600 | b6343073 | Juan Quintela | cirrus_write_hidden_dac(c, val); |
2601 | e6e5ad80 | bellard | break;
|
2602 | e6e5ad80 | bellard | case 0x3c7: |
2603 | b6343073 | Juan Quintela | s->dac_read_index = val; |
2604 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2605 | b6343073 | Juan Quintela | s->dac_state = 3;
|
2606 | e6e5ad80 | bellard | break;
|
2607 | e6e5ad80 | bellard | case 0x3c8: |
2608 | b6343073 | Juan Quintela | s->dac_write_index = val; |
2609 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2610 | b6343073 | Juan Quintela | s->dac_state = 0;
|
2611 | e6e5ad80 | bellard | break;
|
2612 | e6e5ad80 | bellard | case 0x3c9: |
2613 | 86948bb1 | Juan Quintela | cirrus_vga_write_palette(c, val); |
2614 | 86948bb1 | Juan Quintela | break;
|
2615 | e6e5ad80 | bellard | case 0x3ce: |
2616 | b6343073 | Juan Quintela | s->gr_index = val; |
2617 | e6e5ad80 | bellard | break;
|
2618 | e6e5ad80 | bellard | case 0x3cf: |
2619 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2620 | b6343073 | Juan Quintela | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2621 | e6e5ad80 | bellard | #endif
|
2622 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(c, s->gr_index, val); |
2623 | e6e5ad80 | bellard | break;
|
2624 | e6e5ad80 | bellard | case 0x3b4: |
2625 | e6e5ad80 | bellard | case 0x3d4: |
2626 | b6343073 | Juan Quintela | s->cr_index = val; |
2627 | e6e5ad80 | bellard | break;
|
2628 | e6e5ad80 | bellard | case 0x3b5: |
2629 | e6e5ad80 | bellard | case 0x3d5: |
2630 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2631 | b6343073 | Juan Quintela | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2632 | e6e5ad80 | bellard | #endif
|
2633 | 4ec1ce04 | Juan Quintela | cirrus_vga_write_cr(c, val); |
2634 | e6e5ad80 | bellard | break;
|
2635 | e6e5ad80 | bellard | case 0x3ba: |
2636 | e6e5ad80 | bellard | case 0x3da: |
2637 | b6343073 | Juan Quintela | s->fcr = val & 0x10;
|
2638 | e6e5ad80 | bellard | break;
|
2639 | e6e5ad80 | bellard | } |
2640 | e6e5ad80 | bellard | } |
2641 | e6e5ad80 | bellard | |
2642 | e6e5ad80 | bellard | /***************************************
|
2643 | e6e5ad80 | bellard | *
|
2644 | e36f36e1 | bellard | * memory-mapped I/O access
|
2645 | e36f36e1 | bellard | *
|
2646 | e36f36e1 | bellard | ***************************************/
|
2647 | e36f36e1 | bellard | |
2648 | a8170e5e | Avi Kivity | static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr, |
2649 | 1e04d4d6 | Avi Kivity | unsigned size)
|
2650 | e36f36e1 | bellard | { |
2651 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2652 | e36f36e1 | bellard | |
2653 | e36f36e1 | bellard | if (addr >= 0x100) { |
2654 | e36f36e1 | bellard | return cirrus_mmio_blt_read(s, addr - 0x100); |
2655 | e36f36e1 | bellard | } else {
|
2656 | c75e6d8e | Julien Grall | return cirrus_vga_ioport_read(s, addr + 0x10, size); |
2657 | e36f36e1 | bellard | } |
2658 | e36f36e1 | bellard | } |
2659 | e36f36e1 | bellard | |
2660 | a8170e5e | Avi Kivity | static void cirrus_mmio_write(void *opaque, hwaddr addr, |
2661 | 1e04d4d6 | Avi Kivity | uint64_t val, unsigned size)
|
2662 | e36f36e1 | bellard | { |
2663 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2664 | e36f36e1 | bellard | |
2665 | e36f36e1 | bellard | if (addr >= 0x100) { |
2666 | e36f36e1 | bellard | cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2667 | e36f36e1 | bellard | } else {
|
2668 | c75e6d8e | Julien Grall | cirrus_vga_ioport_write(s, addr + 0x10, val, size);
|
2669 | e36f36e1 | bellard | } |
2670 | e36f36e1 | bellard | } |
2671 | e36f36e1 | bellard | |
2672 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_mmio_io_ops = { |
2673 | b1950430 | Avi Kivity | .read = cirrus_mmio_read, |
2674 | b1950430 | Avi Kivity | .write = cirrus_mmio_write, |
2675 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2676 | 1e04d4d6 | Avi Kivity | .impl = { |
2677 | 1e04d4d6 | Avi Kivity | .min_access_size = 1,
|
2678 | 1e04d4d6 | Avi Kivity | .max_access_size = 1,
|
2679 | 1e04d4d6 | Avi Kivity | }, |
2680 | e36f36e1 | bellard | }; |
2681 | e36f36e1 | bellard | |
2682 | 2c6ab832 | bellard | /* load/save state */
|
2683 | 2c6ab832 | bellard | |
2684 | e59fb374 | Juan Quintela | static int cirrus_post_load(void *opaque, int version_id) |
2685 | 2c6ab832 | bellard | { |
2686 | 2c6ab832 | bellard | CirrusVGAState *s = opaque; |
2687 | 2c6ab832 | bellard | |
2688 | 4e12cd94 | Avi Kivity | s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
2689 | 4e12cd94 | Avi Kivity | s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; |
2690 | 2c6ab832 | bellard | |
2691 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
2692 | 2c6ab832 | bellard | /* force refresh */
|
2693 | 4e12cd94 | Avi Kivity | s->vga.graphic_mode = -1;
|
2694 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 0);
|
2695 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 1);
|
2696 | 2c6ab832 | bellard | return 0; |
2697 | 2c6ab832 | bellard | } |
2698 | 2c6ab832 | bellard | |
2699 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_cirrus_vga = { |
2700 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
2701 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
2702 | 7e72abc3 | Juan Quintela | .minimum_version_id = 1,
|
2703 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 1,
|
2704 | 7e72abc3 | Juan Quintela | .post_load = cirrus_post_load, |
2705 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
2706 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(vga.latch, CirrusVGAState), |
2707 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.sr_index, CirrusVGAState), |
2708 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.sr, CirrusVGAState), |
2709 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.gr_index, CirrusVGAState), |
2710 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), |
2711 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), |
2712 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
|
2713 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.ar_index, CirrusVGAState), |
2714 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.ar, CirrusVGAState), |
2715 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), |
2716 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.cr_index, CirrusVGAState), |
2717 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.cr, CirrusVGAState), |
2718 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.msr, CirrusVGAState), |
2719 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.fcr, CirrusVGAState), |
2720 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st00, CirrusVGAState), |
2721 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st01, CirrusVGAState), |
2722 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_state, CirrusVGAState), |
2723 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), |
2724 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), |
2725 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), |
2726 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), |
2727 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.palette, CirrusVGAState), |
2728 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.bank_offset, CirrusVGAState), |
2729 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), |
2730 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), |
2731 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_x, CirrusVGAState), |
2732 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_y, CirrusVGAState), |
2733 | 7e72abc3 | Juan Quintela | /* XXX: we do not save the bitblt state - we assume we do not save
|
2734 | 7e72abc3 | Juan Quintela | the state when the blitter is active */
|
2735 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
2736 | 4f335feb | Juan Quintela | } |
2737 | 7e72abc3 | Juan Quintela | }; |
2738 | 4f335feb | Juan Quintela | |
2739 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_pci_cirrus_vga = { |
2740 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
2741 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
2742 | 7e72abc3 | Juan Quintela | .minimum_version_id = 2,
|
2743 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 2,
|
2744 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
2745 | 7e72abc3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), |
2746 | 7e72abc3 | Juan Quintela | VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
|
2747 | 7e72abc3 | Juan Quintela | vmstate_cirrus_vga, CirrusVGAState), |
2748 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
2749 | 7e72abc3 | Juan Quintela | } |
2750 | 7e72abc3 | Juan Quintela | }; |
2751 | 4f335feb | Juan Quintela | |
2752 | e36f36e1 | bellard | /***************************************
|
2753 | e36f36e1 | bellard | *
|
2754 | e6e5ad80 | bellard | * initialize
|
2755 | e6e5ad80 | bellard | *
|
2756 | e6e5ad80 | bellard | ***************************************/
|
2757 | e6e5ad80 | bellard | |
2758 | 4abc796d | blueswir1 | static void cirrus_reset(void *opaque) |
2759 | e6e5ad80 | bellard | { |
2760 | 4abc796d | blueswir1 | CirrusVGAState *s = opaque; |
2761 | e6e5ad80 | bellard | |
2762 | 03a3e7ba | Juan Quintela | vga_common_reset(&s->vga); |
2763 | ee50c6bc | aliguori | unmap_linear_vram(s); |
2764 | 4e12cd94 | Avi Kivity | s->vga.sr[0x06] = 0x0f; |
2765 | 4abc796d | blueswir1 | if (s->device_id == CIRRUS_ID_CLGD5446) {
|
2766 | 78e127ef | bellard | /* 4MB 64 bit memory config, always PCI */
|
2767 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x2d; // MemClock |
2768 | 4e12cd94 | Avi Kivity | s->vga.gr[0x18] = 0x0f; // fastest memory configuration |
2769 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0f] = 0x98; |
2770 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = 0x20; |
2771 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ |
2772 | 78e127ef | bellard | } else {
|
2773 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x22; // MemClock |
2774 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
2775 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = s->bustype;
|
2776 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
2777 | 78e127ef | bellard | } |
2778 | 4e12cd94 | Avi Kivity | s->vga.cr[0x27] = s->device_id;
|
2779 | e6e5ad80 | bellard | |
2780 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 5;
|
2781 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = 0;
|
2782 | 4abc796d | blueswir1 | } |
2783 | 4abc796d | blueswir1 | |
2784 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_linear_io_ops = { |
2785 | b1950430 | Avi Kivity | .read = cirrus_linear_read, |
2786 | b1950430 | Avi Kivity | .write = cirrus_linear_write, |
2787 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2788 | 899adf81 | Avi Kivity | .impl = { |
2789 | 899adf81 | Avi Kivity | .min_access_size = 1,
|
2790 | 899adf81 | Avi Kivity | .max_access_size = 1,
|
2791 | 899adf81 | Avi Kivity | }, |
2792 | b1950430 | Avi Kivity | }; |
2793 | b1950430 | Avi Kivity | |
2794 | c75e6d8e | Julien Grall | static const MemoryRegionOps cirrus_vga_io_ops = { |
2795 | c75e6d8e | Julien Grall | .read = cirrus_vga_ioport_read, |
2796 | c75e6d8e | Julien Grall | .write = cirrus_vga_ioport_write, |
2797 | c75e6d8e | Julien Grall | .endianness = DEVICE_LITTLE_ENDIAN, |
2798 | c75e6d8e | Julien Grall | .impl = { |
2799 | c75e6d8e | Julien Grall | .min_access_size = 1,
|
2800 | c75e6d8e | Julien Grall | .max_access_size = 1,
|
2801 | c75e6d8e | Julien Grall | }, |
2802 | c75e6d8e | Julien Grall | }; |
2803 | c75e6d8e | Julien Grall | |
2804 | be20f9e9 | Avi Kivity | static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, |
2805 | c75e6d8e | Julien Grall | MemoryRegion *system_memory, |
2806 | c75e6d8e | Julien Grall | MemoryRegion *system_io) |
2807 | 4abc796d | blueswir1 | { |
2808 | 4abc796d | blueswir1 | int i;
|
2809 | 4abc796d | blueswir1 | static int inited; |
2810 | 4abc796d | blueswir1 | |
2811 | 4abc796d | blueswir1 | if (!inited) {
|
2812 | 4abc796d | blueswir1 | inited = 1;
|
2813 | 4abc796d | blueswir1 | for(i = 0;i < 256; i++) |
2814 | 4abc796d | blueswir1 | rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
|
2815 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_0] = 0;
|
2816 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
|
2817 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOP] = 2;
|
2818 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
|
2819 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTDST] = 4;
|
2820 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC] = 5;
|
2821 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_1] = 6;
|
2822 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
|
2823 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
|
2824 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
|
2825 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
|
2826 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
|
2827 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
|
2828 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
|
2829 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
|
2830 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
|
2831 | 4abc796d | blueswir1 | s->device_id = device_id; |
2832 | 4abc796d | blueswir1 | if (is_pci)
|
2833 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_PCI; |
2834 | 4abc796d | blueswir1 | else
|
2835 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_ISA; |
2836 | 4abc796d | blueswir1 | } |
2837 | 4abc796d | blueswir1 | |
2838 | c75e6d8e | Julien Grall | /* Register ioport 0x3b0 - 0x3df */
|
2839 | c75e6d8e | Julien Grall | memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s, |
2840 | c75e6d8e | Julien Grall | "cirrus-io", 0x30); |
2841 | c75e6d8e | Julien Grall | memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
|
2842 | 4abc796d | blueswir1 | |
2843 | b1950430 | Avi Kivity | memory_region_init(&s->low_mem_container, |
2844 | b1950430 | Avi Kivity | "cirrus-lowmem-container",
|
2845 | b1950430 | Avi Kivity | 0x20000);
|
2846 | b1950430 | Avi Kivity | |
2847 | b1950430 | Avi Kivity | memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s, |
2848 | b1950430 | Avi Kivity | "cirrus-low-memory", 0x20000); |
2849 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
|
2850 | 7969d9ed | Avi Kivity | for (i = 0; i < 2; ++i) { |
2851 | 7969d9ed | Avi Kivity | static const char *names[] = { "vga.bank0", "vga.bank1" }; |
2852 | 7969d9ed | Avi Kivity | MemoryRegion *bank = &s->cirrus_bank[i]; |
2853 | 7969d9ed | Avi Kivity | memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000); |
2854 | 7969d9ed | Avi Kivity | memory_region_set_enabled(bank, false);
|
2855 | 7969d9ed | Avi Kivity | memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
|
2856 | 7969d9ed | Avi Kivity | bank, 1);
|
2857 | 7969d9ed | Avi Kivity | } |
2858 | be20f9e9 | Avi Kivity | memory_region_add_subregion_overlap(system_memory, |
2859 | b1950430 | Avi Kivity | isa_mem_base + 0x000a0000,
|
2860 | b1950430 | Avi Kivity | &s->low_mem_container, |
2861 | b1950430 | Avi Kivity | 1);
|
2862 | b1950430 | Avi Kivity | memory_region_set_coalescing(&s->low_mem); |
2863 | 2c6ab832 | bellard | |
2864 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
2865 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s, |
2866 | 19403a68 | Marcelo Tosatti | "cirrus-linear-io", s->vga.vram_size_mb
|
2867 | 19403a68 | Marcelo Tosatti | * 1024 * 1024); |
2868 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_linear_io); |
2869 | fefe54e3 | aliguori | |
2870 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
2871 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_linear_bitblt_io, |
2872 | b1950430 | Avi Kivity | &cirrus_linear_bitblt_io_ops, |
2873 | b1950430 | Avi Kivity | s, |
2874 | b1950430 | Avi Kivity | "cirrus-bitblt-mmio",
|
2875 | b1950430 | Avi Kivity | 0x400000);
|
2876 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io); |
2877 | fefe54e3 | aliguori | |
2878 | fefe54e3 | aliguori | /* I/O handler for memory-mapped I/O */
|
2879 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s, |
2880 | b1950430 | Avi Kivity | "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
|
2881 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_mmio_io); |
2882 | fefe54e3 | aliguori | |
2883 | fefe54e3 | aliguori | s->real_vram_size = |
2884 | fefe54e3 | aliguori | (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; |
2885 | fefe54e3 | aliguori | |
2886 | 4e12cd94 | Avi Kivity | /* XXX: s->vga.vram_size must be a power of two */
|
2887 | fefe54e3 | aliguori | s->cirrus_addr_mask = s->real_vram_size - 1;
|
2888 | fefe54e3 | aliguori | s->linear_mmio_mask = s->real_vram_size - 256;
|
2889 | fefe54e3 | aliguori | |
2890 | 4e12cd94 | Avi Kivity | s->vga.get_bpp = cirrus_get_bpp; |
2891 | 4e12cd94 | Avi Kivity | s->vga.get_offsets = cirrus_get_offsets; |
2892 | 4e12cd94 | Avi Kivity | s->vga.get_resolution = cirrus_get_resolution; |
2893 | 4e12cd94 | Avi Kivity | s->vga.cursor_invalidate = cirrus_cursor_invalidate; |
2894 | 4e12cd94 | Avi Kivity | s->vga.cursor_draw_line = cirrus_cursor_draw_line; |
2895 | fefe54e3 | aliguori | |
2896 | a08d4367 | Jan Kiszka | qemu_register_reset(cirrus_reset, s); |
2897 | e6e5ad80 | bellard | } |
2898 | e6e5ad80 | bellard | |
2899 | e6e5ad80 | bellard | /***************************************
|
2900 | e6e5ad80 | bellard | *
|
2901 | e6e5ad80 | bellard | * ISA bus support
|
2902 | e6e5ad80 | bellard | *
|
2903 | e6e5ad80 | bellard | ***************************************/
|
2904 | e6e5ad80 | bellard | |
2905 | 3d402831 | Blue Swirl | static int vga_initfn(ISADevice *dev) |
2906 | e6e5ad80 | bellard | { |
2907 | 3d402831 | Blue Swirl | ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev); |
2908 | 3d402831 | Blue Swirl | VGACommonState *s = &d->cirrus_vga.vga; |
2909 | 3d402831 | Blue Swirl | |
2910 | 4a1e244e | Gerd Hoffmann | vga_common_init(s); |
2911 | 3d402831 | Blue Swirl | cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
|
2912 | c75e6d8e | Julien Grall | isa_address_space(dev), isa_address_space_io(dev)); |
2913 | c78f7137 | Gerd Hoffmann | s->con = graphic_console_init(s->update, s->invalidate, |
2914 | c78f7137 | Gerd Hoffmann | s->screen_dump, s->text_update, |
2915 | c78f7137 | Gerd Hoffmann | s); |
2916 | 5245d57a | Gerd Hoffmann | rom_add_vga(VGABIOS_CIRRUS_FILENAME); |
2917 | e6e5ad80 | bellard | /* XXX ISA-LFB support */
|
2918 | ad6d45fa | Anthony Liguori | /* FIXME not qdev yet */
|
2919 | 3d402831 | Blue Swirl | return 0; |
2920 | 3d402831 | Blue Swirl | } |
2921 | 3d402831 | Blue Swirl | |
2922 | 19403a68 | Marcelo Tosatti | static Property isa_vga_cirrus_properties[] = {
|
2923 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState, |
2924 | 19403a68 | Marcelo Tosatti | cirrus_vga.vga.vram_size_mb, 8),
|
2925 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_END_OF_LIST(), |
2926 | 19403a68 | Marcelo Tosatti | }; |
2927 | 19403a68 | Marcelo Tosatti | |
2928 | 8f04ee08 | Anthony Liguori | static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) |
2929 | 8f04ee08 | Anthony Liguori | { |
2930 | 8f04ee08 | Anthony Liguori | ISADeviceClass *k = ISA_DEVICE_CLASS(klass); |
2931 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
2932 | 8f04ee08 | Anthony Liguori | |
2933 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_cirrus_vga; |
2934 | 39bffca2 | Anthony Liguori | k->init = vga_initfn; |
2935 | 19403a68 | Marcelo Tosatti | dc->props = isa_vga_cirrus_properties; |
2936 | 8f04ee08 | Anthony Liguori | } |
2937 | 8f04ee08 | Anthony Liguori | |
2938 | 8c43a6f0 | Andreas Färber | static const TypeInfo isa_cirrus_vga_info = { |
2939 | 39bffca2 | Anthony Liguori | .name = "isa-cirrus-vga",
|
2940 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
2941 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(ISACirrusVGAState),
|
2942 | 8f04ee08 | Anthony Liguori | .class_init = isa_cirrus_vga_class_init, |
2943 | 3d402831 | Blue Swirl | }; |
2944 | 3d402831 | Blue Swirl | |
2945 | e6e5ad80 | bellard | /***************************************
|
2946 | e6e5ad80 | bellard | *
|
2947 | e6e5ad80 | bellard | * PCI bus support
|
2948 | e6e5ad80 | bellard | *
|
2949 | e6e5ad80 | bellard | ***************************************/
|
2950 | e6e5ad80 | bellard | |
2951 | 81a322d4 | Gerd Hoffmann | static int pci_cirrus_vga_initfn(PCIDevice *dev) |
2952 | a414c306 | Gerd Hoffmann | { |
2953 | a414c306 | Gerd Hoffmann | PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev); |
2954 | a414c306 | Gerd Hoffmann | CirrusVGAState *s = &d->cirrus_vga; |
2955 | 40021f08 | Anthony Liguori | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
2956 | 40021f08 | Anthony Liguori | int16_t device_id = pc->device_id; |
2957 | a414c306 | Gerd Hoffmann | |
2958 | a414c306 | Gerd Hoffmann | /* setup VGA */
|
2959 | 4a1e244e | Gerd Hoffmann | vga_common_init(&s->vga); |
2960 | c75e6d8e | Julien Grall | cirrus_init_common(s, device_id, 1, pci_address_space(dev),
|
2961 | c75e6d8e | Julien Grall | pci_address_space_io(dev)); |
2962 | c78f7137 | Gerd Hoffmann | s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate, |
2963 | c78f7137 | Gerd Hoffmann | s->vga.screen_dump, s->vga.text_update, |
2964 | c78f7137 | Gerd Hoffmann | &s->vga); |
2965 | a414c306 | Gerd Hoffmann | |
2966 | a414c306 | Gerd Hoffmann | /* setup PCI */
|
2967 | a414c306 | Gerd Hoffmann | |
2968 | b1950430 | Avi Kivity | memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000); |
2969 | b1950430 | Avi Kivity | |
2970 | b1950430 | Avi Kivity | /* XXX: add byte swapping apertures */
|
2971 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
|
2972 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->pci_bar, 0x1000000,
|
2973 | b1950430 | Avi Kivity | &s->cirrus_linear_bitblt_io); |
2974 | b1950430 | Avi Kivity | |
2975 | a414c306 | Gerd Hoffmann | /* setup memory space */
|
2976 | a414c306 | Gerd Hoffmann | /* memory #0 LFB */
|
2977 | a414c306 | Gerd Hoffmann | /* memory #1 memory-mapped I/O */
|
2978 | a414c306 | Gerd Hoffmann | /* XXX: s->vga.vram_size must be a power of two */
|
2979 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
|
2980 | a414c306 | Gerd Hoffmann | if (device_id == CIRRUS_ID_CLGD5446) {
|
2981 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); |
2982 | a414c306 | Gerd Hoffmann | } |
2983 | 81a322d4 | Gerd Hoffmann | return 0; |
2984 | a414c306 | Gerd Hoffmann | } |
2985 | a414c306 | Gerd Hoffmann | |
2986 | 19403a68 | Marcelo Tosatti | static Property pci_vga_cirrus_properties[] = {
|
2987 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState, |
2988 | 19403a68 | Marcelo Tosatti | cirrus_vga.vga.vram_size_mb, 8),
|
2989 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_END_OF_LIST(), |
2990 | 19403a68 | Marcelo Tosatti | }; |
2991 | 19403a68 | Marcelo Tosatti | |
2992 | 40021f08 | Anthony Liguori | static void cirrus_vga_class_init(ObjectClass *klass, void *data) |
2993 | 40021f08 | Anthony Liguori | { |
2994 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
2995 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2996 | 40021f08 | Anthony Liguori | |
2997 | 40021f08 | Anthony Liguori | k->no_hotplug = 1;
|
2998 | 40021f08 | Anthony Liguori | k->init = pci_cirrus_vga_initfn; |
2999 | 40021f08 | Anthony Liguori | k->romfile = VGABIOS_CIRRUS_FILENAME; |
3000 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_CIRRUS; |
3001 | 40021f08 | Anthony Liguori | k->device_id = CIRRUS_ID_CLGD5446; |
3002 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_DISPLAY_VGA; |
3003 | 39bffca2 | Anthony Liguori | dc->desc = "Cirrus CLGD 54xx VGA";
|
3004 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pci_cirrus_vga; |
3005 | 19403a68 | Marcelo Tosatti | dc->props = pci_vga_cirrus_properties; |
3006 | 40021f08 | Anthony Liguori | } |
3007 | 40021f08 | Anthony Liguori | |
3008 | 8c43a6f0 | Andreas Färber | static const TypeInfo cirrus_vga_info = { |
3009 | 39bffca2 | Anthony Liguori | .name = "cirrus-vga",
|
3010 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
3011 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCICirrusVGAState),
|
3012 | 39bffca2 | Anthony Liguori | .class_init = cirrus_vga_class_init, |
3013 | a414c306 | Gerd Hoffmann | }; |
3014 | e6e5ad80 | bellard | |
3015 | 83f7d43a | Andreas Färber | static void cirrus_vga_register_types(void) |
3016 | a414c306 | Gerd Hoffmann | { |
3017 | 83f7d43a | Andreas Färber | type_register_static(&isa_cirrus_vga_info); |
3018 | 39bffca2 | Anthony Liguori | type_register_static(&cirrus_vga_info); |
3019 | e6e5ad80 | bellard | } |
3020 | 83f7d43a | Andreas Färber | |
3021 | 83f7d43a | Andreas Färber | type_init(cirrus_vga_register_types) |