root / hw / intc / xilinx_intc.c @ 49ab747f
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/*
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* QEMU Xilinx OPB Interrupt Controller.
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*
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* Copyright (c) 2009 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "hw/hw.h" |
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#define D(x)
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#define R_ISR 0 |
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#define R_IPR 1 |
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#define R_IER 2 |
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#define R_IAR 3 |
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#define R_SIE 4 |
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#define R_CIE 5 |
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#define R_IVR 6 |
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#define R_MER 7 |
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#define R_MAX 8 |
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struct xlx_pic
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{ |
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SysBusDevice busdev; |
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MemoryRegion mmio; |
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qemu_irq parent_irq; |
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/* Configuration reg chosen at synthesis-time. QEMU populates
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the bits at board-setup. */
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uint32_t c_kind_of_intr; |
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/* Runtime control registers. */
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uint32_t regs[R_MAX]; |
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}; |
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static void update_irq(struct xlx_pic *p) |
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{ |
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uint32_t i; |
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/* Update the pending register. */
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p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; |
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/* Update the vector register. */
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for (i = 0; i < 32; i++) { |
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if (p->regs[R_IPR] & (1 << i)) |
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break;
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} |
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if (i == 32) |
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i = ~0;
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p->regs[R_IVR] = i; |
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if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) { |
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qemu_irq_raise(p->parent_irq); |
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} else {
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qemu_irq_lower(p->parent_irq); |
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} |
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} |
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static uint64_t
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pic_read(void *opaque, hwaddr addr, unsigned int size) |
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{ |
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struct xlx_pic *p = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr)
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{ |
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default:
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if (addr < ARRAY_SIZE(p->regs))
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r = p->regs[addr]; |
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break;
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} |
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D(printf("%s %x=%x\n", __func__, addr * 4, r)); |
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return r;
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} |
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static void |
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pic_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size) |
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{ |
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struct xlx_pic *p = opaque;
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uint32_t value = val64; |
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addr >>= 2;
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D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); |
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switch (addr)
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{ |
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case R_IAR:
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p->regs[R_ISR] &= ~value; /* ACK. */
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break;
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case R_SIE:
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p->regs[R_IER] |= value; /* Atomic set ie. */
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break;
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case R_CIE:
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p->regs[R_IER] &= ~value; /* Atomic clear ie. */
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break;
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default:
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if (addr < ARRAY_SIZE(p->regs))
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p->regs[addr] = value; |
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break;
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} |
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update_irq(p); |
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} |
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static const MemoryRegionOps pic_ops = { |
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.read = pic_read, |
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.write = pic_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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.valid = { |
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.min_access_size = 4,
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.max_access_size = 4
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} |
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}; |
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static void irq_handler(void *opaque, int irq, int level) |
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{ |
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struct xlx_pic *p = opaque;
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if (!(p->regs[R_MER] & 2)) { |
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qemu_irq_lower(p->parent_irq); |
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return;
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} |
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/* Update source flops. Don't clear unless level triggered.
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Edge triggered interrupts only go away when explicitely acked to
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the interrupt controller. */
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if (!(p->c_kind_of_intr & (1 << irq)) || level) { |
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p->regs[R_ISR] &= ~(1 << irq);
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p->regs[R_ISR] |= (level << irq); |
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} |
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update_irq(p); |
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} |
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static int xilinx_intc_init(SysBusDevice *dev) |
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{ |
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struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
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qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
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sysbus_init_irq(dev, &p->parent_irq); |
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memory_region_init_io(&p->mmio, &pic_ops, p, "xlnx.xps-intc", R_MAX * 4); |
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sysbus_init_mmio(dev, &p->mmio); |
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return 0; |
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} |
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static Property xilinx_intc_properties[] = {
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DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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static void xilinx_intc_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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k->init = xilinx_intc_init; |
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dc->props = xilinx_intc_properties; |
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} |
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static const TypeInfo xilinx_intc_info = { |
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.name = "xlnx.xps-intc",
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(struct xlx_pic), |
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.class_init = xilinx_intc_class_init, |
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}; |
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static void xilinx_intc_register_types(void) |
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{ |
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type_register_static(&xilinx_intc_info); |
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} |
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type_init(xilinx_intc_register_types) |