Revision 49ef6c90
| b/hw/sparc32_dma.c | ||
|---|---|---|
| 214 | 214 |
dma_mem_writel, |
| 215 | 215 |
}; |
| 216 | 216 |
|
| 217 |
static void dma_reset(void *opaque)
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|
| 217 |
static void dma_reset(DeviceState *d)
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|
| 218 | 218 |
{
|
| 219 |
DMAState *s = opaque;
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| 219 |
DMAState *s = container_of(d, DMAState, busdev.qdev);
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| 220 | 220 |
|
| 221 | 221 |
memset(s->dmaregs, 0, DMA_SIZE); |
| 222 | 222 |
s->dmaregs[0] = DMA_VER; |
| ... | ... | |
| 243 | 243 |
dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); |
| 244 | 244 |
sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); |
| 245 | 245 |
|
| 246 |
vmstate_register(-1, &vmstate_dma, s); |
|
| 247 |
qemu_register_reset(dma_reset, s); |
|
| 248 |
|
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| 249 | 246 |
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1); |
| 250 | 247 |
qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1); |
| 248 |
dma_reset(&s->busdev.qdev); |
|
| 249 |
|
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| 251 | 250 |
return 0; |
| 252 | 251 |
} |
| 253 | 252 |
|
| ... | ... | |
| 255 | 254 |
.init = sparc32_dma_init1, |
| 256 | 255 |
.qdev.name = "sparc32_dma", |
| 257 | 256 |
.qdev.size = sizeof(DMAState), |
| 257 |
.qdev.vmsd = &vmstate_dma, |
|
| 258 |
.qdev.reset = dma_reset, |
|
| 258 | 259 |
.qdev.props = (Property[]) {
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| 259 | 260 |
DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
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| 260 | 261 |
DEFINE_PROP_END_OF_LIST(), |
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