root / target-microblaze / translate.c @ 4a536270
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/*
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* Xilinx MicroBlaze emulation for qemu: main translation routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias.
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "disas/disas.h" |
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#include "tcg-op.h" |
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#include "helper.h" |
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#include "microblaze-decode.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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#define SIM_COMPAT 0 |
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#define DISAS_GNU 1 |
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#define DISAS_MB 1 |
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#if DISAS_MB && !SIM_COMPAT
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# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
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#else
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# define LOG_DIS(...) do { } while (0) |
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#endif
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#define D(x)
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1)) |
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static TCGv env_debug;
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static TCGv_ptr cpu_env;
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static TCGv cpu_R[32]; |
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static TCGv cpu_SR[18]; |
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static TCGv env_imm;
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static TCGv env_btaken;
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static TCGv env_btarget;
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static TCGv env_iflags;
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static TCGv env_res_addr;
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#include "exec/gen-icount.h" |
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/* This is the state at translation time. */
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typedef struct DisasContext { |
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CPUMBState *env; |
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target_ulong pc; |
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/* Decoder. */
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int type_b;
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uint32_t ir; |
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uint8_t opcode; |
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uint8_t rd, ra, rb; |
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uint16_t imm; |
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unsigned int cpustate_changed; |
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unsigned int delayed_branch; |
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */ |
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unsigned int clear_imm; |
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int is_jmp;
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#define JMP_NOJMP 0 |
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#define JMP_DIRECT 1 |
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#define JMP_DIRECT_CC 2 |
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#define JMP_INDIRECT 3 |
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unsigned int jmp; |
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uint32_t jmp_pc; |
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int abort_at_next_insn;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext; |
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static const char *regnames[] = |
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{ |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
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}; |
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static const char *special_regnames[] = |
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{ |
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"rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", |
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"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", |
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"sr16", "sr17", "sr18" |
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}; |
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/* Sign extend at translation time. */
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static inline int sign_extend(unsigned int val, unsigned int width) |
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{ |
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int sval;
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/* LSL. */
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val <<= 31 - width;
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sval = val; |
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/* ASR. */
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sval >>= 31 - width;
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return sval;
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} |
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static inline void t_sync_flags(DisasContext *dc) |
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{ |
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/* Synch the tb dependent flags between translator and runtime. */
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if (dc->tb_flags != dc->synced_flags) {
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tcg_gen_movi_tl(env_iflags, dc->tb_flags); |
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dc->synced_flags = dc->tb_flags; |
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} |
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} |
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static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) |
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{ |
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TCGv_i32 tmp = tcg_const_i32(index); |
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t_sync_flags(dc); |
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
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gen_helper_raise_exception(cpu_env, tmp); |
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tcg_temp_free_i32(tmp); |
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dc->is_jmp = DISAS_UPDATE; |
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} |
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
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{ |
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TranslationBlock *tb; |
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tb = dc->tb; |
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
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tcg_gen_goto_tb(n); |
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tcg_gen_movi_tl(cpu_SR[SR_PC], dest); |
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tcg_gen_exit_tb((uintptr_t)tb + n); |
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} else {
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tcg_gen_movi_tl(cpu_SR[SR_PC], dest); |
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tcg_gen_exit_tb(0);
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} |
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} |
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static void read_carry(DisasContext *dc, TCGv d) |
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{ |
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tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
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} |
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/*
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* write_carry sets the carry bits in MSR based on bit 0 of v.
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* v[31:1] are ignored.
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*/
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static void write_carry(DisasContext *dc, TCGv v) |
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{ |
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TCGv t0 = tcg_temp_new(); |
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tcg_gen_shli_tl(t0, v, 31);
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tcg_gen_sari_tl(t0, t0, 31);
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tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC)); |
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tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], |
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~(MSR_C | MSR_CC)); |
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tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); |
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tcg_temp_free(t0); |
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} |
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static void write_carryi(DisasContext *dc, bool carry) |
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{ |
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TCGv t0 = tcg_temp_new(); |
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tcg_gen_movi_tl(t0, carry); |
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write_carry(dc, t0); |
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tcg_temp_free(t0); |
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} |
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/* True if ALU operand b is a small immediate that may deserve
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faster treatment. */
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static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) |
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{ |
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/* Immediate insn without the imm prefix ? */
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return dc->type_b && !(dc->tb_flags & IMM_FLAG);
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} |
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static inline TCGv *dec_alu_op_b(DisasContext *dc) |
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{ |
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if (dc->type_b) {
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if (dc->tb_flags & IMM_FLAG)
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tcg_gen_ori_tl(env_imm, env_imm, dc->imm); |
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else
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tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm)); |
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return &env_imm;
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} else
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return &cpu_R[dc->rb];
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} |
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static void dec_add(DisasContext *dc) |
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{ |
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unsigned int k, c; |
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TCGv cf; |
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k = dc->opcode & 4;
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c = dc->opcode & 2;
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LOG_DIS("add%s%s%s r%d r%d r%d\n",
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dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", |
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dc->rd, dc->ra, dc->rb); |
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/* Take care of the easy cases first. */
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if (k) {
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/* k - keep carry, no need to update MSR. */
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/* If rd == r0, it's a nop. */
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if (dc->rd) {
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
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if (c) {
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/* c - Add carry into the result. */
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cf = tcg_temp_new(); |
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read_carry(dc, cf); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
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tcg_temp_free(cf); |
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} |
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} |
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return;
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} |
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/* From now on, we can assume k is zero. So we need to update MSR. */
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/* Extract carry. */
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cf = tcg_temp_new(); |
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if (c) {
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read_carry(dc, cf); |
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} else {
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tcg_gen_movi_tl(cf, 0);
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} |
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if (dc->rd) {
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TCGv ncf = tcg_temp_new(); |
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gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
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write_carry(dc, ncf); |
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tcg_temp_free(ncf); |
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} else {
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gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); |
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write_carry(dc, cf); |
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} |
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tcg_temp_free(cf); |
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} |
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static void dec_sub(DisasContext *dc) |
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{ |
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unsigned int u, cmp, k, c; |
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TCGv cf, na; |
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u = dc->imm & 2;
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k = dc->opcode & 4;
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c = dc->opcode & 2;
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cmp = (dc->imm & 1) && (!dc->type_b) && k;
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if (cmp) {
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LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); |
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if (dc->rd) {
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if (u)
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gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
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else
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gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
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} |
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return;
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} |
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LOG_DIS("sub%s%s r%d, r%d r%d\n",
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k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); |
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/* Take care of the easy cases first. */
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if (k) {
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/* k - keep carry, no need to update MSR. */
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/* If rd == r0, it's a nop. */
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if (dc->rd) {
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tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); |
282 |
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if (c) {
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/* c - Add carry into the result. */
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cf = tcg_temp_new(); |
286 |
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read_carry(dc, cf); |
288 |
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
289 |
tcg_temp_free(cf); |
290 |
} |
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} |
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return;
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} |
294 |
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/* From now on, we can assume k is zero. So we need to update MSR. */
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/* Extract carry. And complement a into na. */
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cf = tcg_temp_new(); |
298 |
na = tcg_temp_new(); |
299 |
if (c) {
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read_carry(dc, cf); |
301 |
} else {
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tcg_gen_movi_tl(cf, 1);
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} |
304 |
|
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/* d = b + ~a + c. carry defaults to 1. */
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tcg_gen_not_tl(na, cpu_R[dc->ra]); |
307 |
|
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if (dc->rd) {
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TCGv ncf = tcg_temp_new(); |
310 |
gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); |
311 |
tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); |
312 |
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
313 |
write_carry(dc, ncf); |
314 |
tcg_temp_free(ncf); |
315 |
} else {
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gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); |
317 |
write_carry(dc, cf); |
318 |
} |
319 |
tcg_temp_free(cf); |
320 |
tcg_temp_free(na); |
321 |
} |
322 |
|
323 |
static void dec_pattern(DisasContext *dc) |
324 |
{ |
325 |
unsigned int mode; |
326 |
int l1;
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327 |
|
328 |
if ((dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
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&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
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331 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
332 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
333 |
} |
334 |
|
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mode = dc->opcode & 3;
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336 |
switch (mode) {
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337 |
case 0: |
338 |
/* pcmpbf. */
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339 |
LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
340 |
if (dc->rd)
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341 |
gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
342 |
break;
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343 |
case 2: |
344 |
LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
345 |
if (dc->rd) {
|
346 |
TCGv t0 = tcg_temp_local_new(); |
347 |
l1 = gen_new_label(); |
348 |
tcg_gen_movi_tl(t0, 1);
|
349 |
tcg_gen_brcond_tl(TCG_COND_EQ, |
350 |
cpu_R[dc->ra], cpu_R[dc->rb], l1); |
351 |
tcg_gen_movi_tl(t0, 0);
|
352 |
gen_set_label(l1); |
353 |
tcg_gen_mov_tl(cpu_R[dc->rd], t0); |
354 |
tcg_temp_free(t0); |
355 |
} |
356 |
break;
|
357 |
case 3: |
358 |
LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
359 |
l1 = gen_new_label(); |
360 |
if (dc->rd) {
|
361 |
TCGv t0 = tcg_temp_local_new(); |
362 |
tcg_gen_movi_tl(t0, 1);
|
363 |
tcg_gen_brcond_tl(TCG_COND_NE, |
364 |
cpu_R[dc->ra], cpu_R[dc->rb], l1); |
365 |
tcg_gen_movi_tl(t0, 0);
|
366 |
gen_set_label(l1); |
367 |
tcg_gen_mov_tl(cpu_R[dc->rd], t0); |
368 |
tcg_temp_free(t0); |
369 |
} |
370 |
break;
|
371 |
default:
|
372 |
cpu_abort(dc->env, |
373 |
"unsupported pattern insn opcode=%x\n", dc->opcode);
|
374 |
break;
|
375 |
} |
376 |
} |
377 |
|
378 |
static void dec_and(DisasContext *dc) |
379 |
{ |
380 |
unsigned int not; |
381 |
|
382 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
383 |
dec_pattern(dc); |
384 |
return;
|
385 |
} |
386 |
|
387 |
not = dc->opcode & (1 << 1); |
388 |
LOG_DIS("and%s\n", not ? "n" : ""); |
389 |
|
390 |
if (!dc->rd)
|
391 |
return;
|
392 |
|
393 |
if (not) {
|
394 |
tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
395 |
} else
|
396 |
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
397 |
} |
398 |
|
399 |
static void dec_or(DisasContext *dc) |
400 |
{ |
401 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
402 |
dec_pattern(dc); |
403 |
return;
|
404 |
} |
405 |
|
406 |
LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
|
407 |
if (dc->rd)
|
408 |
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
409 |
} |
410 |
|
411 |
static void dec_xor(DisasContext *dc) |
412 |
{ |
413 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
414 |
dec_pattern(dc); |
415 |
return;
|
416 |
} |
417 |
|
418 |
LOG_DIS("xor r%d\n", dc->rd);
|
419 |
if (dc->rd)
|
420 |
tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
421 |
} |
422 |
|
423 |
static inline void msr_read(DisasContext *dc, TCGv d) |
424 |
{ |
425 |
tcg_gen_mov_tl(d, cpu_SR[SR_MSR]); |
426 |
} |
427 |
|
428 |
static inline void msr_write(DisasContext *dc, TCGv v) |
429 |
{ |
430 |
TCGv t; |
431 |
|
432 |
t = tcg_temp_new(); |
433 |
dc->cpustate_changed = 1;
|
434 |
/* PVR bit is not writable. */
|
435 |
tcg_gen_andi_tl(t, v, ~MSR_PVR); |
436 |
tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); |
437 |
tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); |
438 |
tcg_temp_free(t); |
439 |
} |
440 |
|
441 |
static void dec_msr(DisasContext *dc) |
442 |
{ |
443 |
TCGv t0, t1; |
444 |
unsigned int sr, to, rn; |
445 |
int mem_index = cpu_mmu_index(dc->env);
|
446 |
|
447 |
sr = dc->imm & ((1 << 14) - 1); |
448 |
to = dc->imm & (1 << 14); |
449 |
dc->type_b = 1;
|
450 |
if (to)
|
451 |
dc->cpustate_changed = 1;
|
452 |
|
453 |
/* msrclr and msrset. */
|
454 |
if (!(dc->imm & (1 << 15))) { |
455 |
unsigned int clr = dc->ir & (1 << 16); |
456 |
|
457 |
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", |
458 |
dc->rd, dc->imm); |
459 |
|
460 |
if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) { |
461 |
/* nop??? */
|
462 |
return;
|
463 |
} |
464 |
|
465 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
466 |
&& mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) { |
467 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
468 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
469 |
return;
|
470 |
} |
471 |
|
472 |
if (dc->rd)
|
473 |
msr_read(dc, cpu_R[dc->rd]); |
474 |
|
475 |
t0 = tcg_temp_new(); |
476 |
t1 = tcg_temp_new(); |
477 |
msr_read(dc, t0); |
478 |
tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc))); |
479 |
|
480 |
if (clr) {
|
481 |
tcg_gen_not_tl(t1, t1); |
482 |
tcg_gen_and_tl(t0, t0, t1); |
483 |
} else
|
484 |
tcg_gen_or_tl(t0, t0, t1); |
485 |
msr_write(dc, t0); |
486 |
tcg_temp_free(t0); |
487 |
tcg_temp_free(t1); |
488 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
|
489 |
dc->is_jmp = DISAS_UPDATE; |
490 |
return;
|
491 |
} |
492 |
|
493 |
if (to) {
|
494 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
495 |
&& mem_index == MMU_USER_IDX) { |
496 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
497 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
498 |
return;
|
499 |
} |
500 |
} |
501 |
|
502 |
#if !defined(CONFIG_USER_ONLY)
|
503 |
/* Catch read/writes to the mmu block. */
|
504 |
if ((sr & ~0xff) == 0x1000) { |
505 |
sr &= 7;
|
506 |
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); |
507 |
if (to)
|
508 |
gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]); |
509 |
else
|
510 |
gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr)); |
511 |
return;
|
512 |
} |
513 |
#endif
|
514 |
|
515 |
if (to) {
|
516 |
LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); |
517 |
switch (sr) {
|
518 |
case 0: |
519 |
break;
|
520 |
case 1: |
521 |
msr_write(dc, cpu_R[dc->ra]); |
522 |
break;
|
523 |
case 0x3: |
524 |
tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]); |
525 |
break;
|
526 |
case 0x5: |
527 |
tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]); |
528 |
break;
|
529 |
case 0x7: |
530 |
tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
|
531 |
break;
|
532 |
case 0x800: |
533 |
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr)); |
534 |
break;
|
535 |
case 0x802: |
536 |
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); |
537 |
break;
|
538 |
default:
|
539 |
cpu_abort(dc->env, "unknown mts reg %x\n", sr);
|
540 |
break;
|
541 |
} |
542 |
} else {
|
543 |
LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); |
544 |
|
545 |
switch (sr) {
|
546 |
case 0: |
547 |
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); |
548 |
break;
|
549 |
case 1: |
550 |
msr_read(dc, cpu_R[dc->rd]); |
551 |
break;
|
552 |
case 0x3: |
553 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]); |
554 |
break;
|
555 |
case 0x5: |
556 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]); |
557 |
break;
|
558 |
case 0x7: |
559 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]); |
560 |
break;
|
561 |
case 0xb: |
562 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]); |
563 |
break;
|
564 |
case 0x800: |
565 |
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr)); |
566 |
break;
|
567 |
case 0x802: |
568 |
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr)); |
569 |
break;
|
570 |
case 0x2000: |
571 |
case 0x2001: |
572 |
case 0x2002: |
573 |
case 0x2003: |
574 |
case 0x2004: |
575 |
case 0x2005: |
576 |
case 0x2006: |
577 |
case 0x2007: |
578 |
case 0x2008: |
579 |
case 0x2009: |
580 |
case 0x200a: |
581 |
case 0x200b: |
582 |
case 0x200c: |
583 |
rn = sr & 0xf;
|
584 |
tcg_gen_ld_tl(cpu_R[dc->rd], |
585 |
cpu_env, offsetof(CPUMBState, pvr.regs[rn])); |
586 |
break;
|
587 |
default:
|
588 |
cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
|
589 |
break;
|
590 |
} |
591 |
} |
592 |
|
593 |
if (dc->rd == 0) { |
594 |
tcg_gen_movi_tl(cpu_R[0], 0); |
595 |
} |
596 |
} |
597 |
|
598 |
/* 64-bit signed mul, lower result in d and upper in d2. */
|
599 |
static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) |
600 |
{ |
601 |
TCGv_i64 t0, t1; |
602 |
|
603 |
t0 = tcg_temp_new_i64(); |
604 |
t1 = tcg_temp_new_i64(); |
605 |
|
606 |
tcg_gen_ext_i32_i64(t0, a); |
607 |
tcg_gen_ext_i32_i64(t1, b); |
608 |
tcg_gen_mul_i64(t0, t0, t1); |
609 |
|
610 |
tcg_gen_trunc_i64_i32(d, t0); |
611 |
tcg_gen_shri_i64(t0, t0, 32);
|
612 |
tcg_gen_trunc_i64_i32(d2, t0); |
613 |
|
614 |
tcg_temp_free_i64(t0); |
615 |
tcg_temp_free_i64(t1); |
616 |
} |
617 |
|
618 |
/* 64-bit unsigned muls, lower result in d and upper in d2. */
|
619 |
static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) |
620 |
{ |
621 |
TCGv_i64 t0, t1; |
622 |
|
623 |
t0 = tcg_temp_new_i64(); |
624 |
t1 = tcg_temp_new_i64(); |
625 |
|
626 |
tcg_gen_extu_i32_i64(t0, a); |
627 |
tcg_gen_extu_i32_i64(t1, b); |
628 |
tcg_gen_mul_i64(t0, t0, t1); |
629 |
|
630 |
tcg_gen_trunc_i64_i32(d, t0); |
631 |
tcg_gen_shri_i64(t0, t0, 32);
|
632 |
tcg_gen_trunc_i64_i32(d2, t0); |
633 |
|
634 |
tcg_temp_free_i64(t0); |
635 |
tcg_temp_free_i64(t1); |
636 |
} |
637 |
|
638 |
/* Multiplier unit. */
|
639 |
static void dec_mul(DisasContext *dc) |
640 |
{ |
641 |
TCGv d[2];
|
642 |
unsigned int subcode; |
643 |
|
644 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
645 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
646 |
&& !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
|
647 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
648 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
649 |
return;
|
650 |
} |
651 |
|
652 |
subcode = dc->imm & 3;
|
653 |
d[0] = tcg_temp_new();
|
654 |
d[1] = tcg_temp_new();
|
655 |
|
656 |
if (dc->type_b) {
|
657 |
LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
|
658 |
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
|
659 |
goto done;
|
660 |
} |
661 |
|
662 |
/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
|
663 |
if (subcode >= 1 && subcode <= 3 |
664 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
|
665 |
/* nop??? */
|
666 |
} |
667 |
|
668 |
switch (subcode) {
|
669 |
case 0: |
670 |
LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
671 |
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
|
672 |
break;
|
673 |
case 1: |
674 |
LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
675 |
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
676 |
break;
|
677 |
case 2: |
678 |
LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
679 |
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
680 |
break;
|
681 |
case 3: |
682 |
LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
683 |
t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
684 |
break;
|
685 |
default:
|
686 |
cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
|
687 |
break;
|
688 |
} |
689 |
done:
|
690 |
tcg_temp_free(d[0]);
|
691 |
tcg_temp_free(d[1]);
|
692 |
} |
693 |
|
694 |
/* Div unit. */
|
695 |
static void dec_div(DisasContext *dc) |
696 |
{ |
697 |
unsigned int u; |
698 |
|
699 |
u = dc->imm & 2;
|
700 |
LOG_DIS("div\n");
|
701 |
|
702 |
if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
703 |
&& !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
|
704 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
705 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
706 |
} |
707 |
|
708 |
if (u)
|
709 |
gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), |
710 |
cpu_R[dc->ra]); |
711 |
else
|
712 |
gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), |
713 |
cpu_R[dc->ra]); |
714 |
if (!dc->rd)
|
715 |
tcg_gen_movi_tl(cpu_R[dc->rd], 0);
|
716 |
} |
717 |
|
718 |
static void dec_barrel(DisasContext *dc) |
719 |
{ |
720 |
TCGv t0; |
721 |
unsigned int s, t; |
722 |
|
723 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
724 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
725 |
&& !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
|
726 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
727 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
728 |
return;
|
729 |
} |
730 |
|
731 |
s = dc->imm & (1 << 10); |
732 |
t = dc->imm & (1 << 9); |
733 |
|
734 |
LOG_DIS("bs%s%s r%d r%d r%d\n",
|
735 |
s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); |
736 |
|
737 |
t0 = tcg_temp_new(); |
738 |
|
739 |
tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); |
740 |
tcg_gen_andi_tl(t0, t0, 31);
|
741 |
|
742 |
if (s)
|
743 |
tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
744 |
else {
|
745 |
if (t)
|
746 |
tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
747 |
else
|
748 |
tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
749 |
} |
750 |
} |
751 |
|
752 |
static void dec_bit(DisasContext *dc) |
753 |
{ |
754 |
TCGv t0; |
755 |
unsigned int op; |
756 |
int mem_index = cpu_mmu_index(dc->env);
|
757 |
|
758 |
op = dc->ir & ((1 << 9) - 1); |
759 |
switch (op) {
|
760 |
case 0x21: |
761 |
/* src. */
|
762 |
t0 = tcg_temp_new(); |
763 |
|
764 |
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
|
765 |
tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC); |
766 |
write_carry(dc, cpu_R[dc->ra]); |
767 |
if (dc->rd) {
|
768 |
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
769 |
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0); |
770 |
} |
771 |
tcg_temp_free(t0); |
772 |
break;
|
773 |
|
774 |
case 0x1: |
775 |
case 0x41: |
776 |
/* srl. */
|
777 |
LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
|
778 |
|
779 |
/* Update carry. Note that write carry only looks at the LSB. */
|
780 |
write_carry(dc, cpu_R[dc->ra]); |
781 |
if (dc->rd) {
|
782 |
if (op == 0x41) |
783 |
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
784 |
else
|
785 |
tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
786 |
} |
787 |
break;
|
788 |
case 0x60: |
789 |
LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
|
790 |
tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); |
791 |
break;
|
792 |
case 0x61: |
793 |
LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
|
794 |
tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); |
795 |
break;
|
796 |
case 0x64: |
797 |
case 0x66: |
798 |
case 0x74: |
799 |
case 0x76: |
800 |
/* wdc. */
|
801 |
LOG_DIS("wdc r%d\n", dc->ra);
|
802 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
803 |
&& mem_index == MMU_USER_IDX) { |
804 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
805 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
806 |
return;
|
807 |
} |
808 |
break;
|
809 |
case 0x68: |
810 |
/* wic. */
|
811 |
LOG_DIS("wic r%d\n", dc->ra);
|
812 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
813 |
&& mem_index == MMU_USER_IDX) { |
814 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
815 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
816 |
return;
|
817 |
} |
818 |
break;
|
819 |
case 0xe0: |
820 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
821 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
822 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
|
823 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
824 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
825 |
} |
826 |
if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) { |
827 |
gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); |
828 |
} |
829 |
break;
|
830 |
case 0x1e0: |
831 |
/* swapb */
|
832 |
LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
|
833 |
tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); |
834 |
break;
|
835 |
case 0x1e2: |
836 |
/*swaph */
|
837 |
LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
|
838 |
tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
|
839 |
break;
|
840 |
default:
|
841 |
cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
|
842 |
dc->pc, op, dc->rd, dc->ra, dc->rb); |
843 |
break;
|
844 |
} |
845 |
} |
846 |
|
847 |
static inline void sync_jmpstate(DisasContext *dc) |
848 |
{ |
849 |
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
|
850 |
if (dc->jmp == JMP_DIRECT) {
|
851 |
tcg_gen_movi_tl(env_btaken, 1);
|
852 |
} |
853 |
dc->jmp = JMP_INDIRECT; |
854 |
tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
855 |
} |
856 |
} |
857 |
|
858 |
static void dec_imm(DisasContext *dc) |
859 |
{ |
860 |
LOG_DIS("imm %x\n", dc->imm << 16); |
861 |
tcg_gen_movi_tl(env_imm, (dc->imm << 16));
|
862 |
dc->tb_flags |= IMM_FLAG; |
863 |
dc->clear_imm = 0;
|
864 |
} |
865 |
|
866 |
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
867 |
unsigned int size, bool exclusive) |
868 |
{ |
869 |
int mem_index = cpu_mmu_index(dc->env);
|
870 |
|
871 |
if (size == 1) { |
872 |
tcg_gen_qemu_ld8u(dst, addr, mem_index); |
873 |
} else if (size == 2) { |
874 |
tcg_gen_qemu_ld16u(dst, addr, mem_index); |
875 |
} else if (size == 4) { |
876 |
tcg_gen_qemu_ld32u(dst, addr, mem_index); |
877 |
} else
|
878 |
cpu_abort(dc->env, "Incorrect load size %d\n", size);
|
879 |
|
880 |
if (exclusive) {
|
881 |
tcg_gen_mov_tl(env_res_addr, addr); |
882 |
} |
883 |
} |
884 |
|
885 |
static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) |
886 |
{ |
887 |
unsigned int extimm = dc->tb_flags & IMM_FLAG; |
888 |
/* Should be set to one if r1 is used by loadstores. */
|
889 |
int stackprot = 0; |
890 |
|
891 |
/* All load/stores use ra. */
|
892 |
if (dc->ra == 1) { |
893 |
stackprot = 1;
|
894 |
} |
895 |
|
896 |
/* Treat the common cases first. */
|
897 |
if (!dc->type_b) {
|
898 |
/* If any of the regs is r0, return a ptr to the other. */
|
899 |
if (dc->ra == 0) { |
900 |
return &cpu_R[dc->rb];
|
901 |
} else if (dc->rb == 0) { |
902 |
return &cpu_R[dc->ra];
|
903 |
} |
904 |
|
905 |
if (dc->rb == 1) { |
906 |
stackprot = 1;
|
907 |
} |
908 |
|
909 |
*t = tcg_temp_new(); |
910 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); |
911 |
|
912 |
if (stackprot) {
|
913 |
gen_helper_stackprot(cpu_env, *t); |
914 |
} |
915 |
return t;
|
916 |
} |
917 |
/* Immediate. */
|
918 |
if (!extimm) {
|
919 |
if (dc->imm == 0) { |
920 |
return &cpu_R[dc->ra];
|
921 |
} |
922 |
*t = tcg_temp_new(); |
923 |
tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm)); |
924 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], *t); |
925 |
} else {
|
926 |
*t = tcg_temp_new(); |
927 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
928 |
} |
929 |
|
930 |
if (stackprot) {
|
931 |
gen_helper_stackprot(cpu_env, *t); |
932 |
} |
933 |
return t;
|
934 |
} |
935 |
|
936 |
static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size) |
937 |
{ |
938 |
if (size == 4) { |
939 |
tcg_gen_bswap32_tl(dst, src); |
940 |
} else if (size == 2) { |
941 |
TCGv t = tcg_temp_new(); |
942 |
|
943 |
/* bswap16 assumes the high bits are zero. */
|
944 |
tcg_gen_andi_tl(t, src, 0xffff);
|
945 |
tcg_gen_bswap16_tl(dst, t); |
946 |
tcg_temp_free(t); |
947 |
} else {
|
948 |
/* Ignore.
|
949 |
cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
|
950 |
*/
|
951 |
} |
952 |
} |
953 |
|
954 |
static void dec_load(DisasContext *dc) |
955 |
{ |
956 |
TCGv t, *addr; |
957 |
unsigned int size, rev = 0, ex = 0; |
958 |
|
959 |
size = 1 << (dc->opcode & 3); |
960 |
|
961 |
if (!dc->type_b) {
|
962 |
rev = (dc->ir >> 9) & 1; |
963 |
ex = (dc->ir >> 10) & 1; |
964 |
} |
965 |
|
966 |
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
967 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
968 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
969 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
970 |
return;
|
971 |
} |
972 |
|
973 |
LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", |
974 |
ex ? "x" : ""); |
975 |
|
976 |
t_sync_flags(dc); |
977 |
addr = compute_ldst_addr(dc, &t); |
978 |
|
979 |
/*
|
980 |
* When doing reverse accesses we need to do two things.
|
981 |
*
|
982 |
* 1. Reverse the address wrt endianness.
|
983 |
* 2. Byteswap the data lanes on the way back into the CPU core.
|
984 |
*/
|
985 |
if (rev && size != 4) { |
986 |
/* Endian reverse the address. t is addr. */
|
987 |
switch (size) {
|
988 |
case 1: |
989 |
{ |
990 |
/* 00 -> 11
|
991 |
01 -> 10
|
992 |
10 -> 10
|
993 |
11 -> 00 */
|
994 |
TCGv low = tcg_temp_new(); |
995 |
|
996 |
/* Force addr into the temp. */
|
997 |
if (addr != &t) {
|
998 |
t = tcg_temp_new(); |
999 |
tcg_gen_mov_tl(t, *addr); |
1000 |
addr = &t; |
1001 |
} |
1002 |
|
1003 |
tcg_gen_andi_tl(low, t, 3);
|
1004 |
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
|
1005 |
tcg_gen_andi_tl(t, t, ~3);
|
1006 |
tcg_gen_or_tl(t, t, low); |
1007 |
tcg_gen_mov_tl(env_imm, t); |
1008 |
tcg_temp_free(low); |
1009 |
break;
|
1010 |
} |
1011 |
|
1012 |
case 2: |
1013 |
/* 00 -> 10
|
1014 |
10 -> 00. */
|
1015 |
/* Force addr into the temp. */
|
1016 |
if (addr != &t) {
|
1017 |
t = tcg_temp_new(); |
1018 |
tcg_gen_xori_tl(t, *addr, 2);
|
1019 |
addr = &t; |
1020 |
} else {
|
1021 |
tcg_gen_xori_tl(t, t, 2);
|
1022 |
} |
1023 |
break;
|
1024 |
default:
|
1025 |
cpu_abort(dc->env, "Invalid reverse size\n");
|
1026 |
break;
|
1027 |
} |
1028 |
} |
1029 |
|
1030 |
/* lwx does not throw unaligned access errors, so force alignment */
|
1031 |
if (ex) {
|
1032 |
/* Force addr into the temp. */
|
1033 |
if (addr != &t) {
|
1034 |
t = tcg_temp_new(); |
1035 |
tcg_gen_mov_tl(t, *addr); |
1036 |
addr = &t; |
1037 |
} |
1038 |
tcg_gen_andi_tl(t, t, ~3);
|
1039 |
} |
1040 |
|
1041 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */
|
1042 |
sync_jmpstate(dc); |
1043 |
|
1044 |
/* Verify alignment if needed. */
|
1045 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { |
1046 |
TCGv v = tcg_temp_new(); |
1047 |
|
1048 |
/*
|
1049 |
* Microblaze gives MMU faults priority over faults due to
|
1050 |
* unaligned addresses. That's why we speculatively do the load
|
1051 |
* into v. If the load succeeds, we verify alignment of the
|
1052 |
* address and if that succeeds we write into the destination reg.
|
1053 |
*/
|
1054 |
gen_load(dc, v, *addr, size, ex); |
1055 |
|
1056 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1057 |
gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), |
1058 |
tcg_const_tl(0), tcg_const_tl(size - 1)); |
1059 |
if (dc->rd) {
|
1060 |
if (rev) {
|
1061 |
dec_byteswap(dc, cpu_R[dc->rd], v, size); |
1062 |
} else {
|
1063 |
tcg_gen_mov_tl(cpu_R[dc->rd], v); |
1064 |
} |
1065 |
} |
1066 |
tcg_temp_free(v); |
1067 |
} else {
|
1068 |
if (dc->rd) {
|
1069 |
gen_load(dc, cpu_R[dc->rd], *addr, size, ex); |
1070 |
if (rev) {
|
1071 |
dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size); |
1072 |
} |
1073 |
} else {
|
1074 |
/* We are loading into r0, no need to reverse. */
|
1075 |
gen_load(dc, env_imm, *addr, size, ex); |
1076 |
} |
1077 |
} |
1078 |
|
1079 |
if (ex) { /* lwx */ |
1080 |
/* no support for for AXI exclusive so always clear C */
|
1081 |
write_carryi(dc, 0);
|
1082 |
} |
1083 |
|
1084 |
if (addr == &t)
|
1085 |
tcg_temp_free(t); |
1086 |
} |
1087 |
|
1088 |
static void gen_store(DisasContext *dc, TCGv addr, TCGv val, |
1089 |
unsigned int size) |
1090 |
{ |
1091 |
int mem_index = cpu_mmu_index(dc->env);
|
1092 |
|
1093 |
if (size == 1) |
1094 |
tcg_gen_qemu_st8(val, addr, mem_index); |
1095 |
else if (size == 2) { |
1096 |
tcg_gen_qemu_st16(val, addr, mem_index); |
1097 |
} else if (size == 4) { |
1098 |
tcg_gen_qemu_st32(val, addr, mem_index); |
1099 |
} else
|
1100 |
cpu_abort(dc->env, "Incorrect store size %d\n", size);
|
1101 |
} |
1102 |
|
1103 |
static void dec_store(DisasContext *dc) |
1104 |
{ |
1105 |
TCGv t, *addr, swx_addr; |
1106 |
int swx_skip = 0; |
1107 |
unsigned int size, rev = 0, ex = 0; |
1108 |
|
1109 |
size = 1 << (dc->opcode & 3); |
1110 |
if (!dc->type_b) {
|
1111 |
rev = (dc->ir >> 9) & 1; |
1112 |
ex = (dc->ir >> 10) & 1; |
1113 |
} |
1114 |
|
1115 |
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
1116 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
1117 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1118 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1119 |
return;
|
1120 |
} |
1121 |
|
1122 |
LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", |
1123 |
ex ? "x" : ""); |
1124 |
t_sync_flags(dc); |
1125 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */
|
1126 |
sync_jmpstate(dc); |
1127 |
addr = compute_ldst_addr(dc, &t); |
1128 |
|
1129 |
swx_addr = tcg_temp_local_new(); |
1130 |
if (ex) { /* swx */ |
1131 |
|
1132 |
/* Force addr into the swx_addr. */
|
1133 |
tcg_gen_mov_tl(swx_addr, *addr); |
1134 |
addr = &swx_addr; |
1135 |
/* swx does not throw unaligned access errors, so force alignment */
|
1136 |
tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
|
1137 |
|
1138 |
write_carryi(dc, 1);
|
1139 |
swx_skip = gen_new_label(); |
1140 |
tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, swx_addr, swx_skip); |
1141 |
write_carryi(dc, 0);
|
1142 |
} |
1143 |
|
1144 |
if (rev && size != 4) { |
1145 |
/* Endian reverse the address. t is addr. */
|
1146 |
switch (size) {
|
1147 |
case 1: |
1148 |
{ |
1149 |
/* 00 -> 11
|
1150 |
01 -> 10
|
1151 |
10 -> 10
|
1152 |
11 -> 00 */
|
1153 |
TCGv low = tcg_temp_new(); |
1154 |
|
1155 |
/* Force addr into the temp. */
|
1156 |
if (addr != &t) {
|
1157 |
t = tcg_temp_new(); |
1158 |
tcg_gen_mov_tl(t, *addr); |
1159 |
addr = &t; |
1160 |
} |
1161 |
|
1162 |
tcg_gen_andi_tl(low, t, 3);
|
1163 |
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
|
1164 |
tcg_gen_andi_tl(t, t, ~3);
|
1165 |
tcg_gen_or_tl(t, t, low); |
1166 |
tcg_gen_mov_tl(env_imm, t); |
1167 |
tcg_temp_free(low); |
1168 |
break;
|
1169 |
} |
1170 |
|
1171 |
case 2: |
1172 |
/* 00 -> 10
|
1173 |
10 -> 00. */
|
1174 |
/* Force addr into the temp. */
|
1175 |
if (addr != &t) {
|
1176 |
t = tcg_temp_new(); |
1177 |
tcg_gen_xori_tl(t, *addr, 2);
|
1178 |
addr = &t; |
1179 |
} else {
|
1180 |
tcg_gen_xori_tl(t, t, 2);
|
1181 |
} |
1182 |
break;
|
1183 |
default:
|
1184 |
cpu_abort(dc->env, "Invalid reverse size\n");
|
1185 |
break;
|
1186 |
} |
1187 |
|
1188 |
if (size != 1) { |
1189 |
TCGv bs_data = tcg_temp_new(); |
1190 |
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); |
1191 |
gen_store(dc, *addr, bs_data, size); |
1192 |
tcg_temp_free(bs_data); |
1193 |
} else {
|
1194 |
gen_store(dc, *addr, cpu_R[dc->rd], size); |
1195 |
} |
1196 |
} else {
|
1197 |
if (rev) {
|
1198 |
TCGv bs_data = tcg_temp_new(); |
1199 |
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); |
1200 |
gen_store(dc, *addr, bs_data, size); |
1201 |
tcg_temp_free(bs_data); |
1202 |
} else {
|
1203 |
gen_store(dc, *addr, cpu_R[dc->rd], size); |
1204 |
} |
1205 |
} |
1206 |
|
1207 |
/* Verify alignment if needed. */
|
1208 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { |
1209 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1210 |
/* FIXME: if the alignment is wrong, we should restore the value
|
1211 |
* in memory. One possible way to achieve this is to probe
|
1212 |
* the MMU prior to the memaccess, thay way we could put
|
1213 |
* the alignment checks in between the probe and the mem
|
1214 |
* access.
|
1215 |
*/
|
1216 |
gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), |
1217 |
tcg_const_tl(1), tcg_const_tl(size - 1)); |
1218 |
} |
1219 |
|
1220 |
if (ex) {
|
1221 |
gen_set_label(swx_skip); |
1222 |
} |
1223 |
tcg_temp_free(swx_addr); |
1224 |
|
1225 |
if (addr == &t)
|
1226 |
tcg_temp_free(t); |
1227 |
} |
1228 |
|
1229 |
static inline void eval_cc(DisasContext *dc, unsigned int cc, |
1230 |
TCGv d, TCGv a, TCGv b) |
1231 |
{ |
1232 |
switch (cc) {
|
1233 |
case CC_EQ:
|
1234 |
tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b); |
1235 |
break;
|
1236 |
case CC_NE:
|
1237 |
tcg_gen_setcond_tl(TCG_COND_NE, d, a, b); |
1238 |
break;
|
1239 |
case CC_LT:
|
1240 |
tcg_gen_setcond_tl(TCG_COND_LT, d, a, b); |
1241 |
break;
|
1242 |
case CC_LE:
|
1243 |
tcg_gen_setcond_tl(TCG_COND_LE, d, a, b); |
1244 |
break;
|
1245 |
case CC_GE:
|
1246 |
tcg_gen_setcond_tl(TCG_COND_GE, d, a, b); |
1247 |
break;
|
1248 |
case CC_GT:
|
1249 |
tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); |
1250 |
break;
|
1251 |
default:
|
1252 |
cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
|
1253 |
break;
|
1254 |
} |
1255 |
} |
1256 |
|
1257 |
static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false) |
1258 |
{ |
1259 |
int l1;
|
1260 |
|
1261 |
l1 = gen_new_label(); |
1262 |
/* Conditional jmp. */
|
1263 |
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false); |
1264 |
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
|
1265 |
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true); |
1266 |
gen_set_label(l1); |
1267 |
} |
1268 |
|
1269 |
static void dec_bcc(DisasContext *dc) |
1270 |
{ |
1271 |
unsigned int cc; |
1272 |
unsigned int dslot; |
1273 |
|
1274 |
cc = EXTRACT_FIELD(dc->ir, 21, 23); |
1275 |
dslot = dc->ir & (1 << 25); |
1276 |
LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); |
1277 |
|
1278 |
dc->delayed_branch = 1;
|
1279 |
if (dslot) {
|
1280 |
dc->delayed_branch = 2;
|
1281 |
dc->tb_flags |= D_FLAG; |
1282 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1283 |
cpu_env, offsetof(CPUMBState, bimm)); |
1284 |
} |
1285 |
|
1286 |
if (dec_alu_op_b_is_small_imm(dc)) {
|
1287 |
int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
|
1288 |
|
1289 |
tcg_gen_movi_tl(env_btarget, dc->pc + offset); |
1290 |
dc->jmp = JMP_DIRECT_CC; |
1291 |
dc->jmp_pc = dc->pc + offset; |
1292 |
} else {
|
1293 |
dc->jmp = JMP_INDIRECT; |
1294 |
tcg_gen_movi_tl(env_btarget, dc->pc); |
1295 |
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); |
1296 |
} |
1297 |
eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
|
1298 |
} |
1299 |
|
1300 |
static void dec_br(DisasContext *dc) |
1301 |
{ |
1302 |
unsigned int dslot, link, abs, mbar; |
1303 |
int mem_index = cpu_mmu_index(dc->env);
|
1304 |
|
1305 |
dslot = dc->ir & (1 << 20); |
1306 |
abs = dc->ir & (1 << 19); |
1307 |
link = dc->ir & (1 << 18); |
1308 |
|
1309 |
/* Memory barrier. */
|
1310 |
mbar = (dc->ir >> 16) & 31; |
1311 |
if (mbar == 2 && dc->imm == 4) { |
1312 |
/* mbar IMM & 16 decodes to sleep. */
|
1313 |
if (dc->rd & 16) { |
1314 |
TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); |
1315 |
TCGv_i32 tmp_1 = tcg_const_i32(1);
|
1316 |
|
1317 |
LOG_DIS("sleep\n");
|
1318 |
|
1319 |
t_sync_flags(dc); |
1320 |
tcg_gen_st_i32(tmp_1, cpu_env, |
1321 |
-offsetof(MicroBlazeCPU, env) |
1322 |
+offsetof(CPUState, halted)); |
1323 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
|
1324 |
gen_helper_raise_exception(cpu_env, tmp_hlt); |
1325 |
tcg_temp_free_i32(tmp_hlt); |
1326 |
tcg_temp_free_i32(tmp_1); |
1327 |
return;
|
1328 |
} |
1329 |
LOG_DIS("mbar %d\n", dc->rd);
|
1330 |
/* Break the TB. */
|
1331 |
dc->cpustate_changed = 1;
|
1332 |
return;
|
1333 |
} |
1334 |
|
1335 |
LOG_DIS("br%s%s%s%s imm=%x\n",
|
1336 |
abs ? "a" : "", link ? "l" : "", |
1337 |
dc->type_b ? "i" : "", dslot ? "d" : "", |
1338 |
dc->imm); |
1339 |
|
1340 |
dc->delayed_branch = 1;
|
1341 |
if (dslot) {
|
1342 |
dc->delayed_branch = 2;
|
1343 |
dc->tb_flags |= D_FLAG; |
1344 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1345 |
cpu_env, offsetof(CPUMBState, bimm)); |
1346 |
} |
1347 |
if (link && dc->rd)
|
1348 |
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); |
1349 |
|
1350 |
dc->jmp = JMP_INDIRECT; |
1351 |
if (abs) {
|
1352 |
tcg_gen_movi_tl(env_btaken, 1);
|
1353 |
tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc))); |
1354 |
if (link && !dslot) {
|
1355 |
if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) |
1356 |
t_gen_raise_exception(dc, EXCP_BREAK); |
1357 |
if (dc->imm == 0) { |
1358 |
if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
|
1359 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1360 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1361 |
return;
|
1362 |
} |
1363 |
|
1364 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1365 |
} |
1366 |
} |
1367 |
} else {
|
1368 |
if (dec_alu_op_b_is_small_imm(dc)) {
|
1369 |
dc->jmp = JMP_DIRECT; |
1370 |
dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); |
1371 |
} else {
|
1372 |
tcg_gen_movi_tl(env_btaken, 1);
|
1373 |
tcg_gen_movi_tl(env_btarget, dc->pc); |
1374 |
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); |
1375 |
} |
1376 |
} |
1377 |
} |
1378 |
|
1379 |
static inline void do_rti(DisasContext *dc) |
1380 |
{ |
1381 |
TCGv t0, t1; |
1382 |
t0 = tcg_temp_new(); |
1383 |
t1 = tcg_temp_new(); |
1384 |
tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
|
1385 |
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE); |
1386 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1387 |
|
1388 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1389 |
tcg_gen_or_tl(t1, t1, t0); |
1390 |
msr_write(dc, t1); |
1391 |
tcg_temp_free(t1); |
1392 |
tcg_temp_free(t0); |
1393 |
dc->tb_flags &= ~DRTI_FLAG; |
1394 |
} |
1395 |
|
1396 |
static inline void do_rtb(DisasContext *dc) |
1397 |
{ |
1398 |
TCGv t0, t1; |
1399 |
t0 = tcg_temp_new(); |
1400 |
t1 = tcg_temp_new(); |
1401 |
tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP); |
1402 |
tcg_gen_shri_tl(t0, t1, 1);
|
1403 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1404 |
|
1405 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1406 |
tcg_gen_or_tl(t1, t1, t0); |
1407 |
msr_write(dc, t1); |
1408 |
tcg_temp_free(t1); |
1409 |
tcg_temp_free(t0); |
1410 |
dc->tb_flags &= ~DRTB_FLAG; |
1411 |
} |
1412 |
|
1413 |
static inline void do_rte(DisasContext *dc) |
1414 |
{ |
1415 |
TCGv t0, t1; |
1416 |
t0 = tcg_temp_new(); |
1417 |
t1 = tcg_temp_new(); |
1418 |
|
1419 |
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE); |
1420 |
tcg_gen_andi_tl(t1, t1, ~MSR_EIP); |
1421 |
tcg_gen_shri_tl(t0, t1, 1);
|
1422 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1423 |
|
1424 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1425 |
tcg_gen_or_tl(t1, t1, t0); |
1426 |
msr_write(dc, t1); |
1427 |
tcg_temp_free(t1); |
1428 |
tcg_temp_free(t0); |
1429 |
dc->tb_flags &= ~DRTE_FLAG; |
1430 |
} |
1431 |
|
1432 |
static void dec_rts(DisasContext *dc) |
1433 |
{ |
1434 |
unsigned int b_bit, i_bit, e_bit; |
1435 |
int mem_index = cpu_mmu_index(dc->env);
|
1436 |
|
1437 |
i_bit = dc->ir & (1 << 21); |
1438 |
b_bit = dc->ir & (1 << 22); |
1439 |
e_bit = dc->ir & (1 << 23); |
1440 |
|
1441 |
dc->delayed_branch = 2;
|
1442 |
dc->tb_flags |= D_FLAG; |
1443 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1444 |
cpu_env, offsetof(CPUMBState, bimm)); |
1445 |
|
1446 |
if (i_bit) {
|
1447 |
LOG_DIS("rtid ir=%x\n", dc->ir);
|
1448 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1449 |
&& mem_index == MMU_USER_IDX) { |
1450 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1451 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1452 |
} |
1453 |
dc->tb_flags |= DRTI_FLAG; |
1454 |
} else if (b_bit) { |
1455 |
LOG_DIS("rtbd ir=%x\n", dc->ir);
|
1456 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1457 |
&& mem_index == MMU_USER_IDX) { |
1458 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1459 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1460 |
} |
1461 |
dc->tb_flags |= DRTB_FLAG; |
1462 |
} else if (e_bit) { |
1463 |
LOG_DIS("rted ir=%x\n", dc->ir);
|
1464 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1465 |
&& mem_index == MMU_USER_IDX) { |
1466 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1467 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1468 |
} |
1469 |
dc->tb_flags |= DRTE_FLAG; |
1470 |
} else
|
1471 |
LOG_DIS("rts ir=%x\n", dc->ir);
|
1472 |
|
1473 |
dc->jmp = JMP_INDIRECT; |
1474 |
tcg_gen_movi_tl(env_btaken, 1);
|
1475 |
tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
1476 |
} |
1477 |
|
1478 |
static int dec_check_fpuv2(DisasContext *dc) |
1479 |
{ |
1480 |
int r;
|
1481 |
|
1482 |
r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
|
1483 |
|
1484 |
if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
|
1485 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); |
1486 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1487 |
} |
1488 |
return r;
|
1489 |
} |
1490 |
|
1491 |
static void dec_fpu(DisasContext *dc) |
1492 |
{ |
1493 |
unsigned int fpu_insn; |
1494 |
|
1495 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1496 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
1497 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
|
1498 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1499 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1500 |
return;
|
1501 |
} |
1502 |
|
1503 |
fpu_insn = (dc->ir >> 7) & 7; |
1504 |
|
1505 |
switch (fpu_insn) {
|
1506 |
case 0: |
1507 |
gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], |
1508 |
cpu_R[dc->rb]); |
1509 |
break;
|
1510 |
|
1511 |
case 1: |
1512 |
gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], |
1513 |
cpu_R[dc->rb]); |
1514 |
break;
|
1515 |
|
1516 |
case 2: |
1517 |
gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], |
1518 |
cpu_R[dc->rb]); |
1519 |
break;
|
1520 |
|
1521 |
case 3: |
1522 |
gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], |
1523 |
cpu_R[dc->rb]); |
1524 |
break;
|
1525 |
|
1526 |
case 4: |
1527 |
switch ((dc->ir >> 4) & 7) { |
1528 |
case 0: |
1529 |
gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, |
1530 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1531 |
break;
|
1532 |
case 1: |
1533 |
gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, |
1534 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1535 |
break;
|
1536 |
case 2: |
1537 |
gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, |
1538 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1539 |
break;
|
1540 |
case 3: |
1541 |
gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, |
1542 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1543 |
break;
|
1544 |
case 4: |
1545 |
gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, |
1546 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1547 |
break;
|
1548 |
case 5: |
1549 |
gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, |
1550 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1551 |
break;
|
1552 |
case 6: |
1553 |
gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, |
1554 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1555 |
break;
|
1556 |
default:
|
1557 |
qemu_log_mask(LOG_UNIMP, |
1558 |
"unimplemented fcmp fpu_insn=%x pc=%x"
|
1559 |
" opc=%x\n",
|
1560 |
fpu_insn, dc->pc, dc->opcode); |
1561 |
dc->abort_at_next_insn = 1;
|
1562 |
break;
|
1563 |
} |
1564 |
break;
|
1565 |
|
1566 |
case 5: |
1567 |
if (!dec_check_fpuv2(dc)) {
|
1568 |
return;
|
1569 |
} |
1570 |
gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); |
1571 |
break;
|
1572 |
|
1573 |
case 6: |
1574 |
if (!dec_check_fpuv2(dc)) {
|
1575 |
return;
|
1576 |
} |
1577 |
gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); |
1578 |
break;
|
1579 |
|
1580 |
case 7: |
1581 |
if (!dec_check_fpuv2(dc)) {
|
1582 |
return;
|
1583 |
} |
1584 |
gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); |
1585 |
break;
|
1586 |
|
1587 |
default:
|
1588 |
qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
|
1589 |
" opc=%x\n",
|
1590 |
fpu_insn, dc->pc, dc->opcode); |
1591 |
dc->abort_at_next_insn = 1;
|
1592 |
break;
|
1593 |
} |
1594 |
} |
1595 |
|
1596 |
static void dec_null(DisasContext *dc) |
1597 |
{ |
1598 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1599 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
1600 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1601 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1602 |
return;
|
1603 |
} |
1604 |
qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
|
1605 |
dc->abort_at_next_insn = 1;
|
1606 |
} |
1607 |
|
1608 |
/* Insns connected to FSL or AXI stream attached devices. */
|
1609 |
static void dec_stream(DisasContext *dc) |
1610 |
{ |
1611 |
int mem_index = cpu_mmu_index(dc->env);
|
1612 |
TCGv_i32 t_id, t_ctrl; |
1613 |
int ctrl;
|
1614 |
|
1615 |
LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", |
1616 |
dc->type_b ? "" : "d", dc->imm); |
1617 |
|
1618 |
if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
|
1619 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1620 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1621 |
return;
|
1622 |
} |
1623 |
|
1624 |
t_id = tcg_temp_new(); |
1625 |
if (dc->type_b) {
|
1626 |
tcg_gen_movi_tl(t_id, dc->imm & 0xf);
|
1627 |
ctrl = dc->imm >> 10;
|
1628 |
} else {
|
1629 |
tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
|
1630 |
ctrl = dc->imm >> 5;
|
1631 |
} |
1632 |
|
1633 |
t_ctrl = tcg_const_tl(ctrl); |
1634 |
|
1635 |
if (dc->rd == 0) { |
1636 |
gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); |
1637 |
} else {
|
1638 |
gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); |
1639 |
} |
1640 |
tcg_temp_free(t_id); |
1641 |
tcg_temp_free(t_ctrl); |
1642 |
} |
1643 |
|
1644 |
static struct decoder_info { |
1645 |
struct {
|
1646 |
uint32_t bits; |
1647 |
uint32_t mask; |
1648 |
}; |
1649 |
void (*dec)(DisasContext *dc);
|
1650 |
} decinfo[] = { |
1651 |
{DEC_ADD, dec_add}, |
1652 |
{DEC_SUB, dec_sub}, |
1653 |
{DEC_AND, dec_and}, |
1654 |
{DEC_XOR, dec_xor}, |
1655 |
{DEC_OR, dec_or}, |
1656 |
{DEC_BIT, dec_bit}, |
1657 |
{DEC_BARREL, dec_barrel}, |
1658 |
{DEC_LD, dec_load}, |
1659 |
{DEC_ST, dec_store}, |
1660 |
{DEC_IMM, dec_imm}, |
1661 |
{DEC_BR, dec_br}, |
1662 |
{DEC_BCC, dec_bcc}, |
1663 |
{DEC_RTS, dec_rts}, |
1664 |
{DEC_FPU, dec_fpu}, |
1665 |
{DEC_MUL, dec_mul}, |
1666 |
{DEC_DIV, dec_div}, |
1667 |
{DEC_MSR, dec_msr}, |
1668 |
{DEC_STREAM, dec_stream}, |
1669 |
{{0, 0}, dec_null} |
1670 |
}; |
1671 |
|
1672 |
static inline void decode(DisasContext *dc, uint32_t ir) |
1673 |
{ |
1674 |
int i;
|
1675 |
|
1676 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
1677 |
tcg_gen_debug_insn_start(dc->pc); |
1678 |
} |
1679 |
|
1680 |
dc->ir = ir; |
1681 |
LOG_DIS("%8.8x\t", dc->ir);
|
1682 |
|
1683 |
if (dc->ir)
|
1684 |
dc->nr_nops = 0;
|
1685 |
else {
|
1686 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1687 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
1688 |
&& (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
|
1689 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1690 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1691 |
return;
|
1692 |
} |
1693 |
|
1694 |
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
|
1695 |
dc->nr_nops++; |
1696 |
if (dc->nr_nops > 4) |
1697 |
cpu_abort(dc->env, "fetching nop sequence\n");
|
1698 |
} |
1699 |
/* bit 2 seems to indicate insn type. */
|
1700 |
dc->type_b = ir & (1 << 29); |
1701 |
|
1702 |
dc->opcode = EXTRACT_FIELD(ir, 26, 31); |
1703 |
dc->rd = EXTRACT_FIELD(ir, 21, 25); |
1704 |
dc->ra = EXTRACT_FIELD(ir, 16, 20); |
1705 |
dc->rb = EXTRACT_FIELD(ir, 11, 15); |
1706 |
dc->imm = EXTRACT_FIELD(ir, 0, 15); |
1707 |
|
1708 |
/* Large switch for all insns. */
|
1709 |
for (i = 0; i < ARRAY_SIZE(decinfo); i++) { |
1710 |
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
|
1711 |
decinfo[i].dec(dc); |
1712 |
break;
|
1713 |
} |
1714 |
} |
1715 |
} |
1716 |
|
1717 |
static void check_breakpoint(CPUMBState *env, DisasContext *dc) |
1718 |
{ |
1719 |
CPUBreakpoint *bp; |
1720 |
|
1721 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
1722 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1723 |
if (bp->pc == dc->pc) {
|
1724 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1725 |
dc->is_jmp = DISAS_UPDATE; |
1726 |
} |
1727 |
} |
1728 |
} |
1729 |
} |
1730 |
|
1731 |
/* generate intermediate code for basic block 'tb'. */
|
1732 |
static inline void |
1733 |
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, |
1734 |
bool search_pc)
|
1735 |
{ |
1736 |
CPUState *cs = CPU(cpu); |
1737 |
CPUMBState *env = &cpu->env; |
1738 |
uint16_t *gen_opc_end; |
1739 |
uint32_t pc_start; |
1740 |
int j, lj;
|
1741 |
struct DisasContext ctx;
|
1742 |
struct DisasContext *dc = &ctx;
|
1743 |
uint32_t next_page_start, org_flags; |
1744 |
target_ulong npc; |
1745 |
int num_insns;
|
1746 |
int max_insns;
|
1747 |
|
1748 |
pc_start = tb->pc; |
1749 |
dc->env = env; |
1750 |
dc->tb = tb; |
1751 |
org_flags = dc->synced_flags = dc->tb_flags = tb->flags; |
1752 |
|
1753 |
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
1754 |
|
1755 |
dc->is_jmp = DISAS_NEXT; |
1756 |
dc->jmp = 0;
|
1757 |
dc->delayed_branch = !!(dc->tb_flags & D_FLAG); |
1758 |
if (dc->delayed_branch) {
|
1759 |
dc->jmp = JMP_INDIRECT; |
1760 |
} |
1761 |
dc->pc = pc_start; |
1762 |
dc->singlestep_enabled = cs->singlestep_enabled; |
1763 |
dc->cpustate_changed = 0;
|
1764 |
dc->abort_at_next_insn = 0;
|
1765 |
dc->nr_nops = 0;
|
1766 |
|
1767 |
if (pc_start & 3) |
1768 |
cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
|
1769 |
|
1770 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1771 |
#if !SIM_COMPAT
|
1772 |
qemu_log("--------------\n");
|
1773 |
log_cpu_state(CPU(cpu), 0);
|
1774 |
#endif
|
1775 |
} |
1776 |
|
1777 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
1778 |
lj = -1;
|
1779 |
num_insns = 0;
|
1780 |
max_insns = tb->cflags & CF_COUNT_MASK; |
1781 |
if (max_insns == 0) |
1782 |
max_insns = CF_COUNT_MASK; |
1783 |
|
1784 |
gen_tb_start(); |
1785 |
do
|
1786 |
{ |
1787 |
#if SIM_COMPAT
|
1788 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1789 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1790 |
gen_helper_debug(); |
1791 |
} |
1792 |
#endif
|
1793 |
check_breakpoint(env, dc); |
1794 |
|
1795 |
if (search_pc) {
|
1796 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
1797 |
if (lj < j) {
|
1798 |
lj++; |
1799 |
while (lj < j)
|
1800 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
1801 |
} |
1802 |
tcg_ctx.gen_opc_pc[lj] = dc->pc; |
1803 |
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
1804 |
tcg_ctx.gen_opc_icount[lj] = num_insns; |
1805 |
} |
1806 |
|
1807 |
/* Pretty disas. */
|
1808 |
LOG_DIS("%8.8x:\t", dc->pc);
|
1809 |
|
1810 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1811 |
gen_io_start(); |
1812 |
|
1813 |
dc->clear_imm = 1;
|
1814 |
decode(dc, cpu_ldl_code(env, dc->pc)); |
1815 |
if (dc->clear_imm)
|
1816 |
dc->tb_flags &= ~IMM_FLAG; |
1817 |
dc->pc += 4;
|
1818 |
num_insns++; |
1819 |
|
1820 |
if (dc->delayed_branch) {
|
1821 |
dc->delayed_branch--; |
1822 |
if (!dc->delayed_branch) {
|
1823 |
if (dc->tb_flags & DRTI_FLAG)
|
1824 |
do_rti(dc); |
1825 |
if (dc->tb_flags & DRTB_FLAG)
|
1826 |
do_rtb(dc); |
1827 |
if (dc->tb_flags & DRTE_FLAG)
|
1828 |
do_rte(dc); |
1829 |
/* Clear the delay slot flag. */
|
1830 |
dc->tb_flags &= ~D_FLAG; |
1831 |
/* If it is a direct jump, try direct chaining. */
|
1832 |
if (dc->jmp == JMP_INDIRECT) {
|
1833 |
eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc)); |
1834 |
dc->is_jmp = DISAS_JUMP; |
1835 |
} else if (dc->jmp == JMP_DIRECT) { |
1836 |
t_sync_flags(dc); |
1837 |
gen_goto_tb(dc, 0, dc->jmp_pc);
|
1838 |
dc->is_jmp = DISAS_TB_JUMP; |
1839 |
} else if (dc->jmp == JMP_DIRECT_CC) { |
1840 |
int l1;
|
1841 |
|
1842 |
t_sync_flags(dc); |
1843 |
l1 = gen_new_label(); |
1844 |
/* Conditional jmp. */
|
1845 |
tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
|
1846 |
gen_goto_tb(dc, 1, dc->pc);
|
1847 |
gen_set_label(l1); |
1848 |
gen_goto_tb(dc, 0, dc->jmp_pc);
|
1849 |
|
1850 |
dc->is_jmp = DISAS_TB_JUMP; |
1851 |
} |
1852 |
break;
|
1853 |
} |
1854 |
} |
1855 |
if (cs->singlestep_enabled) {
|
1856 |
break;
|
1857 |
} |
1858 |
} while (!dc->is_jmp && !dc->cpustate_changed
|
1859 |
&& tcg_ctx.gen_opc_ptr < gen_opc_end |
1860 |
&& !singlestep |
1861 |
&& (dc->pc < next_page_start) |
1862 |
&& num_insns < max_insns); |
1863 |
|
1864 |
npc = dc->pc; |
1865 |
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
|
1866 |
if (dc->tb_flags & D_FLAG) {
|
1867 |
dc->is_jmp = DISAS_UPDATE; |
1868 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1869 |
sync_jmpstate(dc); |
1870 |
} else
|
1871 |
npc = dc->jmp_pc; |
1872 |
} |
1873 |
|
1874 |
if (tb->cflags & CF_LAST_IO)
|
1875 |
gen_io_end(); |
1876 |
/* Force an update if the per-tb cpu state has changed. */
|
1877 |
if (dc->is_jmp == DISAS_NEXT
|
1878 |
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) { |
1879 |
dc->is_jmp = DISAS_UPDATE; |
1880 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1881 |
} |
1882 |
t_sync_flags(dc); |
1883 |
|
1884 |
if (unlikely(cs->singlestep_enabled)) {
|
1885 |
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); |
1886 |
|
1887 |
if (dc->is_jmp != DISAS_JUMP) {
|
1888 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1889 |
} |
1890 |
gen_helper_raise_exception(cpu_env, tmp); |
1891 |
tcg_temp_free_i32(tmp); |
1892 |
} else {
|
1893 |
switch(dc->is_jmp) {
|
1894 |
case DISAS_NEXT:
|
1895 |
gen_goto_tb(dc, 1, npc);
|
1896 |
break;
|
1897 |
default:
|
1898 |
case DISAS_JUMP:
|
1899 |
case DISAS_UPDATE:
|
1900 |
/* indicate that the hash table must be used
|
1901 |
to find the next TB */
|
1902 |
tcg_gen_exit_tb(0);
|
1903 |
break;
|
1904 |
case DISAS_TB_JUMP:
|
1905 |
/* nothing more to generate */
|
1906 |
break;
|
1907 |
} |
1908 |
} |
1909 |
gen_tb_end(tb, num_insns); |
1910 |
*tcg_ctx.gen_opc_ptr = INDEX_op_end; |
1911 |
if (search_pc) {
|
1912 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
1913 |
lj++; |
1914 |
while (lj <= j)
|
1915 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
1916 |
} else {
|
1917 |
tb->size = dc->pc - pc_start; |
1918 |
tb->icount = num_insns; |
1919 |
} |
1920 |
|
1921 |
#ifdef DEBUG_DISAS
|
1922 |
#if !SIM_COMPAT
|
1923 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1924 |
qemu_log("\n");
|
1925 |
#if DISAS_GNU
|
1926 |
log_target_disas(env, pc_start, dc->pc - pc_start, 0);
|
1927 |
#endif
|
1928 |
qemu_log("\nisize=%d osize=%td\n",
|
1929 |
dc->pc - pc_start, tcg_ctx.gen_opc_ptr - |
1930 |
tcg_ctx.gen_opc_buf); |
1931 |
} |
1932 |
#endif
|
1933 |
#endif
|
1934 |
assert(!dc->abort_at_next_insn); |
1935 |
} |
1936 |
|
1937 |
void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb) |
1938 |
{ |
1939 |
gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
|
1940 |
} |
1941 |
|
1942 |
void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb) |
1943 |
{ |
1944 |
gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
|
1945 |
} |
1946 |
|
1947 |
void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
|
1948 |
int flags)
|
1949 |
{ |
1950 |
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
1951 |
CPUMBState *env = &cpu->env; |
1952 |
int i;
|
1953 |
|
1954 |
if (!env || !f)
|
1955 |
return;
|
1956 |
|
1957 |
cpu_fprintf(f, "IN: PC=%x %s\n",
|
1958 |
env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); |
1959 |
cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
|
1960 |
env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], |
1961 |
env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); |
1962 |
cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
|
1963 |
env->btaken, env->btarget, |
1964 |
(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", |
1965 |
(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", |
1966 |
(env->sregs[SR_MSR] & MSR_EIP), |
1967 |
(env->sregs[SR_MSR] & MSR_IE)); |
1968 |
|
1969 |
for (i = 0; i < 32; i++) { |
1970 |
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
|
1971 |
if ((i + 1) % 4 == 0) |
1972 |
cpu_fprintf(f, "\n");
|
1973 |
} |
1974 |
cpu_fprintf(f, "\n\n");
|
1975 |
} |
1976 |
|
1977 |
MicroBlazeCPU *cpu_mb_init(const char *cpu_model) |
1978 |
{ |
1979 |
MicroBlazeCPU *cpu; |
1980 |
|
1981 |
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); |
1982 |
|
1983 |
object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
1984 |
|
1985 |
return cpu;
|
1986 |
} |
1987 |
|
1988 |
void mb_tcg_init(void) |
1989 |
{ |
1990 |
int i;
|
1991 |
|
1992 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
1993 |
|
1994 |
env_debug = tcg_global_mem_new(TCG_AREG0, |
1995 |
offsetof(CPUMBState, debug), |
1996 |
"debug0");
|
1997 |
env_iflags = tcg_global_mem_new(TCG_AREG0, |
1998 |
offsetof(CPUMBState, iflags), |
1999 |
"iflags");
|
2000 |
env_imm = tcg_global_mem_new(TCG_AREG0, |
2001 |
offsetof(CPUMBState, imm), |
2002 |
"imm");
|
2003 |
env_btarget = tcg_global_mem_new(TCG_AREG0, |
2004 |
offsetof(CPUMBState, btarget), |
2005 |
"btarget");
|
2006 |
env_btaken = tcg_global_mem_new(TCG_AREG0, |
2007 |
offsetof(CPUMBState, btaken), |
2008 |
"btaken");
|
2009 |
env_res_addr = tcg_global_mem_new(TCG_AREG0, |
2010 |
offsetof(CPUMBState, res_addr), |
2011 |
"res_addr");
|
2012 |
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { |
2013 |
cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
2014 |
offsetof(CPUMBState, regs[i]), |
2015 |
regnames[i]); |
2016 |
} |
2017 |
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { |
2018 |
cpu_SR[i] = tcg_global_mem_new(TCG_AREG0, |
2019 |
offsetof(CPUMBState, sregs[i]), |
2020 |
special_regnames[i]); |
2021 |
} |
2022 |
} |
2023 |
|
2024 |
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) |
2025 |
{ |
2026 |
env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos]; |
2027 |
} |