Revision 4a8fa5dc hw/pc.c

b/hw/pc.c
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    smm_arg = arg;
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}
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void cpu_smm_update(CPUState *env)
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void cpu_smm_update(CPUX86State *env)
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{
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    if (smm_set && smm_arg && env == first_cpu)
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        smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
......
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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int cpu_get_pic_interrupt(CPUX86State *env)
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{
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    int intno;
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......
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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    CPUState *env = first_cpu;
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    CPUX86State *env = first_cpu;
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    DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
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    if (env->apic_state) {
......
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static void handle_a20_line_change(void *opaque, int irq, int level)
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{
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    CPUState *cpu = opaque;
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    CPUX86State *cpu = opaque;
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    /* XXX: send to all CPUs ? */
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    /* XXX: add logic to handle multiple A20 line sources */
......
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    nb_ne2k++;
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}
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int cpu_is_bsp(CPUState *env)
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int cpu_is_bsp(CPUX86State *env)
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{
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    /* We hard-wire the BSP to the first CPU. */
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    return env->cpu_index == 0;
......
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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{
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    CPUState *s = opaque;
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    CPUX86State *s = opaque;
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    if (level) {
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        cpu_interrupt(s, CPU_INTERRUPT_SMI);
......
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static void pc_cpu_reset(void *opaque)
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{
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    CPUState *env = opaque;
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    CPUX86State *env = opaque;
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    cpu_state_reset(env);
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    env->halted = !cpu_is_bsp(env);
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}
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static CPUState *pc_new_cpu(const char *cpu_model)
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static CPUX86State *pc_new_cpu(const char *cpu_model)
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{
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    CPUState *env;
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    CPUX86State *env;
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    env = cpu_init(cpu_model);
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    if (!env) {
......
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static void cpu_request_exit(void *opaque, int irq, int level)
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{
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    CPUState *env = cpu_single_env;
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    CPUX86State *env = cpu_single_env;
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    if (env && level) {
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        cpu_exit(env);

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