Revision 4a8fa5dc hw/pc.c
b/hw/pc.c | ||
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140 | 140 |
smm_arg = arg; |
141 | 141 |
} |
142 | 142 |
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143 |
void cpu_smm_update(CPUState *env) |
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143 |
void cpu_smm_update(CPUX86State *env)
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144 | 144 |
{ |
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if (smm_set && smm_arg && env == first_cpu) |
146 | 146 |
smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
... | ... | |
148 | 148 |
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149 | 149 |
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150 | 150 |
/* IRQ handling */ |
151 |
int cpu_get_pic_interrupt(CPUState *env) |
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151 |
int cpu_get_pic_interrupt(CPUX86State *env)
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152 | 152 |
{ |
153 | 153 |
int intno; |
154 | 154 |
|
... | ... | |
167 | 167 |
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168 | 168 |
static void pic_irq_request(void *opaque, int irq, int level) |
169 | 169 |
{ |
170 |
CPUState *env = first_cpu; |
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CPUX86State *env = first_cpu;
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171 | 171 |
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172 | 172 |
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
173 | 173 |
if (env->apic_state) { |
... | ... | |
522 | 522 |
|
523 | 523 |
static void handle_a20_line_change(void *opaque, int irq, int level) |
524 | 524 |
{ |
525 |
CPUState *cpu = opaque; |
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CPUX86State *cpu = opaque;
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526 | 526 |
|
527 | 527 |
/* XXX: send to all CPUs ? */ |
528 | 528 |
/* XXX: add logic to handle multiple A20 line sources */ |
... | ... | |
869 | 869 |
nb_ne2k++; |
870 | 870 |
} |
871 | 871 |
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872 |
int cpu_is_bsp(CPUState *env) |
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872 |
int cpu_is_bsp(CPUX86State *env)
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873 | 873 |
{ |
874 | 874 |
/* We hard-wire the BSP to the first CPU. */ |
875 | 875 |
return env->cpu_index == 0; |
... | ... | |
917 | 917 |
|
918 | 918 |
void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
919 | 919 |
{ |
920 |
CPUState *s = opaque; |
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920 |
CPUX86State *s = opaque;
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921 | 921 |
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922 | 922 |
if (level) { |
923 | 923 |
cpu_interrupt(s, CPU_INTERRUPT_SMI); |
... | ... | |
926 | 926 |
|
927 | 927 |
static void pc_cpu_reset(void *opaque) |
928 | 928 |
{ |
929 |
CPUState *env = opaque; |
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929 |
CPUX86State *env = opaque;
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930 | 930 |
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931 | 931 |
cpu_state_reset(env); |
932 | 932 |
env->halted = !cpu_is_bsp(env); |
933 | 933 |
} |
934 | 934 |
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935 |
static CPUState *pc_new_cpu(const char *cpu_model) |
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935 |
static CPUX86State *pc_new_cpu(const char *cpu_model)
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936 | 936 |
{ |
937 |
CPUState *env; |
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937 |
CPUX86State *env;
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938 | 938 |
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939 | 939 |
env = cpu_init(cpu_model); |
940 | 940 |
if (!env) { |
... | ... | |
1070 | 1070 |
|
1071 | 1071 |
static void cpu_request_exit(void *opaque, int irq, int level) |
1072 | 1072 |
{ |
1073 |
CPUState *env = cpu_single_env; |
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1073 |
CPUX86State *env = cpu_single_env;
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1074 | 1074 |
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1075 | 1075 |
if (env && level) { |
1076 | 1076 |
cpu_exit(env); |
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