Revision 4aa5d285
| b/hw/i8254.c | ||
|---|---|---|
| 90 | 90 |
} |
| 91 | 91 |
|
| 92 | 92 |
/* get pit output bit */ |
| 93 |
static int pit_get_out1(PITChannelState *s, int64_t current_time)
|
|
| 93 |
static int pit_get_out(PITChannelState *s, int64_t current_time) |
|
| 94 | 94 |
{
|
| 95 | 95 |
uint64_t d; |
| 96 | 96 |
int out; |
| ... | ... | |
| 122 | 122 |
return out; |
| 123 | 123 |
} |
| 124 | 124 |
|
| 125 |
int pit_get_out(ISADevice *dev, int channel, int64_t current_time) |
|
| 126 |
{
|
|
| 127 |
PITState *pit = DO_UPCAST(PITState, dev, dev); |
|
| 128 |
PITChannelState *s = &pit->channels[channel]; |
|
| 129 |
return pit_get_out1(s, current_time); |
|
| 130 |
} |
|
| 131 |
|
|
| 132 | 125 |
/* return -1 if no transition will occur. */ |
| 133 | 126 |
static int64_t pit_get_next_transition_time(PITChannelState *s, |
| 134 | 127 |
int64_t current_time) |
| ... | ... | |
| 215 | 208 |
s->gate = val; |
| 216 | 209 |
} |
| 217 | 210 |
|
| 218 |
int pit_get_gate(ISADevice *dev, int channel) |
|
| 219 |
{
|
|
| 220 |
PITState *pit = DO_UPCAST(PITState, dev, dev); |
|
| 221 |
PITChannelState *s = &pit->channels[channel]; |
|
| 222 |
return s->gate; |
|
| 223 |
} |
|
| 224 |
|
|
| 225 |
int pit_get_initial_count(ISADevice *dev, int channel) |
|
| 211 |
void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info) |
|
| 226 | 212 |
{
|
| 227 | 213 |
PITState *pit = DO_UPCAST(PITState, dev, dev); |
| 228 | 214 |
PITChannelState *s = &pit->channels[channel]; |
| 229 |
return s->count; |
|
| 230 |
} |
|
| 231 | 215 |
|
| 232 |
int pit_get_mode(ISADevice *dev, int channel) |
|
| 233 |
{
|
|
| 234 |
PITState *pit = DO_UPCAST(PITState, dev, dev); |
|
| 235 |
PITChannelState *s = &pit->channels[channel]; |
|
| 236 |
return s->mode; |
|
| 216 |
info->gate = s->gate; |
|
| 217 |
info->mode = s->mode; |
|
| 218 |
info->initial_count = s->count; |
|
| 219 |
info->out = pit_get_out(s, qemu_get_clock_ns(vm_clock)); |
|
| 237 | 220 |
} |
| 238 | 221 |
|
| 239 | 222 |
static inline void pit_load_count(PITChannelState *s, int val) |
| ... | ... | |
| 274 | 257 |
if (!(val & 0x10) && !s->status_latched) {
|
| 275 | 258 |
/* status latch */ |
| 276 | 259 |
/* XXX: add BCD and null count */ |
| 277 |
s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) | |
|
| 260 |
s->status = |
|
| 261 |
(pit_get_out(s, |
|
| 262 |
qemu_get_clock_ns(vm_clock)) << 7) | |
|
| 278 | 263 |
(s->rw_mode << 4) | |
| 279 | 264 |
(s->mode << 1) | |
| 280 | 265 |
s->bcd; |
| ... | ... | |
| 381 | 366 |
return; |
| 382 | 367 |
} |
| 383 | 368 |
expire_time = pit_get_next_transition_time(s, current_time); |
| 384 |
irq_level = pit_get_out1(s, current_time);
|
|
| 369 |
irq_level = pit_get_out(s, current_time); |
|
| 385 | 370 |
qemu_set_irq(s->irq, irq_level); |
| 386 | 371 |
#ifdef DEBUG_PIT |
| 387 | 372 |
printf("irq_level=%d next_delay=%f\n",
|
| b/hw/i8254.h | ||
|---|---|---|
| 30 | 30 |
|
| 31 | 31 |
#define PIT_FREQ 1193182 |
| 32 | 32 |
|
| 33 |
typedef struct PITChannelInfo {
|
|
| 34 |
int gate; |
|
| 35 |
int mode; |
|
| 36 |
int initial_count; |
|
| 37 |
int out; |
|
| 38 |
} PITChannelInfo; |
|
| 39 |
|
|
| 33 | 40 |
static inline ISADevice *pit_init(ISABus *bus, int base, int isa_irq, |
| 34 | 41 |
qemu_irq alt_irq) |
| 35 | 42 |
{
|
| ... | ... | |
| 45 | 52 |
} |
| 46 | 53 |
|
| 47 | 54 |
void pit_set_gate(ISADevice *dev, int channel, int val); |
| 48 |
int pit_get_gate(ISADevice *dev, int channel); |
|
| 49 |
int pit_get_initial_count(ISADevice *dev, int channel); |
|
| 50 |
int pit_get_mode(ISADevice *dev, int channel); |
|
| 51 |
int pit_get_out(ISADevice *dev, int channel, int64_t current_time); |
|
| 55 |
void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info); |
|
| 52 | 56 |
|
| 53 | 57 |
#endif /* !HW_I8254_H */ |
| b/hw/pcspk.c | ||
|---|---|---|
| 75 | 75 |
static void pcspk_callback(void *opaque, int free) |
| 76 | 76 |
{
|
| 77 | 77 |
PCSpkState *s = opaque; |
| 78 |
PITChannelInfo ch; |
|
| 78 | 79 |
unsigned int n; |
| 79 | 80 |
|
| 80 |
if (pit_get_mode(s->pit, 2) != 3) |
|
| 81 |
pit_get_channel_info(s->pit, 2, &ch); |
|
| 82 |
|
|
| 83 |
if (ch.mode != 3) {
|
|
| 81 | 84 |
return; |
| 85 |
} |
|
| 82 | 86 |
|
| 83 |
n = pit_get_initial_count(s->pit, 2);
|
|
| 87 |
n = ch.initial_count;
|
|
| 84 | 88 |
/* avoid frequencies that are not reproducible with sample rate */ |
| 85 | 89 |
if (n < PCSPK_MIN_COUNT) |
| 86 | 90 |
n = 0; |
| ... | ... | |
| 121 | 125 |
unsigned size) |
| 122 | 126 |
{
|
| 123 | 127 |
PCSpkState *s = opaque; |
| 124 |
int out; |
|
| 128 |
PITChannelInfo ch; |
|
| 129 |
|
|
| 130 |
pit_get_channel_info(s->pit, 2, &ch); |
|
| 125 | 131 |
|
| 126 | 132 |
s->dummy_refresh_clock ^= (1 << 4); |
| 127 |
out = pit_get_out(s->pit, 2, qemu_get_clock_ns(vm_clock)) << 5; |
|
| 128 | 133 |
|
| 129 |
return pit_get_gate(s->pit, 2) | (s->data_on << 1) | s->dummy_refresh_clock | out; |
|
| 134 |
return ch.gate | (s->data_on << 1) | s->dummy_refresh_clock | |
|
| 135 |
(ch.out << 5); |
|
| 130 | 136 |
} |
| 131 | 137 |
|
| 132 | 138 |
static void pcspk_io_write(void *opaque, target_phys_addr_t addr, uint64_t val, |
Also available in: Unified diff