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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 574bbf7b | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | 574bbf7b | bellard | */
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20 | 87ecb68b | pbrook | #include "hw.h" |
21 | 87ecb68b | pbrook | #include "pc.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | bb7e7293 | aurel32 | #include "host-utils.h" |
24 | 574bbf7b | bellard | |
25 | 574bbf7b | bellard | //#define DEBUG_APIC
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26 | 574bbf7b | bellard | |
27 | 574bbf7b | bellard | /* APIC Local Vector Table */
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28 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
29 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
30 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
31 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
32 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
33 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
34 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
35 | 574bbf7b | bellard | |
36 | 574bbf7b | bellard | /* APIC delivery modes */
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37 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
38 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
39 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
40 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
41 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
42 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
43 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
44 | 574bbf7b | bellard | |
45 | d592d303 | bellard | /* APIC destination mode */
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46 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
47 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
48 | d592d303 | bellard | |
49 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
50 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
51 | 574bbf7b | bellard | |
52 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
53 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
54 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
55 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
56 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
57 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
58 | 574bbf7b | bellard | |
59 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
60 | 574bbf7b | bellard | |
61 | 574bbf7b | bellard | #define APIC_SV_ENABLE (1 << 8) |
62 | 574bbf7b | bellard | |
63 | d3e9db93 | bellard | #define MAX_APICS 255 |
64 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
65 | d3e9db93 | bellard | |
66 | 574bbf7b | bellard | typedef struct APICState { |
67 | 574bbf7b | bellard | CPUState *cpu_env; |
68 | 574bbf7b | bellard | uint32_t apicbase; |
69 | 574bbf7b | bellard | uint8_t id; |
70 | d592d303 | bellard | uint8_t arb_id; |
71 | 574bbf7b | bellard | uint8_t tpr; |
72 | 574bbf7b | bellard | uint32_t spurious_vec; |
73 | d592d303 | bellard | uint8_t log_dest; |
74 | d592d303 | bellard | uint8_t dest_mode; |
75 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
76 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
77 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
78 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
79 | 574bbf7b | bellard | uint32_t esr; /* error register */
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80 | 574bbf7b | bellard | uint32_t icr[2];
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81 | 574bbf7b | bellard | |
82 | 574bbf7b | bellard | uint32_t divide_conf; |
83 | 574bbf7b | bellard | int count_shift;
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84 | 574bbf7b | bellard | uint32_t initial_count; |
85 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
86 | 574bbf7b | bellard | QEMUTimer *timer; |
87 | 574bbf7b | bellard | } APICState; |
88 | 574bbf7b | bellard | |
89 | 574bbf7b | bellard | static int apic_io_memory; |
90 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
91 | d592d303 | bellard | static int last_apic_id = 0; |
92 | 73822ec8 | aliguori | static int apic_irq_delivered; |
93 | 73822ec8 | aliguori | |
94 | d592d303 | bellard | |
95 | d592d303 | bellard | static void apic_init_ipi(APICState *s); |
96 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
97 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
98 | 610626af | aliguori | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
99 | 610626af | aliguori | uint8_t dest, uint8_t dest_mode); |
100 | d592d303 | bellard | |
101 | 3b63c04e | aurel32 | /* Find first bit starting from msb */
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102 | 3b63c04e | aurel32 | static int fls_bit(uint32_t value) |
103 | 3b63c04e | aurel32 | { |
104 | 3b63c04e | aurel32 | return 31 - clz32(value); |
105 | 3b63c04e | aurel32 | } |
106 | 3b63c04e | aurel32 | |
107 | e95f5491 | aurel32 | /* Find first bit starting from lsb */
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108 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
109 | d3e9db93 | bellard | { |
110 | bb7e7293 | aurel32 | return ctz32(value);
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111 | d3e9db93 | bellard | } |
112 | d3e9db93 | bellard | |
113 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
114 | d3e9db93 | bellard | { |
115 | d3e9db93 | bellard | int i, mask;
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116 | d3e9db93 | bellard | i = index >> 5;
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117 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
118 | d3e9db93 | bellard | tab[i] |= mask; |
119 | d3e9db93 | bellard | } |
120 | d3e9db93 | bellard | |
121 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
122 | d3e9db93 | bellard | { |
123 | d3e9db93 | bellard | int i, mask;
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124 | d3e9db93 | bellard | i = index >> 5;
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125 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
126 | d3e9db93 | bellard | tab[i] &= ~mask; |
127 | d3e9db93 | bellard | } |
128 | d3e9db93 | bellard | |
129 | 73822ec8 | aliguori | static inline int get_bit(uint32_t *tab, int index) |
130 | 73822ec8 | aliguori | { |
131 | 73822ec8 | aliguori | int i, mask;
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132 | 73822ec8 | aliguori | i = index >> 5;
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133 | 73822ec8 | aliguori | mask = 1 << (index & 0x1f); |
134 | 73822ec8 | aliguori | return !!(tab[i] & mask);
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135 | 73822ec8 | aliguori | } |
136 | 73822ec8 | aliguori | |
137 | 1a7de94a | aurel32 | static void apic_local_deliver(CPUState *env, int vector) |
138 | a5b38b51 | aurel32 | { |
139 | a5b38b51 | aurel32 | APICState *s = env->apic_state; |
140 | a5b38b51 | aurel32 | uint32_t lvt = s->lvt[vector]; |
141 | a5b38b51 | aurel32 | int trigger_mode;
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142 | a5b38b51 | aurel32 | |
143 | a5b38b51 | aurel32 | if (lvt & APIC_LVT_MASKED)
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144 | a5b38b51 | aurel32 | return;
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145 | a5b38b51 | aurel32 | |
146 | a5b38b51 | aurel32 | switch ((lvt >> 8) & 7) { |
147 | a5b38b51 | aurel32 | case APIC_DM_SMI:
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148 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_SMI); |
149 | a5b38b51 | aurel32 | break;
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150 | a5b38b51 | aurel32 | |
151 | a5b38b51 | aurel32 | case APIC_DM_NMI:
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152 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_NMI); |
153 | a5b38b51 | aurel32 | break;
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154 | a5b38b51 | aurel32 | |
155 | a5b38b51 | aurel32 | case APIC_DM_EXTINT:
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156 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
157 | a5b38b51 | aurel32 | break;
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158 | a5b38b51 | aurel32 | |
159 | a5b38b51 | aurel32 | case APIC_DM_FIXED:
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160 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_EDGE; |
161 | a5b38b51 | aurel32 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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162 | a5b38b51 | aurel32 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
163 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_LEVEL; |
164 | a5b38b51 | aurel32 | apic_set_irq(s, lvt & 0xff, trigger_mode);
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165 | a5b38b51 | aurel32 | } |
166 | a5b38b51 | aurel32 | } |
167 | a5b38b51 | aurel32 | |
168 | 1a7de94a | aurel32 | void apic_deliver_pic_intr(CPUState *env, int level) |
169 | 1a7de94a | aurel32 | { |
170 | 1a7de94a | aurel32 | if (level)
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171 | 1a7de94a | aurel32 | apic_local_deliver(env, APIC_LVT_LINT0); |
172 | 1a7de94a | aurel32 | else {
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173 | 1a7de94a | aurel32 | APICState *s = env->apic_state; |
174 | 1a7de94a | aurel32 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
175 | 1a7de94a | aurel32 | |
176 | 1a7de94a | aurel32 | switch ((lvt >> 8) & 7) { |
177 | 1a7de94a | aurel32 | case APIC_DM_FIXED:
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178 | 1a7de94a | aurel32 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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179 | 1a7de94a | aurel32 | break;
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180 | 1a7de94a | aurel32 | reset_bit(s->irr, lvt & 0xff);
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181 | 1a7de94a | aurel32 | /* fall through */
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182 | 1a7de94a | aurel32 | case APIC_DM_EXTINT:
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183 | 1a7de94a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
184 | 1a7de94a | aurel32 | break;
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185 | 1a7de94a | aurel32 | } |
186 | 1a7de94a | aurel32 | } |
187 | 1a7de94a | aurel32 | } |
188 | 1a7de94a | aurel32 | |
189 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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190 | d3e9db93 | bellard | {\ |
191 | d3e9db93 | bellard | int __i, __j, __mask;\
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192 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
193 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
194 | d3e9db93 | bellard | if (__mask) {\
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195 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
196 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
197 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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198 | d3e9db93 | bellard | if (apic) {\
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199 | d3e9db93 | bellard | code;\ |
200 | d3e9db93 | bellard | }\ |
201 | d3e9db93 | bellard | }\ |
202 | d3e9db93 | bellard | }\ |
203 | d3e9db93 | bellard | }\ |
204 | d3e9db93 | bellard | }\ |
205 | d3e9db93 | bellard | } |
206 | d3e9db93 | bellard | |
207 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
208 | d3e9db93 | bellard | uint8_t delivery_mode, |
209 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
210 | d592d303 | bellard | uint8_t trigger_mode) |
211 | d592d303 | bellard | { |
212 | d592d303 | bellard | APICState *apic_iter; |
213 | d592d303 | bellard | |
214 | d592d303 | bellard | switch (delivery_mode) {
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215 | d592d303 | bellard | case APIC_DM_LOWPRI:
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216 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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217 | d3e9db93 | bellard | { |
218 | d3e9db93 | bellard | int i, d;
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219 | d3e9db93 | bellard | d = -1;
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220 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
221 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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222 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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223 | d3e9db93 | bellard | break;
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224 | d3e9db93 | bellard | } |
225 | d3e9db93 | bellard | } |
226 | d3e9db93 | bellard | if (d >= 0) { |
227 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
228 | d3e9db93 | bellard | if (apic_iter) {
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229 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
230 | d3e9db93 | bellard | } |
231 | d3e9db93 | bellard | } |
232 | 8dd69b8f | bellard | } |
233 | d3e9db93 | bellard | return;
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234 | 8dd69b8f | bellard | |
235 | d592d303 | bellard | case APIC_DM_FIXED:
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236 | d592d303 | bellard | break;
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237 | d592d303 | bellard | |
238 | d592d303 | bellard | case APIC_DM_SMI:
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239 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
240 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
241 | e2eb9d3e | aurel32 | return;
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242 | e2eb9d3e | aurel32 | |
243 | d592d303 | bellard | case APIC_DM_NMI:
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244 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
245 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
246 | e2eb9d3e | aurel32 | return;
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247 | d592d303 | bellard | |
248 | d592d303 | bellard | case APIC_DM_INIT:
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249 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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250 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
251 | d3e9db93 | bellard | apic_init_ipi(apic_iter) ); |
252 | d592d303 | bellard | return;
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253 | 3b46e624 | ths | |
254 | d592d303 | bellard | case APIC_DM_EXTINT:
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255 | b1fc0348 | bellard | /* handled in I/O APIC code */
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256 | d592d303 | bellard | break;
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257 | d592d303 | bellard | |
258 | d592d303 | bellard | default:
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259 | d592d303 | bellard | return;
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260 | d592d303 | bellard | } |
261 | d592d303 | bellard | |
262 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
263 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
264 | d592d303 | bellard | } |
265 | 574bbf7b | bellard | |
266 | 610626af | aliguori | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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267 | 610626af | aliguori | uint8_t delivery_mode, uint8_t vector_num, |
268 | 610626af | aliguori | uint8_t polarity, uint8_t trigger_mode) |
269 | 610626af | aliguori | { |
270 | 610626af | aliguori | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
271 | 610626af | aliguori | |
272 | 610626af | aliguori | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
273 | 610626af | aliguori | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
274 | 610626af | aliguori | trigger_mode); |
275 | 610626af | aliguori | } |
276 | 610626af | aliguori | |
277 | 574bbf7b | bellard | void cpu_set_apic_base(CPUState *env, uint64_t val)
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278 | 574bbf7b | bellard | { |
279 | 574bbf7b | bellard | APICState *s = env->apic_state; |
280 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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281 | 26a76461 | bellard | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
282 | 574bbf7b | bellard | #endif
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283 | 2c7c13d4 | aurel32 | if (!s)
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284 | 2c7c13d4 | aurel32 | return;
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285 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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286 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
287 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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288 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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289 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
290 | 574bbf7b | bellard | env->cpuid_features &= ~CPUID_APIC; |
291 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
292 | 574bbf7b | bellard | } |
293 | 574bbf7b | bellard | } |
294 | 574bbf7b | bellard | |
295 | 574bbf7b | bellard | uint64_t cpu_get_apic_base(CPUState *env) |
296 | 574bbf7b | bellard | { |
297 | 574bbf7b | bellard | APICState *s = env->apic_state; |
298 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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299 | 2c7c13d4 | aurel32 | printf("cpu_get_apic_base: %016" PRIx64 "\n", |
300 | 2c7c13d4 | aurel32 | s ? (uint64_t)s->apicbase: 0);
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301 | 574bbf7b | bellard | #endif
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302 | 2c7c13d4 | aurel32 | return s ? s->apicbase : 0; |
303 | 574bbf7b | bellard | } |
304 | 574bbf7b | bellard | |
305 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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306 | 9230e66e | bellard | { |
307 | 9230e66e | bellard | APICState *s = env->apic_state; |
308 | 2c7c13d4 | aurel32 | if (!s)
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309 | 2c7c13d4 | aurel32 | return;
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310 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
311 | d592d303 | bellard | apic_update_irq(s); |
312 | 9230e66e | bellard | } |
313 | 9230e66e | bellard | |
314 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env) |
315 | 9230e66e | bellard | { |
316 | 9230e66e | bellard | APICState *s = env->apic_state; |
317 | 2c7c13d4 | aurel32 | return s ? s->tpr >> 4 : 0; |
318 | 9230e66e | bellard | } |
319 | 9230e66e | bellard | |
320 | d592d303 | bellard | /* return -1 if no bit is set */
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321 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
322 | d592d303 | bellard | { |
323 | d592d303 | bellard | int i;
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324 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
325 | d592d303 | bellard | if (tab[i] != 0) { |
326 | 3b63c04e | aurel32 | return i * 32 + fls_bit(tab[i]); |
327 | d592d303 | bellard | } |
328 | d592d303 | bellard | } |
329 | d592d303 | bellard | return -1; |
330 | d592d303 | bellard | } |
331 | d592d303 | bellard | |
332 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
333 | 574bbf7b | bellard | { |
334 | 574bbf7b | bellard | int tpr, isrv, ppr;
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335 | 574bbf7b | bellard | |
336 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
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337 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
338 | 574bbf7b | bellard | if (isrv < 0) |
339 | 574bbf7b | bellard | isrv = 0;
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340 | 574bbf7b | bellard | isrv >>= 4;
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341 | 574bbf7b | bellard | if (tpr >= isrv)
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342 | 574bbf7b | bellard | ppr = s->tpr; |
343 | 574bbf7b | bellard | else
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344 | 574bbf7b | bellard | ppr = isrv << 4;
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345 | 574bbf7b | bellard | return ppr;
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346 | 574bbf7b | bellard | } |
347 | 574bbf7b | bellard | |
348 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
349 | d592d303 | bellard | { |
350 | d592d303 | bellard | /* XXX: arbitration */
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351 | d592d303 | bellard | return 0; |
352 | d592d303 | bellard | } |
353 | d592d303 | bellard | |
354 | 574bbf7b | bellard | /* signal the CPU if an irq is pending */
|
355 | 574bbf7b | bellard | static void apic_update_irq(APICState *s) |
356 | 574bbf7b | bellard | { |
357 | d592d303 | bellard | int irrv, ppr;
|
358 | d592d303 | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
359 | d592d303 | bellard | return;
|
360 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
361 | 574bbf7b | bellard | if (irrv < 0) |
362 | 574bbf7b | bellard | return;
|
363 | d592d303 | bellard | ppr = apic_get_ppr(s); |
364 | d592d303 | bellard | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
365 | 574bbf7b | bellard | return;
|
366 | 574bbf7b | bellard | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
367 | 574bbf7b | bellard | } |
368 | 574bbf7b | bellard | |
369 | 73822ec8 | aliguori | void apic_reset_irq_delivered(void) |
370 | 73822ec8 | aliguori | { |
371 | 73822ec8 | aliguori | apic_irq_delivered = 0;
|
372 | 73822ec8 | aliguori | } |
373 | 73822ec8 | aliguori | |
374 | 73822ec8 | aliguori | int apic_get_irq_delivered(void) |
375 | 73822ec8 | aliguori | { |
376 | 73822ec8 | aliguori | return apic_irq_delivered;
|
377 | 73822ec8 | aliguori | } |
378 | 73822ec8 | aliguori | |
379 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
380 | 574bbf7b | bellard | { |
381 | 73822ec8 | aliguori | apic_irq_delivered += !get_bit(s->irr, vector_num); |
382 | 73822ec8 | aliguori | |
383 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
384 | 574bbf7b | bellard | if (trigger_mode)
|
385 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
386 | 574bbf7b | bellard | else
|
387 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
388 | 574bbf7b | bellard | apic_update_irq(s); |
389 | 574bbf7b | bellard | } |
390 | 574bbf7b | bellard | |
391 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
392 | 574bbf7b | bellard | { |
393 | 574bbf7b | bellard | int isrv;
|
394 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
395 | 574bbf7b | bellard | if (isrv < 0) |
396 | 574bbf7b | bellard | return;
|
397 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
398 | d592d303 | bellard | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
399 | d592d303 | bellard | set the remote IRR bit for level triggered interrupts. */
|
400 | 574bbf7b | bellard | apic_update_irq(s); |
401 | 574bbf7b | bellard | } |
402 | 574bbf7b | bellard | |
403 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
404 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
405 | d592d303 | bellard | { |
406 | d592d303 | bellard | APICState *apic_iter; |
407 | d3e9db93 | bellard | int i;
|
408 | d592d303 | bellard | |
409 | d592d303 | bellard | if (dest_mode == 0) { |
410 | d3e9db93 | bellard | if (dest == 0xff) { |
411 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
412 | d3e9db93 | bellard | } else {
|
413 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
414 | d3e9db93 | bellard | set_bit(deliver_bitmask, dest); |
415 | d3e9db93 | bellard | } |
416 | d592d303 | bellard | } else {
|
417 | d592d303 | bellard | /* XXX: cluster mode */
|
418 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
419 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
420 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
421 | d3e9db93 | bellard | if (apic_iter) {
|
422 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
423 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
424 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
425 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
426 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
427 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
428 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
429 | d3e9db93 | bellard | } |
430 | d3e9db93 | bellard | } |
431 | d3e9db93 | bellard | } |
432 | d592d303 | bellard | } |
433 | d592d303 | bellard | } |
434 | d592d303 | bellard | } |
435 | d592d303 | bellard | |
436 | d592d303 | bellard | |
437 | d592d303 | bellard | static void apic_init_ipi(APICState *s) |
438 | d592d303 | bellard | { |
439 | d592d303 | bellard | int i;
|
440 | d592d303 | bellard | |
441 | d592d303 | bellard | s->tpr = 0;
|
442 | d592d303 | bellard | s->spurious_vec = 0xff;
|
443 | d592d303 | bellard | s->log_dest = 0;
|
444 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
445 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
446 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
447 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
448 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
449 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
450 | d592d303 | bellard | s->esr = 0;
|
451 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
452 | d592d303 | bellard | s->divide_conf = 0;
|
453 | d592d303 | bellard | s->count_shift = 0;
|
454 | d592d303 | bellard | s->initial_count = 0;
|
455 | d592d303 | bellard | s->initial_count_load_time = 0;
|
456 | d592d303 | bellard | s->next_time = 0;
|
457 | 3003b8bb | aurel32 | |
458 | 3003b8bb | aurel32 | cpu_reset(s->cpu_env); |
459 | 3003b8bb | aurel32 | |
460 | 3003b8bb | aurel32 | if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
|
461 | 3003b8bb | aurel32 | s->cpu_env->halted = 1;
|
462 | d592d303 | bellard | } |
463 | d592d303 | bellard | |
464 | e0fd8781 | bellard | /* send a SIPI message to the CPU to start it */
|
465 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
466 | e0fd8781 | bellard | { |
467 | e0fd8781 | bellard | CPUState *env = s->cpu_env; |
468 | ce5232c5 | bellard | if (!env->halted)
|
469 | e0fd8781 | bellard | return;
|
470 | e0fd8781 | bellard | env->eip = 0;
|
471 | 5fafdf24 | ths | cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, |
472 | e0fd8781 | bellard | 0xffff, 0); |
473 | ce5232c5 | bellard | env->halted = 0;
|
474 | e0fd8781 | bellard | } |
475 | e0fd8781 | bellard | |
476 | d592d303 | bellard | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
477 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
478 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
479 | d592d303 | bellard | { |
480 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
481 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
482 | d592d303 | bellard | APICState *apic_iter; |
483 | d592d303 | bellard | |
484 | e0fd8781 | bellard | switch (dest_shorthand) {
|
485 | d3e9db93 | bellard | case 0: |
486 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
487 | d3e9db93 | bellard | break;
|
488 | d3e9db93 | bellard | case 1: |
489 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
490 | d3e9db93 | bellard | set_bit(deliver_bitmask, s->id); |
491 | d3e9db93 | bellard | break;
|
492 | d3e9db93 | bellard | case 2: |
493 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
494 | d3e9db93 | bellard | break;
|
495 | d3e9db93 | bellard | case 3: |
496 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
497 | d3e9db93 | bellard | reset_bit(deliver_bitmask, s->id); |
498 | d3e9db93 | bellard | break;
|
499 | e0fd8781 | bellard | } |
500 | e0fd8781 | bellard | |
501 | d592d303 | bellard | switch (delivery_mode) {
|
502 | d592d303 | bellard | case APIC_DM_INIT:
|
503 | d592d303 | bellard | { |
504 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
505 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
506 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
507 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
508 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
509 | d592d303 | bellard | return;
|
510 | d592d303 | bellard | } |
511 | d592d303 | bellard | } |
512 | d592d303 | bellard | break;
|
513 | d592d303 | bellard | |
514 | d592d303 | bellard | case APIC_DM_SIPI:
|
515 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
516 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
517 | d592d303 | bellard | return;
|
518 | d592d303 | bellard | } |
519 | d592d303 | bellard | |
520 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
521 | d592d303 | bellard | trigger_mode); |
522 | d592d303 | bellard | } |
523 | d592d303 | bellard | |
524 | 574bbf7b | bellard | int apic_get_interrupt(CPUState *env)
|
525 | 574bbf7b | bellard | { |
526 | 574bbf7b | bellard | APICState *s = env->apic_state; |
527 | 574bbf7b | bellard | int intno;
|
528 | 574bbf7b | bellard | |
529 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
530 | 574bbf7b | bellard | IRQs */
|
531 | 574bbf7b | bellard | if (!s)
|
532 | 574bbf7b | bellard | return -1; |
533 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
534 | 574bbf7b | bellard | return -1; |
535 | 3b46e624 | ths | |
536 | 574bbf7b | bellard | /* XXX: spurious IRQ handling */
|
537 | 574bbf7b | bellard | intno = get_highest_priority_int(s->irr); |
538 | 574bbf7b | bellard | if (intno < 0) |
539 | 574bbf7b | bellard | return -1; |
540 | d592d303 | bellard | if (s->tpr && intno <= s->tpr)
|
541 | d592d303 | bellard | return s->spurious_vec & 0xff; |
542 | b4511723 | bellard | reset_bit(s->irr, intno); |
543 | 574bbf7b | bellard | set_bit(s->isr, intno); |
544 | 574bbf7b | bellard | apic_update_irq(s); |
545 | 574bbf7b | bellard | return intno;
|
546 | 574bbf7b | bellard | } |
547 | 574bbf7b | bellard | |
548 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env)
|
549 | 0e21e12b | ths | { |
550 | 0e21e12b | ths | APICState *s = env->apic_state; |
551 | 0e21e12b | ths | uint32_t lvt0; |
552 | 0e21e12b | ths | |
553 | 0e21e12b | ths | if (!s)
|
554 | 0e21e12b | ths | return -1; |
555 | 0e21e12b | ths | |
556 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
557 | 0e21e12b | ths | |
558 | a5b38b51 | aurel32 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
559 | a5b38b51 | aurel32 | (lvt0 & APIC_LVT_MASKED) == 0)
|
560 | 0e21e12b | ths | return 1; |
561 | 0e21e12b | ths | |
562 | 0e21e12b | ths | return 0; |
563 | 0e21e12b | ths | } |
564 | 0e21e12b | ths | |
565 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
566 | 574bbf7b | bellard | { |
567 | 574bbf7b | bellard | int64_t d; |
568 | 574bbf7b | bellard | uint32_t val; |
569 | 5fafdf24 | ths | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
570 | 574bbf7b | bellard | s->count_shift; |
571 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
572 | 574bbf7b | bellard | /* periodic */
|
573 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
574 | 574bbf7b | bellard | } else {
|
575 | 574bbf7b | bellard | if (d >= s->initial_count)
|
576 | 574bbf7b | bellard | val = 0;
|
577 | 574bbf7b | bellard | else
|
578 | 574bbf7b | bellard | val = s->initial_count - d; |
579 | 574bbf7b | bellard | } |
580 | 574bbf7b | bellard | return val;
|
581 | 574bbf7b | bellard | } |
582 | 574bbf7b | bellard | |
583 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
584 | 574bbf7b | bellard | { |
585 | 574bbf7b | bellard | int64_t next_time, d; |
586 | 3b46e624 | ths | |
587 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
588 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
589 | 574bbf7b | bellard | s->count_shift; |
590 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
591 | 681f8c29 | aliguori | if (!s->initial_count)
|
592 | 681f8c29 | aliguori | goto no_timer;
|
593 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
594 | 574bbf7b | bellard | } else {
|
595 | 574bbf7b | bellard | if (d >= s->initial_count)
|
596 | 574bbf7b | bellard | goto no_timer;
|
597 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
598 | 574bbf7b | bellard | } |
599 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
600 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
601 | 574bbf7b | bellard | s->next_time = next_time; |
602 | 574bbf7b | bellard | } else {
|
603 | 574bbf7b | bellard | no_timer:
|
604 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
605 | 574bbf7b | bellard | } |
606 | 574bbf7b | bellard | } |
607 | 574bbf7b | bellard | |
608 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
609 | 574bbf7b | bellard | { |
610 | 574bbf7b | bellard | APICState *s = opaque; |
611 | 574bbf7b | bellard | |
612 | a5b38b51 | aurel32 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
613 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
614 | 574bbf7b | bellard | } |
615 | 574bbf7b | bellard | |
616 | 574bbf7b | bellard | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
617 | 574bbf7b | bellard | { |
618 | 574bbf7b | bellard | return 0; |
619 | 574bbf7b | bellard | } |
620 | 574bbf7b | bellard | |
621 | 574bbf7b | bellard | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
622 | 574bbf7b | bellard | { |
623 | 574bbf7b | bellard | return 0; |
624 | 574bbf7b | bellard | } |
625 | 574bbf7b | bellard | |
626 | 574bbf7b | bellard | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
627 | 574bbf7b | bellard | { |
628 | 574bbf7b | bellard | } |
629 | 574bbf7b | bellard | |
630 | 574bbf7b | bellard | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
631 | 574bbf7b | bellard | { |
632 | 574bbf7b | bellard | } |
633 | 574bbf7b | bellard | |
634 | 574bbf7b | bellard | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
635 | 574bbf7b | bellard | { |
636 | 574bbf7b | bellard | CPUState *env; |
637 | 574bbf7b | bellard | APICState *s; |
638 | 574bbf7b | bellard | uint32_t val; |
639 | 574bbf7b | bellard | int index;
|
640 | 574bbf7b | bellard | |
641 | 574bbf7b | bellard | env = cpu_single_env; |
642 | 574bbf7b | bellard | if (!env)
|
643 | 574bbf7b | bellard | return 0; |
644 | 574bbf7b | bellard | s = env->apic_state; |
645 | 574bbf7b | bellard | |
646 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
647 | 574bbf7b | bellard | switch(index) {
|
648 | 574bbf7b | bellard | case 0x02: /* id */ |
649 | 574bbf7b | bellard | val = s->id << 24;
|
650 | 574bbf7b | bellard | break;
|
651 | 574bbf7b | bellard | case 0x03: /* version */ |
652 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
653 | 574bbf7b | bellard | break;
|
654 | 574bbf7b | bellard | case 0x08: |
655 | 574bbf7b | bellard | val = s->tpr; |
656 | 574bbf7b | bellard | break;
|
657 | d592d303 | bellard | case 0x09: |
658 | d592d303 | bellard | val = apic_get_arb_pri(s); |
659 | d592d303 | bellard | break;
|
660 | 574bbf7b | bellard | case 0x0a: |
661 | 574bbf7b | bellard | /* ppr */
|
662 | 574bbf7b | bellard | val = apic_get_ppr(s); |
663 | 574bbf7b | bellard | break;
|
664 | b237db36 | aurel32 | case 0x0b: |
665 | b237db36 | aurel32 | val = 0;
|
666 | b237db36 | aurel32 | break;
|
667 | d592d303 | bellard | case 0x0d: |
668 | d592d303 | bellard | val = s->log_dest << 24;
|
669 | d592d303 | bellard | break;
|
670 | d592d303 | bellard | case 0x0e: |
671 | d592d303 | bellard | val = s->dest_mode << 28;
|
672 | d592d303 | bellard | break;
|
673 | 574bbf7b | bellard | case 0x0f: |
674 | 574bbf7b | bellard | val = s->spurious_vec; |
675 | 574bbf7b | bellard | break;
|
676 | 574bbf7b | bellard | case 0x10 ... 0x17: |
677 | 574bbf7b | bellard | val = s->isr[index & 7];
|
678 | 574bbf7b | bellard | break;
|
679 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
680 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
681 | 574bbf7b | bellard | break;
|
682 | 574bbf7b | bellard | case 0x20 ... 0x27: |
683 | 574bbf7b | bellard | val = s->irr[index & 7];
|
684 | 574bbf7b | bellard | break;
|
685 | 574bbf7b | bellard | case 0x28: |
686 | 574bbf7b | bellard | val = s->esr; |
687 | 574bbf7b | bellard | break;
|
688 | 574bbf7b | bellard | case 0x30: |
689 | 574bbf7b | bellard | case 0x31: |
690 | 574bbf7b | bellard | val = s->icr[index & 1];
|
691 | 574bbf7b | bellard | break;
|
692 | e0fd8781 | bellard | case 0x32 ... 0x37: |
693 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
694 | e0fd8781 | bellard | break;
|
695 | 574bbf7b | bellard | case 0x38: |
696 | 574bbf7b | bellard | val = s->initial_count; |
697 | 574bbf7b | bellard | break;
|
698 | 574bbf7b | bellard | case 0x39: |
699 | 574bbf7b | bellard | val = apic_get_current_count(s); |
700 | 574bbf7b | bellard | break;
|
701 | 574bbf7b | bellard | case 0x3e: |
702 | 574bbf7b | bellard | val = s->divide_conf; |
703 | 574bbf7b | bellard | break;
|
704 | 574bbf7b | bellard | default:
|
705 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
706 | 574bbf7b | bellard | val = 0;
|
707 | 574bbf7b | bellard | break;
|
708 | 574bbf7b | bellard | } |
709 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
710 | 574bbf7b | bellard | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
711 | 574bbf7b | bellard | #endif
|
712 | 574bbf7b | bellard | return val;
|
713 | 574bbf7b | bellard | } |
714 | 574bbf7b | bellard | |
715 | 574bbf7b | bellard | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
716 | 574bbf7b | bellard | { |
717 | 574bbf7b | bellard | CPUState *env; |
718 | 574bbf7b | bellard | APICState *s; |
719 | 574bbf7b | bellard | int index;
|
720 | 574bbf7b | bellard | |
721 | 574bbf7b | bellard | env = cpu_single_env; |
722 | 574bbf7b | bellard | if (!env)
|
723 | 574bbf7b | bellard | return;
|
724 | 574bbf7b | bellard | s = env->apic_state; |
725 | 574bbf7b | bellard | |
726 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
727 | 574bbf7b | bellard | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
728 | 574bbf7b | bellard | #endif
|
729 | 574bbf7b | bellard | |
730 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
731 | 574bbf7b | bellard | switch(index) {
|
732 | 574bbf7b | bellard | case 0x02: |
733 | 574bbf7b | bellard | s->id = (val >> 24);
|
734 | 574bbf7b | bellard | break;
|
735 | e0fd8781 | bellard | case 0x03: |
736 | e0fd8781 | bellard | break;
|
737 | 574bbf7b | bellard | case 0x08: |
738 | 574bbf7b | bellard | s->tpr = val; |
739 | d592d303 | bellard | apic_update_irq(s); |
740 | 574bbf7b | bellard | break;
|
741 | e0fd8781 | bellard | case 0x09: |
742 | e0fd8781 | bellard | case 0x0a: |
743 | e0fd8781 | bellard | break;
|
744 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
745 | 574bbf7b | bellard | apic_eoi(s); |
746 | 574bbf7b | bellard | break;
|
747 | d592d303 | bellard | case 0x0d: |
748 | d592d303 | bellard | s->log_dest = val >> 24;
|
749 | d592d303 | bellard | break;
|
750 | d592d303 | bellard | case 0x0e: |
751 | d592d303 | bellard | s->dest_mode = val >> 28;
|
752 | d592d303 | bellard | break;
|
753 | 574bbf7b | bellard | case 0x0f: |
754 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
755 | d592d303 | bellard | apic_update_irq(s); |
756 | 574bbf7b | bellard | break;
|
757 | e0fd8781 | bellard | case 0x10 ... 0x17: |
758 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
759 | e0fd8781 | bellard | case 0x20 ... 0x27: |
760 | e0fd8781 | bellard | case 0x28: |
761 | e0fd8781 | bellard | break;
|
762 | 574bbf7b | bellard | case 0x30: |
763 | d592d303 | bellard | s->icr[0] = val;
|
764 | d592d303 | bellard | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
765 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
766 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
767 | d592d303 | bellard | break;
|
768 | 574bbf7b | bellard | case 0x31: |
769 | d592d303 | bellard | s->icr[1] = val;
|
770 | 574bbf7b | bellard | break;
|
771 | 574bbf7b | bellard | case 0x32 ... 0x37: |
772 | 574bbf7b | bellard | { |
773 | 574bbf7b | bellard | int n = index - 0x32; |
774 | 574bbf7b | bellard | s->lvt[n] = val; |
775 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
776 | 574bbf7b | bellard | apic_timer_update(s, qemu_get_clock(vm_clock)); |
777 | 574bbf7b | bellard | } |
778 | 574bbf7b | bellard | break;
|
779 | 574bbf7b | bellard | case 0x38: |
780 | 574bbf7b | bellard | s->initial_count = val; |
781 | 574bbf7b | bellard | s->initial_count_load_time = qemu_get_clock(vm_clock); |
782 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
783 | 574bbf7b | bellard | break;
|
784 | e0fd8781 | bellard | case 0x39: |
785 | e0fd8781 | bellard | break;
|
786 | 574bbf7b | bellard | case 0x3e: |
787 | 574bbf7b | bellard | { |
788 | 574bbf7b | bellard | int v;
|
789 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
790 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
791 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
792 | 574bbf7b | bellard | } |
793 | 574bbf7b | bellard | break;
|
794 | 574bbf7b | bellard | default:
|
795 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
796 | 574bbf7b | bellard | break;
|
797 | 574bbf7b | bellard | } |
798 | 574bbf7b | bellard | } |
799 | 574bbf7b | bellard | |
800 | d592d303 | bellard | static void apic_save(QEMUFile *f, void *opaque) |
801 | d592d303 | bellard | { |
802 | d592d303 | bellard | APICState *s = opaque; |
803 | d592d303 | bellard | int i;
|
804 | d592d303 | bellard | |
805 | d592d303 | bellard | qemu_put_be32s(f, &s->apicbase); |
806 | d592d303 | bellard | qemu_put_8s(f, &s->id); |
807 | d592d303 | bellard | qemu_put_8s(f, &s->arb_id); |
808 | d592d303 | bellard | qemu_put_8s(f, &s->tpr); |
809 | d592d303 | bellard | qemu_put_be32s(f, &s->spurious_vec); |
810 | d592d303 | bellard | qemu_put_8s(f, &s->log_dest); |
811 | d592d303 | bellard | qemu_put_8s(f, &s->dest_mode); |
812 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
813 | d592d303 | bellard | qemu_put_be32s(f, &s->isr[i]); |
814 | d592d303 | bellard | qemu_put_be32s(f, &s->tmr[i]); |
815 | d592d303 | bellard | qemu_put_be32s(f, &s->irr[i]); |
816 | d592d303 | bellard | } |
817 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
818 | d592d303 | bellard | qemu_put_be32s(f, &s->lvt[i]); |
819 | d592d303 | bellard | } |
820 | d592d303 | bellard | qemu_put_be32s(f, &s->esr); |
821 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[0]);
|
822 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[1]);
|
823 | d592d303 | bellard | qemu_put_be32s(f, &s->divide_conf); |
824 | bee8d684 | ths | qemu_put_be32(f, s->count_shift); |
825 | d592d303 | bellard | qemu_put_be32s(f, &s->initial_count); |
826 | bee8d684 | ths | qemu_put_be64(f, s->initial_count_load_time); |
827 | bee8d684 | ths | qemu_put_be64(f, s->next_time); |
828 | e6cf6a8c | bellard | |
829 | e6cf6a8c | bellard | qemu_put_timer(f, s->timer); |
830 | d592d303 | bellard | } |
831 | d592d303 | bellard | |
832 | d592d303 | bellard | static int apic_load(QEMUFile *f, void *opaque, int version_id) |
833 | d592d303 | bellard | { |
834 | d592d303 | bellard | APICState *s = opaque; |
835 | d592d303 | bellard | int i;
|
836 | d592d303 | bellard | |
837 | e6cf6a8c | bellard | if (version_id > 2) |
838 | d592d303 | bellard | return -EINVAL;
|
839 | d592d303 | bellard | |
840 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
841 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
842 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
843 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
844 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
845 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
846 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
847 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
848 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
849 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
850 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
851 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
852 | d592d303 | bellard | } |
853 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
854 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
855 | d592d303 | bellard | } |
856 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
857 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
858 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
859 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
860 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
861 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
862 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
863 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
864 | e6cf6a8c | bellard | |
865 | e6cf6a8c | bellard | if (version_id >= 2) |
866 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
867 | d592d303 | bellard | return 0; |
868 | d592d303 | bellard | } |
869 | 574bbf7b | bellard | |
870 | d592d303 | bellard | static void apic_reset(void *opaque) |
871 | d592d303 | bellard | { |
872 | d592d303 | bellard | APICState *s = opaque; |
873 | fec5fa02 | aurel32 | |
874 | fec5fa02 | aurel32 | s->apicbase = 0xfee00000 |
|
875 | fec5fa02 | aurel32 | (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
|
876 | fec5fa02 | aurel32 | |
877 | d592d303 | bellard | apic_init_ipi(s); |
878 | 0e21e12b | ths | |
879 | a5b38b51 | aurel32 | if (s->id == 0) { |
880 | a5b38b51 | aurel32 | /*
|
881 | a5b38b51 | aurel32 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
882 | a5b38b51 | aurel32 | * time typically by BIOS, so PIC interrupt can be delivered to the
|
883 | a5b38b51 | aurel32 | * processor when local APIC is enabled.
|
884 | a5b38b51 | aurel32 | */
|
885 | a5b38b51 | aurel32 | s->lvt[APIC_LVT_LINT0] = 0x700;
|
886 | a5b38b51 | aurel32 | } |
887 | d592d303 | bellard | } |
888 | 574bbf7b | bellard | |
889 | 574bbf7b | bellard | static CPUReadMemoryFunc *apic_mem_read[3] = { |
890 | 574bbf7b | bellard | apic_mem_readb, |
891 | 574bbf7b | bellard | apic_mem_readw, |
892 | 574bbf7b | bellard | apic_mem_readl, |
893 | 574bbf7b | bellard | }; |
894 | 574bbf7b | bellard | |
895 | 574bbf7b | bellard | static CPUWriteMemoryFunc *apic_mem_write[3] = { |
896 | 574bbf7b | bellard | apic_mem_writeb, |
897 | 574bbf7b | bellard | apic_mem_writew, |
898 | 574bbf7b | bellard | apic_mem_writel, |
899 | 574bbf7b | bellard | }; |
900 | 574bbf7b | bellard | |
901 | 574bbf7b | bellard | int apic_init(CPUState *env)
|
902 | 574bbf7b | bellard | { |
903 | 574bbf7b | bellard | APICState *s; |
904 | 574bbf7b | bellard | |
905 | d3e9db93 | bellard | if (last_apic_id >= MAX_APICS)
|
906 | d3e9db93 | bellard | return -1; |
907 | d592d303 | bellard | s = qemu_mallocz(sizeof(APICState));
|
908 | 574bbf7b | bellard | env->apic_state = s; |
909 | d592d303 | bellard | s->id = last_apic_id++; |
910 | eae7629b | ths | env->cpuid_apic_id = s->id; |
911 | 574bbf7b | bellard | s->cpu_env = env; |
912 | 574bbf7b | bellard | |
913 | a5b38b51 | aurel32 | apic_reset(s); |
914 | 0e21e12b | ths | |
915 | d592d303 | bellard | /* XXX: mapping more APICs at the same memory location */
|
916 | 574bbf7b | bellard | if (apic_io_memory == 0) { |
917 | 574bbf7b | bellard | /* NOTE: the APIC is directly connected to the CPU - it is not
|
918 | 574bbf7b | bellard | on the global memory bus. */
|
919 | 5fafdf24 | ths | apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
|
920 | 574bbf7b | bellard | apic_mem_write, NULL);
|
921 | d592d303 | bellard | cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
922 | d592d303 | bellard | apic_io_memory); |
923 | 574bbf7b | bellard | } |
924 | 574bbf7b | bellard | s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
925 | d592d303 | bellard | |
926 | be0164f2 | ths | register_savevm("apic", s->id, 2, apic_save, apic_load, s); |
927 | d592d303 | bellard | qemu_register_reset(apic_reset, s); |
928 | 3b46e624 | ths | |
929 | d3e9db93 | bellard | local_apics[s->id] = s; |
930 | d592d303 | bellard | return 0; |
931 | d592d303 | bellard | } |