root / target-m68k / cpu.h @ 4b16eb9d
History | View | Annotate | Download (7.2 kB)
1 | e6e5906b | pbrook | /*
|
---|---|---|---|
2 | e6e5906b | pbrook | * m68k virtual CPU header
|
3 | 5fafdf24 | ths | *
|
4 | 0633879f | pbrook | * Copyright (c) 2005-2007 CodeSourcery
|
5 | e6e5906b | pbrook | * Written by Paul Brook
|
6 | e6e5906b | pbrook | *
|
7 | e6e5906b | pbrook | * This library is free software; you can redistribute it and/or
|
8 | e6e5906b | pbrook | * modify it under the terms of the GNU Lesser General Public
|
9 | e6e5906b | pbrook | * License as published by the Free Software Foundation; either
|
10 | e6e5906b | pbrook | * version 2 of the License, or (at your option) any later version.
|
11 | e6e5906b | pbrook | *
|
12 | e6e5906b | pbrook | * This library is distributed in the hope that it will be useful,
|
13 | e6e5906b | pbrook | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 | e6e5906b | pbrook | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 | e6e5906b | pbrook | * General Public License for more details.
|
16 | e6e5906b | pbrook | *
|
17 | e6e5906b | pbrook | * You should have received a copy of the GNU Lesser General Public
|
18 | e6e5906b | pbrook | * License along with this library; if not, write to the Free Software
|
19 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
20 | e6e5906b | pbrook | */
|
21 | e6e5906b | pbrook | #ifndef CPU_M68K_H
|
22 | e6e5906b | pbrook | #define CPU_M68K_H
|
23 | e6e5906b | pbrook | |
24 | e6e5906b | pbrook | #define TARGET_LONG_BITS 32 |
25 | e6e5906b | pbrook | |
26 | c2764719 | pbrook | #define CPUState struct CPUM68KState |
27 | c2764719 | pbrook | |
28 | e6e5906b | pbrook | #include "cpu-defs.h" |
29 | e6e5906b | pbrook | |
30 | e6e5906b | pbrook | #include "softfloat.h" |
31 | e6e5906b | pbrook | |
32 | e6e5906b | pbrook | #define MAX_QREGS 32 |
33 | e6e5906b | pbrook | |
34 | e6e5906b | pbrook | #define TARGET_HAS_ICE 1 |
35 | e6e5906b | pbrook | |
36 | 9042c0e2 | ths | #define ELF_MACHINE EM_68K
|
37 | 9042c0e2 | ths | |
38 | e6e5906b | pbrook | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
39 | e6e5906b | pbrook | #define EXCP_ADDRESS 3 /* Address error. */ |
40 | e6e5906b | pbrook | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
41 | e6e5906b | pbrook | #define EXCP_DIV0 5 /* Divide by zero */ |
42 | e6e5906b | pbrook | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
43 | e6e5906b | pbrook | #define EXCP_TRACE 9 |
44 | e6e5906b | pbrook | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
45 | e6e5906b | pbrook | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
46 | e6e5906b | pbrook | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
47 | e6e5906b | pbrook | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
48 | e6e5906b | pbrook | #define EXCP_FORMAT 14 /* RTE format error. */ |
49 | e6e5906b | pbrook | #define EXCP_UNINITIALIZED 15 |
50 | e6e5906b | pbrook | #define EXCP_TRAP0 32 /* User trap #0. */ |
51 | e6e5906b | pbrook | #define EXCP_TRAP15 47 /* User trap #15. */ |
52 | e6e5906b | pbrook | #define EXCP_UNSUPPORTED 61 |
53 | e6e5906b | pbrook | #define EXCP_ICE 13 |
54 | e6e5906b | pbrook | |
55 | 0633879f | pbrook | #define EXCP_RTE 0x100 |
56 | a87295e8 | pbrook | #define EXCP_HALT_INSN 0x101 |
57 | 0633879f | pbrook | |
58 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
59 | 6ebbf390 | j_mayer | |
60 | e6e5906b | pbrook | typedef struct CPUM68KState { |
61 | e6e5906b | pbrook | uint32_t dregs[8];
|
62 | e6e5906b | pbrook | uint32_t aregs[8];
|
63 | e6e5906b | pbrook | uint32_t pc; |
64 | e6e5906b | pbrook | uint32_t sr; |
65 | e6e5906b | pbrook | |
66 | 20dcee94 | pbrook | /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
|
67 | 20dcee94 | pbrook | int current_sp;
|
68 | 20dcee94 | pbrook | uint32_t sp[2];
|
69 | 20dcee94 | pbrook | |
70 | e6e5906b | pbrook | /* Condition flags. */
|
71 | e6e5906b | pbrook | uint32_t cc_op; |
72 | e6e5906b | pbrook | uint32_t cc_dest; |
73 | e6e5906b | pbrook | uint32_t cc_src; |
74 | e6e5906b | pbrook | uint32_t cc_x; |
75 | e6e5906b | pbrook | |
76 | e6e5906b | pbrook | float64 fregs[8];
|
77 | e6e5906b | pbrook | float64 fp_result; |
78 | e6e5906b | pbrook | uint32_t fpcr; |
79 | e6e5906b | pbrook | uint32_t fpsr; |
80 | e6e5906b | pbrook | float_status fp_status; |
81 | e6e5906b | pbrook | |
82 | acf930aa | pbrook | uint64_t mactmp; |
83 | acf930aa | pbrook | /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
|
84 | acf930aa | pbrook | two 8-bit parts. We store a single 64-bit value and
|
85 | acf930aa | pbrook | rearrange/extend this when changing modes. */
|
86 | acf930aa | pbrook | uint64_t macc[4];
|
87 | acf930aa | pbrook | uint32_t macsr; |
88 | acf930aa | pbrook | uint32_t mac_mask; |
89 | acf930aa | pbrook | |
90 | e6e5906b | pbrook | /* Temporary storage for DIV helpers. */
|
91 | e6e5906b | pbrook | uint32_t div1; |
92 | e6e5906b | pbrook | uint32_t div2; |
93 | 3b46e624 | ths | |
94 | e6e5906b | pbrook | /* MMU status. */
|
95 | e6e5906b | pbrook | struct {
|
96 | e6e5906b | pbrook | uint32_t ar; |
97 | e6e5906b | pbrook | } mmu; |
98 | 0633879f | pbrook | |
99 | 0633879f | pbrook | /* Control registers. */
|
100 | 0633879f | pbrook | uint32_t vbr; |
101 | 0633879f | pbrook | uint32_t mbar; |
102 | 0633879f | pbrook | uint32_t rambar0; |
103 | 20dcee94 | pbrook | uint32_t cacr; |
104 | 0633879f | pbrook | |
105 | e6e5906b | pbrook | /* ??? remove this. */
|
106 | e6e5906b | pbrook | uint32_t t1; |
107 | e6e5906b | pbrook | |
108 | 0633879f | pbrook | int pending_vector;
|
109 | 0633879f | pbrook | int pending_level;
|
110 | e6e5906b | pbrook | |
111 | e6e5906b | pbrook | uint32_t qregs[MAX_QREGS]; |
112 | e6e5906b | pbrook | |
113 | e6e5906b | pbrook | CPU_COMMON |
114 | aaed909a | bellard | |
115 | aaed909a | bellard | uint32_t features; |
116 | e6e5906b | pbrook | } CPUM68KState; |
117 | e6e5906b | pbrook | |
118 | e1f3808e | pbrook | void m68k_tcg_init(void); |
119 | aaed909a | bellard | CPUM68KState *cpu_m68k_init(const char *cpu_model); |
120 | e6e5906b | pbrook | int cpu_m68k_exec(CPUM68KState *s);
|
121 | e6e5906b | pbrook | void cpu_m68k_close(CPUM68KState *s);
|
122 | 0633879f | pbrook | void do_interrupt(int is_hw); |
123 | e6e5906b | pbrook | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
124 | e6e5906b | pbrook | signal handlers to inform the virtual CPU of exceptions. non zero
|
125 | e6e5906b | pbrook | is returned if the signal was handled by the virtual CPU. */
|
126 | 5fafdf24 | ths | int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
127 | e6e5906b | pbrook | void *puc);
|
128 | e6e5906b | pbrook | void cpu_m68k_flush_flags(CPUM68KState *, int); |
129 | e6e5906b | pbrook | |
130 | e6e5906b | pbrook | enum {
|
131 | e6e5906b | pbrook | CC_OP_DYNAMIC, /* Use env->cc_op */
|
132 | e6e5906b | pbrook | CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
|
133 | e6e5906b | pbrook | CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
|
134 | e6e5906b | pbrook | CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
|
135 | e6e5906b | pbrook | CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
|
136 | e6e5906b | pbrook | CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
|
137 | e6e5906b | pbrook | CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
|
138 | e6e5906b | pbrook | CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
|
139 | e6e5906b | pbrook | CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
|
140 | e1f3808e | pbrook | CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
|
141 | e6e5906b | pbrook | }; |
142 | e6e5906b | pbrook | |
143 | e6e5906b | pbrook | #define CCF_C 0x01 |
144 | e6e5906b | pbrook | #define CCF_V 0x02 |
145 | e6e5906b | pbrook | #define CCF_Z 0x04 |
146 | e6e5906b | pbrook | #define CCF_N 0x08 |
147 | 0633879f | pbrook | #define CCF_X 0x10 |
148 | 0633879f | pbrook | |
149 | 0633879f | pbrook | #define SR_I_SHIFT 8 |
150 | 0633879f | pbrook | #define SR_I 0x0700 |
151 | 0633879f | pbrook | #define SR_M 0x1000 |
152 | 0633879f | pbrook | #define SR_S 0x2000 |
153 | 0633879f | pbrook | #define SR_T 0x8000 |
154 | e6e5906b | pbrook | |
155 | 20dcee94 | pbrook | #define M68K_SSP 0 |
156 | 20dcee94 | pbrook | #define M68K_USP 1 |
157 | 20dcee94 | pbrook | |
158 | 20dcee94 | pbrook | /* CACR fields are implementation defined, but some bits are common. */
|
159 | 20dcee94 | pbrook | #define M68K_CACR_EUSP 0x10 |
160 | 20dcee94 | pbrook | |
161 | acf930aa | pbrook | #define MACSR_PAV0 0x100 |
162 | acf930aa | pbrook | #define MACSR_OMC 0x080 |
163 | acf930aa | pbrook | #define MACSR_SU 0x040 |
164 | acf930aa | pbrook | #define MACSR_FI 0x020 |
165 | acf930aa | pbrook | #define MACSR_RT 0x010 |
166 | acf930aa | pbrook | #define MACSR_N 0x008 |
167 | acf930aa | pbrook | #define MACSR_Z 0x004 |
168 | acf930aa | pbrook | #define MACSR_V 0x002 |
169 | acf930aa | pbrook | #define MACSR_EV 0x001 |
170 | acf930aa | pbrook | |
171 | 0633879f | pbrook | void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); |
172 | acf930aa | pbrook | void m68k_set_macsr(CPUM68KState *env, uint32_t val);
|
173 | 20dcee94 | pbrook | void m68k_switch_sp(CPUM68KState *env);
|
174 | e6e5906b | pbrook | |
175 | e6e5906b | pbrook | #define M68K_FPCR_PREC (1 << 6) |
176 | e6e5906b | pbrook | |
177 | a87295e8 | pbrook | void do_m68k_semihosting(CPUM68KState *env, int nr); |
178 | a87295e8 | pbrook | |
179 | d315c888 | pbrook | /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
|
180 | d315c888 | pbrook | Each feature covers the subset of instructions common to the
|
181 | d315c888 | pbrook | ISA revisions mentioned. */
|
182 | d315c888 | pbrook | |
183 | 0402f767 | pbrook | enum m68k_features {
|
184 | 0402f767 | pbrook | M68K_FEATURE_CF_ISA_A, |
185 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
|
186 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
187 | d315c888 | pbrook | M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
|
188 | 0402f767 | pbrook | M68K_FEATURE_CF_FPU, |
189 | 0402f767 | pbrook | M68K_FEATURE_CF_MAC, |
190 | 0402f767 | pbrook | M68K_FEATURE_CF_EMAC, |
191 | d315c888 | pbrook | M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
|
192 | d315c888 | pbrook | M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
|
193 | e6dbd3b3 | pbrook | M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
|
194 | e6dbd3b3 | pbrook | M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
|
195 | 0402f767 | pbrook | }; |
196 | 0402f767 | pbrook | |
197 | 0402f767 | pbrook | static inline int m68k_feature(CPUM68KState *env, int feature) |
198 | 0402f767 | pbrook | { |
199 | 0402f767 | pbrook | return (env->features & (1u << feature)) != 0; |
200 | 0402f767 | pbrook | } |
201 | 0402f767 | pbrook | |
202 | 0402f767 | pbrook | void register_m68k_insns (CPUM68KState *env);
|
203 | 0402f767 | pbrook | |
204 | e6e5906b | pbrook | #ifdef CONFIG_USER_ONLY
|
205 | e6e5906b | pbrook | /* Linux uses 8k pages. */
|
206 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 13 |
207 | e6e5906b | pbrook | #else
|
208 | 5fafdf24 | ths | /* Smallest TLB entry size is 1k. */
|
209 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 10 |
210 | e6e5906b | pbrook | #endif
|
211 | 9467d44c | ths | |
212 | 9467d44c | ths | #define cpu_init cpu_m68k_init
|
213 | 9467d44c | ths | #define cpu_exec cpu_m68k_exec
|
214 | 9467d44c | ths | #define cpu_gen_code cpu_m68k_gen_code
|
215 | 9467d44c | ths | #define cpu_signal_handler cpu_m68k_signal_handler
|
216 | 9467d44c | ths | |
217 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
218 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
|
219 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
|
220 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
221 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
222 | 6ebbf390 | j_mayer | { |
223 | 6ebbf390 | j_mayer | return (env->sr & SR_S) == 0 ? 1 : 0; |
224 | 6ebbf390 | j_mayer | } |
225 | 6ebbf390 | j_mayer | |
226 | aaedd1f9 | aurel32 | int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
227 | aaedd1f9 | aurel32 | int mmu_idx, int is_softmmu); |
228 | aaedd1f9 | aurel32 | |
229 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
|
230 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
231 | 6e68e076 | pbrook | { |
232 | f8ed7070 | pbrook | if (newsp)
|
233 | 6e68e076 | pbrook | env->aregs[7] = newsp;
|
234 | 6e68e076 | pbrook | env->dregs[0] = 0; |
235 | 6e68e076 | pbrook | } |
236 | 6e68e076 | pbrook | #endif
|
237 | 6e68e076 | pbrook | |
238 | e6e5906b | pbrook | #include "cpu-all.h" |
239 | 622ed360 | aliguori | #include "exec-all.h" |
240 | 622ed360 | aliguori | |
241 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
242 | 622ed360 | aliguori | { |
243 | 622ed360 | aliguori | env->pc = tb->pc; |
244 | 622ed360 | aliguori | } |
245 | e6e5906b | pbrook | |
246 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
247 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
248 | 6b917547 | aliguori | { |
249 | 6b917547 | aliguori | *pc = env->pc; |
250 | 6b917547 | aliguori | *cs_base = 0;
|
251 | 6b917547 | aliguori | *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
|
252 | 6b917547 | aliguori | | (env->sr & SR_S) /* Bit 13 */
|
253 | 6b917547 | aliguori | | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
254 | 6b917547 | aliguori | } |
255 | 6b917547 | aliguori | |
256 | e6e5906b | pbrook | #endif |