root / hw / omap_dss.c @ 4b16eb9d
History | View | Annotate | Download (31.3 kB)
1 |
/*
|
---|---|
2 |
* OMAP2 Display Subsystem.
|
3 |
*
|
4 |
* Copyright (C) 2008 Nokia Corporation
|
5 |
* Written by Andrzej Zaborowski <andrew@openedhand.com>
|
6 |
*
|
7 |
* This program is free software; you can redistribute it and/or
|
8 |
* modify it under the terms of the GNU General Public License as
|
9 |
* published by the Free Software Foundation; either version 2 or
|
10 |
* (at your option) version 3 of the License.
|
11 |
*
|
12 |
* This program is distributed in the hope that it will be useful,
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 |
* GNU General Public License for more details.
|
16 |
*
|
17 |
* You should have received a copy of the GNU General Public License along
|
18 |
* with this program; if not, write to the Free Software Foundation, Inc.,
|
19 |
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
20 |
*/
|
21 |
#include "hw.h" |
22 |
#include "console.h" |
23 |
#include "omap.h" |
24 |
|
25 |
struct omap_dss_s {
|
26 |
qemu_irq irq; |
27 |
qemu_irq drq; |
28 |
DisplayState *state; |
29 |
|
30 |
int autoidle;
|
31 |
int control;
|
32 |
int enable;
|
33 |
|
34 |
struct omap_dss_panel_s {
|
35 |
int enable;
|
36 |
int nx;
|
37 |
int ny;
|
38 |
|
39 |
int x;
|
40 |
int y;
|
41 |
} dig, lcd; |
42 |
|
43 |
struct {
|
44 |
uint32_t idlemode; |
45 |
uint32_t irqst; |
46 |
uint32_t irqen; |
47 |
uint32_t control; |
48 |
uint32_t config; |
49 |
uint32_t capable; |
50 |
uint32_t timing[4];
|
51 |
int line;
|
52 |
uint32_t bg[2];
|
53 |
uint32_t trans[2];
|
54 |
|
55 |
struct omap_dss_plane_s {
|
56 |
int enable;
|
57 |
int bpp;
|
58 |
int posx;
|
59 |
int posy;
|
60 |
int nx;
|
61 |
int ny;
|
62 |
|
63 |
target_phys_addr_t addr[3];
|
64 |
|
65 |
uint32_t attr; |
66 |
uint32_t tresh; |
67 |
int rowinc;
|
68 |
int colinc;
|
69 |
int wininc;
|
70 |
} l[3];
|
71 |
|
72 |
int invalidate;
|
73 |
uint16_t palette[256];
|
74 |
} dispc; |
75 |
|
76 |
struct {
|
77 |
int idlemode;
|
78 |
uint32_t control; |
79 |
int enable;
|
80 |
int pixels;
|
81 |
int busy;
|
82 |
int skiplines;
|
83 |
uint16_t rxbuf; |
84 |
uint32_t config[2];
|
85 |
uint32_t time[4];
|
86 |
uint32_t data[6];
|
87 |
uint16_t vsync; |
88 |
uint16_t hsync; |
89 |
struct rfbi_chip_s *chip[2]; |
90 |
} rfbi; |
91 |
}; |
92 |
|
93 |
static void omap_dispc_interrupt_update(struct omap_dss_s *s) |
94 |
{ |
95 |
qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen); |
96 |
} |
97 |
|
98 |
static void omap_rfbi_reset(struct omap_dss_s *s) |
99 |
{ |
100 |
s->rfbi.idlemode = 0;
|
101 |
s->rfbi.control = 2;
|
102 |
s->rfbi.enable = 0;
|
103 |
s->rfbi.pixels = 0;
|
104 |
s->rfbi.skiplines = 0;
|
105 |
s->rfbi.busy = 0;
|
106 |
s->rfbi.config[0] = 0x00310000; |
107 |
s->rfbi.config[1] = 0x00310000; |
108 |
s->rfbi.time[0] = 0; |
109 |
s->rfbi.time[1] = 0; |
110 |
s->rfbi.time[2] = 0; |
111 |
s->rfbi.time[3] = 0; |
112 |
s->rfbi.data[0] = 0; |
113 |
s->rfbi.data[1] = 0; |
114 |
s->rfbi.data[2] = 0; |
115 |
s->rfbi.data[3] = 0; |
116 |
s->rfbi.data[4] = 0; |
117 |
s->rfbi.data[5] = 0; |
118 |
s->rfbi.vsync = 0;
|
119 |
s->rfbi.hsync = 0;
|
120 |
} |
121 |
|
122 |
void omap_dss_reset(struct omap_dss_s *s) |
123 |
{ |
124 |
s->autoidle = 0;
|
125 |
s->control = 0;
|
126 |
s->enable = 0;
|
127 |
|
128 |
s->dig.enable = 0;
|
129 |
s->dig.nx = 1;
|
130 |
s->dig.ny = 1;
|
131 |
|
132 |
s->lcd.enable = 0;
|
133 |
s->lcd.nx = 1;
|
134 |
s->lcd.ny = 1;
|
135 |
|
136 |
s->dispc.idlemode = 0;
|
137 |
s->dispc.irqst = 0;
|
138 |
s->dispc.irqen = 0;
|
139 |
s->dispc.control = 0;
|
140 |
s->dispc.config = 0;
|
141 |
s->dispc.capable = 0x161;
|
142 |
s->dispc.timing[0] = 0; |
143 |
s->dispc.timing[1] = 0; |
144 |
s->dispc.timing[2] = 0; |
145 |
s->dispc.timing[3] = 0; |
146 |
s->dispc.line = 0;
|
147 |
s->dispc.bg[0] = 0; |
148 |
s->dispc.bg[1] = 0; |
149 |
s->dispc.trans[0] = 0; |
150 |
s->dispc.trans[1] = 0; |
151 |
|
152 |
s->dispc.l[0].enable = 0; |
153 |
s->dispc.l[0].bpp = 0; |
154 |
s->dispc.l[0].addr[0] = 0; |
155 |
s->dispc.l[0].addr[1] = 0; |
156 |
s->dispc.l[0].addr[2] = 0; |
157 |
s->dispc.l[0].posx = 0; |
158 |
s->dispc.l[0].posy = 0; |
159 |
s->dispc.l[0].nx = 1; |
160 |
s->dispc.l[0].ny = 1; |
161 |
s->dispc.l[0].attr = 0; |
162 |
s->dispc.l[0].tresh = 0; |
163 |
s->dispc.l[0].rowinc = 1; |
164 |
s->dispc.l[0].colinc = 1; |
165 |
s->dispc.l[0].wininc = 0; |
166 |
|
167 |
omap_rfbi_reset(s); |
168 |
omap_dispc_interrupt_update(s); |
169 |
} |
170 |
|
171 |
static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) |
172 |
{ |
173 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
174 |
|
175 |
switch (addr) {
|
176 |
case 0x00: /* DSS_REVISIONNUMBER */ |
177 |
return 0x20; |
178 |
|
179 |
case 0x10: /* DSS_SYSCONFIG */ |
180 |
return s->autoidle;
|
181 |
|
182 |
case 0x14: /* DSS_SYSSTATUS */ |
183 |
return 1; /* RESETDONE */ |
184 |
|
185 |
case 0x40: /* DSS_CONTROL */ |
186 |
return s->control;
|
187 |
|
188 |
case 0x50: /* DSS_PSA_LCD_REG_1 */ |
189 |
case 0x54: /* DSS_PSA_LCD_REG_2 */ |
190 |
case 0x58: /* DSS_PSA_VIDEO_REG */ |
191 |
/* TODO: fake some values when appropriate s->control bits are set */
|
192 |
return 0; |
193 |
|
194 |
case 0x5c: /* DSS_STATUS */ |
195 |
return 1 + (s->control & 1); |
196 |
|
197 |
default:
|
198 |
break;
|
199 |
} |
200 |
OMAP_BAD_REG(addr); |
201 |
return 0; |
202 |
} |
203 |
|
204 |
static void omap_diss_write(void *opaque, target_phys_addr_t addr, |
205 |
uint32_t value) |
206 |
{ |
207 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
208 |
|
209 |
switch (addr) {
|
210 |
case 0x00: /* DSS_REVISIONNUMBER */ |
211 |
case 0x14: /* DSS_SYSSTATUS */ |
212 |
case 0x50: /* DSS_PSA_LCD_REG_1 */ |
213 |
case 0x54: /* DSS_PSA_LCD_REG_2 */ |
214 |
case 0x58: /* DSS_PSA_VIDEO_REG */ |
215 |
case 0x5c: /* DSS_STATUS */ |
216 |
OMAP_RO_REG(addr); |
217 |
break;
|
218 |
|
219 |
case 0x10: /* DSS_SYSCONFIG */ |
220 |
if (value & 2) /* SOFTRESET */ |
221 |
omap_dss_reset(s); |
222 |
s->autoidle = value & 1;
|
223 |
break;
|
224 |
|
225 |
case 0x40: /* DSS_CONTROL */ |
226 |
s->control = value & 0x3dd;
|
227 |
break;
|
228 |
|
229 |
default:
|
230 |
OMAP_BAD_REG(addr); |
231 |
} |
232 |
} |
233 |
|
234 |
static CPUReadMemoryFunc *omap_diss1_readfn[] = {
|
235 |
omap_badwidth_read32, |
236 |
omap_badwidth_read32, |
237 |
omap_diss_read, |
238 |
}; |
239 |
|
240 |
static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
|
241 |
omap_badwidth_write32, |
242 |
omap_badwidth_write32, |
243 |
omap_diss_write, |
244 |
}; |
245 |
|
246 |
static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) |
247 |
{ |
248 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
249 |
|
250 |
switch (addr) {
|
251 |
case 0x000: /* DISPC_REVISION */ |
252 |
return 0x20; |
253 |
|
254 |
case 0x010: /* DISPC_SYSCONFIG */ |
255 |
return s->dispc.idlemode;
|
256 |
|
257 |
case 0x014: /* DISPC_SYSSTATUS */ |
258 |
return 1; /* RESETDONE */ |
259 |
|
260 |
case 0x018: /* DISPC_IRQSTATUS */ |
261 |
return s->dispc.irqst;
|
262 |
|
263 |
case 0x01c: /* DISPC_IRQENABLE */ |
264 |
return s->dispc.irqen;
|
265 |
|
266 |
case 0x040: /* DISPC_CONTROL */ |
267 |
return s->dispc.control;
|
268 |
|
269 |
case 0x044: /* DISPC_CONFIG */ |
270 |
return s->dispc.config;
|
271 |
|
272 |
case 0x048: /* DISPC_CAPABLE */ |
273 |
return s->dispc.capable;
|
274 |
|
275 |
case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
276 |
return s->dispc.bg[0]; |
277 |
case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
278 |
return s->dispc.bg[1]; |
279 |
case 0x054: /* DISPC_TRANS_COLOR0 */ |
280 |
return s->dispc.trans[0]; |
281 |
case 0x058: /* DISPC_TRANS_COLOR1 */ |
282 |
return s->dispc.trans[1]; |
283 |
|
284 |
case 0x05c: /* DISPC_LINE_STATUS */ |
285 |
return 0x7ff; |
286 |
case 0x060: /* DISPC_LINE_NUMBER */ |
287 |
return s->dispc.line;
|
288 |
|
289 |
case 0x064: /* DISPC_TIMING_H */ |
290 |
return s->dispc.timing[0]; |
291 |
case 0x068: /* DISPC_TIMING_V */ |
292 |
return s->dispc.timing[1]; |
293 |
case 0x06c: /* DISPC_POL_FREQ */ |
294 |
return s->dispc.timing[2]; |
295 |
case 0x070: /* DISPC_DIVISOR */ |
296 |
return s->dispc.timing[3]; |
297 |
|
298 |
case 0x078: /* DISPC_SIZE_DIG */ |
299 |
return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1); |
300 |
case 0x07c: /* DISPC_SIZE_LCD */ |
301 |
return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1); |
302 |
|
303 |
case 0x080: /* DISPC_GFX_BA0 */ |
304 |
return s->dispc.l[0].addr[0]; |
305 |
case 0x084: /* DISPC_GFX_BA1 */ |
306 |
return s->dispc.l[0].addr[1]; |
307 |
case 0x088: /* DISPC_GFX_POSITION */ |
308 |
return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx; |
309 |
case 0x08c: /* DISPC_GFX_SIZE */ |
310 |
return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1); |
311 |
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
312 |
return s->dispc.l[0].attr; |
313 |
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
314 |
return s->dispc.l[0].tresh; |
315 |
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */ |
316 |
return 256; |
317 |
case 0x0ac: /* DISPC_GFX_ROW_INC */ |
318 |
return s->dispc.l[0].rowinc; |
319 |
case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
320 |
return s->dispc.l[0].colinc; |
321 |
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
322 |
return s->dispc.l[0].wininc; |
323 |
case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
324 |
return s->dispc.l[0].addr[2]; |
325 |
|
326 |
case 0x0bc: /* DISPC_VID1_BA0 */ |
327 |
case 0x0c0: /* DISPC_VID1_BA1 */ |
328 |
case 0x0c4: /* DISPC_VID1_POSITION */ |
329 |
case 0x0c8: /* DISPC_VID1_SIZE */ |
330 |
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
331 |
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
332 |
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */ |
333 |
case 0x0d8: /* DISPC_VID1_ROW_INC */ |
334 |
case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
335 |
case 0x0e0: /* DISPC_VID1_FIR */ |
336 |
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
337 |
case 0x0e8: /* DISPC_VID1_ACCU0 */ |
338 |
case 0x0ec: /* DISPC_VID1_ACCU1 */ |
339 |
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
340 |
case 0x14c: /* DISPC_VID2_BA0 */ |
341 |
case 0x150: /* DISPC_VID2_BA1 */ |
342 |
case 0x154: /* DISPC_VID2_POSITION */ |
343 |
case 0x158: /* DISPC_VID2_SIZE */ |
344 |
case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
345 |
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
346 |
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */ |
347 |
case 0x168: /* DISPC_VID2_ROW_INC */ |
348 |
case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
349 |
case 0x170: /* DISPC_VID2_FIR */ |
350 |
case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
351 |
case 0x178: /* DISPC_VID2_ACCU0 */ |
352 |
case 0x17c: /* DISPC_VID2_ACCU1 */ |
353 |
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
354 |
case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
355 |
case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
356 |
case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
357 |
return 0; |
358 |
|
359 |
default:
|
360 |
break;
|
361 |
} |
362 |
OMAP_BAD_REG(addr); |
363 |
return 0; |
364 |
} |
365 |
|
366 |
static void omap_disc_write(void *opaque, target_phys_addr_t addr, |
367 |
uint32_t value) |
368 |
{ |
369 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
370 |
|
371 |
switch (addr) {
|
372 |
case 0x010: /* DISPC_SYSCONFIG */ |
373 |
if (value & 2) /* SOFTRESET */ |
374 |
omap_dss_reset(s); |
375 |
s->dispc.idlemode = value & 0x301b;
|
376 |
break;
|
377 |
|
378 |
case 0x018: /* DISPC_IRQSTATUS */ |
379 |
s->dispc.irqst &= ~value; |
380 |
omap_dispc_interrupt_update(s); |
381 |
break;
|
382 |
|
383 |
case 0x01c: /* DISPC_IRQENABLE */ |
384 |
s->dispc.irqen = value & 0xffff;
|
385 |
omap_dispc_interrupt_update(s); |
386 |
break;
|
387 |
|
388 |
case 0x040: /* DISPC_CONTROL */ |
389 |
s->dispc.control = value & 0x07ff9fff;
|
390 |
s->dig.enable = (value >> 1) & 1; |
391 |
s->lcd.enable = (value >> 0) & 1; |
392 |
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */ |
393 |
if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) |
394 |
fprintf(stderr, "%s: Overlay Optimization when no overlay "
|
395 |
"region effectively exists leads to "
|
396 |
"unpredictable behaviour!\n", __FUNCTION__);
|
397 |
if (value & (1 << 6)) { /* GODIGITAL */ |
398 |
/* XXX: Shadowed fields are:
|
399 |
* s->dispc.config
|
400 |
* s->dispc.capable
|
401 |
* s->dispc.bg[0]
|
402 |
* s->dispc.bg[1]
|
403 |
* s->dispc.trans[0]
|
404 |
* s->dispc.trans[1]
|
405 |
* s->dispc.line
|
406 |
* s->dispc.timing[0]
|
407 |
* s->dispc.timing[1]
|
408 |
* s->dispc.timing[2]
|
409 |
* s->dispc.timing[3]
|
410 |
* s->lcd.nx
|
411 |
* s->lcd.ny
|
412 |
* s->dig.nx
|
413 |
* s->dig.ny
|
414 |
* s->dispc.l[0].addr[0]
|
415 |
* s->dispc.l[0].addr[1]
|
416 |
* s->dispc.l[0].addr[2]
|
417 |
* s->dispc.l[0].posx
|
418 |
* s->dispc.l[0].posy
|
419 |
* s->dispc.l[0].nx
|
420 |
* s->dispc.l[0].ny
|
421 |
* s->dispc.l[0].tresh
|
422 |
* s->dispc.l[0].rowinc
|
423 |
* s->dispc.l[0].colinc
|
424 |
* s->dispc.l[0].wininc
|
425 |
* All they need to be loaded here from their shadow registers.
|
426 |
*/
|
427 |
} |
428 |
if (value & (1 << 5)) { /* GOLCD */ |
429 |
/* XXX: Likewise for LCD here. */
|
430 |
} |
431 |
s->dispc.invalidate = 1;
|
432 |
break;
|
433 |
|
434 |
case 0x044: /* DISPC_CONFIG */ |
435 |
s->dispc.config = value & 0x3fff;
|
436 |
/* XXX:
|
437 |
* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
|
438 |
* bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
|
439 |
*/
|
440 |
s->dispc.invalidate = 1;
|
441 |
break;
|
442 |
|
443 |
case 0x048: /* DISPC_CAPABLE */ |
444 |
s->dispc.capable = value & 0x3ff;
|
445 |
break;
|
446 |
|
447 |
case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
448 |
s->dispc.bg[0] = value & 0xffffff; |
449 |
s->dispc.invalidate = 1;
|
450 |
break;
|
451 |
case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
452 |
s->dispc.bg[1] = value & 0xffffff; |
453 |
s->dispc.invalidate = 1;
|
454 |
break;
|
455 |
case 0x054: /* DISPC_TRANS_COLOR0 */ |
456 |
s->dispc.trans[0] = value & 0xffffff; |
457 |
s->dispc.invalidate = 1;
|
458 |
break;
|
459 |
case 0x058: /* DISPC_TRANS_COLOR1 */ |
460 |
s->dispc.trans[1] = value & 0xffffff; |
461 |
s->dispc.invalidate = 1;
|
462 |
break;
|
463 |
|
464 |
case 0x060: /* DISPC_LINE_NUMBER */ |
465 |
s->dispc.line = value & 0x7ff;
|
466 |
break;
|
467 |
|
468 |
case 0x064: /* DISPC_TIMING_H */ |
469 |
s->dispc.timing[0] = value & 0x0ff0ff3f; |
470 |
break;
|
471 |
case 0x068: /* DISPC_TIMING_V */ |
472 |
s->dispc.timing[1] = value & 0x0ff0ff3f; |
473 |
break;
|
474 |
case 0x06c: /* DISPC_POL_FREQ */ |
475 |
s->dispc.timing[2] = value & 0x0003ffff; |
476 |
break;
|
477 |
case 0x070: /* DISPC_DIVISOR */ |
478 |
s->dispc.timing[3] = value & 0x00ff00ff; |
479 |
break;
|
480 |
|
481 |
case 0x078: /* DISPC_SIZE_DIG */ |
482 |
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
483 |
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
484 |
s->dispc.invalidate = 1;
|
485 |
break;
|
486 |
case 0x07c: /* DISPC_SIZE_LCD */ |
487 |
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
488 |
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
489 |
s->dispc.invalidate = 1;
|
490 |
break;
|
491 |
case 0x080: /* DISPC_GFX_BA0 */ |
492 |
s->dispc.l[0].addr[0] = (target_phys_addr_t) value; |
493 |
s->dispc.invalidate = 1;
|
494 |
break;
|
495 |
case 0x084: /* DISPC_GFX_BA1 */ |
496 |
s->dispc.l[0].addr[1] = (target_phys_addr_t) value; |
497 |
s->dispc.invalidate = 1;
|
498 |
break;
|
499 |
case 0x088: /* DISPC_GFX_POSITION */ |
500 |
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */ |
501 |
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */ |
502 |
s->dispc.invalidate = 1;
|
503 |
break;
|
504 |
case 0x08c: /* DISPC_GFX_SIZE */ |
505 |
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */ |
506 |
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */ |
507 |
s->dispc.invalidate = 1;
|
508 |
break;
|
509 |
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
510 |
s->dispc.l[0].attr = value & 0x7ff; |
511 |
if (value & (3 << 9)) |
512 |
fprintf(stderr, "%s: Big-endian pixel format not supported\n",
|
513 |
__FUNCTION__); |
514 |
s->dispc.l[0].enable = value & 1; |
515 |
s->dispc.l[0].bpp = (value >> 1) & 0xf; |
516 |
s->dispc.invalidate = 1;
|
517 |
break;
|
518 |
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
519 |
s->dispc.l[0].tresh = value & 0x01ff01ff; |
520 |
break;
|
521 |
case 0x0ac: /* DISPC_GFX_ROW_INC */ |
522 |
s->dispc.l[0].rowinc = value;
|
523 |
s->dispc.invalidate = 1;
|
524 |
break;
|
525 |
case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
526 |
s->dispc.l[0].colinc = value;
|
527 |
s->dispc.invalidate = 1;
|
528 |
break;
|
529 |
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
530 |
s->dispc.l[0].wininc = value;
|
531 |
break;
|
532 |
case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
533 |
s->dispc.l[0].addr[2] = (target_phys_addr_t) value; |
534 |
s->dispc.invalidate = 1;
|
535 |
break;
|
536 |
|
537 |
case 0x0bc: /* DISPC_VID1_BA0 */ |
538 |
case 0x0c0: /* DISPC_VID1_BA1 */ |
539 |
case 0x0c4: /* DISPC_VID1_POSITION */ |
540 |
case 0x0c8: /* DISPC_VID1_SIZE */ |
541 |
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
542 |
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
543 |
case 0x0d8: /* DISPC_VID1_ROW_INC */ |
544 |
case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
545 |
case 0x0e0: /* DISPC_VID1_FIR */ |
546 |
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
547 |
case 0x0e8: /* DISPC_VID1_ACCU0 */ |
548 |
case 0x0ec: /* DISPC_VID1_ACCU1 */ |
549 |
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
550 |
case 0x14c: /* DISPC_VID2_BA0 */ |
551 |
case 0x150: /* DISPC_VID2_BA1 */ |
552 |
case 0x154: /* DISPC_VID2_POSITION */ |
553 |
case 0x158: /* DISPC_VID2_SIZE */ |
554 |
case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
555 |
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
556 |
case 0x168: /* DISPC_VID2_ROW_INC */ |
557 |
case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
558 |
case 0x170: /* DISPC_VID2_FIR */ |
559 |
case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
560 |
case 0x178: /* DISPC_VID2_ACCU0 */ |
561 |
case 0x17c: /* DISPC_VID2_ACCU1 */ |
562 |
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
563 |
case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
564 |
case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
565 |
case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
566 |
break;
|
567 |
|
568 |
default:
|
569 |
OMAP_BAD_REG(addr); |
570 |
} |
571 |
} |
572 |
|
573 |
static CPUReadMemoryFunc *omap_disc1_readfn[] = {
|
574 |
omap_badwidth_read32, |
575 |
omap_badwidth_read32, |
576 |
omap_disc_read, |
577 |
}; |
578 |
|
579 |
static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
|
580 |
omap_badwidth_write32, |
581 |
omap_badwidth_write32, |
582 |
omap_disc_write, |
583 |
}; |
584 |
|
585 |
static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
586 |
{ |
587 |
if (!s->rfbi.busy)
|
588 |
return;
|
589 |
|
590 |
/* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
|
591 |
|
592 |
s->rfbi.busy = 0;
|
593 |
} |
594 |
|
595 |
static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
596 |
{ |
597 |
void *data;
|
598 |
target_phys_addr_t len; |
599 |
target_phys_addr_t data_addr; |
600 |
int pitch;
|
601 |
static void *bounce_buffer; |
602 |
static target_phys_addr_t bounce_len;
|
603 |
|
604 |
if (!s->rfbi.enable || s->rfbi.busy)
|
605 |
return;
|
606 |
|
607 |
if (s->rfbi.control & (1 << 1)) { /* BYPASS */ |
608 |
/* TODO: in non-Bypass mode we probably need to just assert the
|
609 |
* DRQ and wait for DMA to write the pixels. */
|
610 |
fprintf(stderr, "%s: Bypass mode unimplemented\n", __FUNCTION__);
|
611 |
return;
|
612 |
} |
613 |
|
614 |
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */ |
615 |
return;
|
616 |
/* TODO: check that LCD output is enabled in DISPC. */
|
617 |
|
618 |
s->rfbi.busy = 1;
|
619 |
|
620 |
len = s->rfbi.pixels * 2;
|
621 |
|
622 |
data_addr = s->dispc.l[0].addr[0]; |
623 |
data = cpu_physical_memory_map(data_addr, &len, 0);
|
624 |
if (data && len != s->rfbi.pixels * 2) { |
625 |
cpu_physical_memory_unmap(data, len, 0, 0); |
626 |
data = NULL;
|
627 |
len = s->rfbi.pixels * 2;
|
628 |
} |
629 |
if (!data) {
|
630 |
if (len > bounce_len) {
|
631 |
bounce_buffer = qemu_realloc(bounce_buffer, len); |
632 |
} |
633 |
data = bounce_buffer; |
634 |
cpu_physical_memory_read(data_addr, data, len); |
635 |
} |
636 |
|
637 |
/* TODO bpp */
|
638 |
s->rfbi.pixels = 0;
|
639 |
|
640 |
/* TODO: negative values */
|
641 |
pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2; |
642 |
|
643 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
644 |
s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch); |
645 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
646 |
s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); |
647 |
|
648 |
if (data != bounce_buffer) {
|
649 |
cpu_physical_memory_unmap(data, len, 0, len);
|
650 |
} |
651 |
|
652 |
omap_rfbi_transfer_stop(s); |
653 |
|
654 |
/* TODO */
|
655 |
s->dispc.irqst |= 1; /* FRAMEDONE */ |
656 |
omap_dispc_interrupt_update(s); |
657 |
} |
658 |
|
659 |
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) |
660 |
{ |
661 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
662 |
|
663 |
switch (addr) {
|
664 |
case 0x00: /* RFBI_REVISION */ |
665 |
return 0x10; |
666 |
|
667 |
case 0x10: /* RFBI_SYSCONFIG */ |
668 |
return s->rfbi.idlemode;
|
669 |
|
670 |
case 0x14: /* RFBI_SYSSTATUS */ |
671 |
return 1 | (s->rfbi.busy << 8); /* RESETDONE */ |
672 |
|
673 |
case 0x40: /* RFBI_CONTROL */ |
674 |
return s->rfbi.control;
|
675 |
|
676 |
case 0x44: /* RFBI_PIXELCNT */ |
677 |
return s->rfbi.pixels;
|
678 |
|
679 |
case 0x48: /* RFBI_LINE_NUMBER */ |
680 |
return s->rfbi.skiplines;
|
681 |
|
682 |
case 0x58: /* RFBI_READ */ |
683 |
case 0x5c: /* RFBI_STATUS */ |
684 |
return s->rfbi.rxbuf;
|
685 |
|
686 |
case 0x60: /* RFBI_CONFIG0 */ |
687 |
return s->rfbi.config[0]; |
688 |
case 0x64: /* RFBI_ONOFF_TIME0 */ |
689 |
return s->rfbi.time[0]; |
690 |
case 0x68: /* RFBI_CYCLE_TIME0 */ |
691 |
return s->rfbi.time[1]; |
692 |
case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
693 |
return s->rfbi.data[0]; |
694 |
case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
695 |
return s->rfbi.data[1]; |
696 |
case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
697 |
return s->rfbi.data[2]; |
698 |
|
699 |
case 0x78: /* RFBI_CONFIG1 */ |
700 |
return s->rfbi.config[1]; |
701 |
case 0x7c: /* RFBI_ONOFF_TIME1 */ |
702 |
return s->rfbi.time[2]; |
703 |
case 0x80: /* RFBI_CYCLE_TIME1 */ |
704 |
return s->rfbi.time[3]; |
705 |
case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
706 |
return s->rfbi.data[3]; |
707 |
case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
708 |
return s->rfbi.data[4]; |
709 |
case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
710 |
return s->rfbi.data[5]; |
711 |
|
712 |
case 0x90: /* RFBI_VSYNC_WIDTH */ |
713 |
return s->rfbi.vsync;
|
714 |
case 0x94: /* RFBI_HSYNC_WIDTH */ |
715 |
return s->rfbi.hsync;
|
716 |
} |
717 |
OMAP_BAD_REG(addr); |
718 |
return 0; |
719 |
} |
720 |
|
721 |
static void omap_rfbi_write(void *opaque, target_phys_addr_t addr, |
722 |
uint32_t value) |
723 |
{ |
724 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
725 |
|
726 |
switch (addr) {
|
727 |
case 0x10: /* RFBI_SYSCONFIG */ |
728 |
if (value & 2) /* SOFTRESET */ |
729 |
omap_rfbi_reset(s); |
730 |
s->rfbi.idlemode = value & 0x19;
|
731 |
break;
|
732 |
|
733 |
case 0x40: /* RFBI_CONTROL */ |
734 |
s->rfbi.control = value & 0xf;
|
735 |
s->rfbi.enable = value & 1;
|
736 |
if (value & (1 << 4) && /* ITE */ |
737 |
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) |
738 |
omap_rfbi_transfer_start(s); |
739 |
break;
|
740 |
|
741 |
case 0x44: /* RFBI_PIXELCNT */ |
742 |
s->rfbi.pixels = value; |
743 |
break;
|
744 |
|
745 |
case 0x48: /* RFBI_LINE_NUMBER */ |
746 |
s->rfbi.skiplines = value & 0x7ff;
|
747 |
break;
|
748 |
|
749 |
case 0x4c: /* RFBI_CMD */ |
750 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
751 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff); |
752 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
753 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff); |
754 |
break;
|
755 |
case 0x50: /* RFBI_PARAM */ |
756 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
757 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
758 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
759 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
760 |
break;
|
761 |
case 0x54: /* RFBI_DATA */ |
762 |
/* TODO: take into account the format set up in s->rfbi.config[?] and
|
763 |
* s->rfbi.data[?], but special-case the most usual scenario so that
|
764 |
* speed doesn't suffer. */
|
765 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) { |
766 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
767 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16); |
768 |
} |
769 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) { |
770 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
771 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16); |
772 |
} |
773 |
if (!-- s->rfbi.pixels)
|
774 |
omap_rfbi_transfer_stop(s); |
775 |
break;
|
776 |
case 0x58: /* RFBI_READ */ |
777 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
778 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
779 |
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
780 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
781 |
if (!-- s->rfbi.pixels)
|
782 |
omap_rfbi_transfer_stop(s); |
783 |
break;
|
784 |
|
785 |
case 0x5c: /* RFBI_STATUS */ |
786 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
787 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
788 |
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
789 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
790 |
if (!-- s->rfbi.pixels)
|
791 |
omap_rfbi_transfer_stop(s); |
792 |
break;
|
793 |
|
794 |
case 0x60: /* RFBI_CONFIG0 */ |
795 |
s->rfbi.config[0] = value & 0x003f1fff; |
796 |
break;
|
797 |
|
798 |
case 0x64: /* RFBI_ONOFF_TIME0 */ |
799 |
s->rfbi.time[0] = value & 0x3fffffff; |
800 |
break;
|
801 |
case 0x68: /* RFBI_CYCLE_TIME0 */ |
802 |
s->rfbi.time[1] = value & 0x0fffffff; |
803 |
break;
|
804 |
case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
805 |
s->rfbi.data[0] = value & 0x0f1f0f1f; |
806 |
break;
|
807 |
case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
808 |
s->rfbi.data[1] = value & 0x0f1f0f1f; |
809 |
break;
|
810 |
case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
811 |
s->rfbi.data[2] = value & 0x0f1f0f1f; |
812 |
break;
|
813 |
case 0x78: /* RFBI_CONFIG1 */ |
814 |
s->rfbi.config[1] = value & 0x003f1fff; |
815 |
break;
|
816 |
|
817 |
case 0x7c: /* RFBI_ONOFF_TIME1 */ |
818 |
s->rfbi.time[2] = value & 0x3fffffff; |
819 |
break;
|
820 |
case 0x80: /* RFBI_CYCLE_TIME1 */ |
821 |
s->rfbi.time[3] = value & 0x0fffffff; |
822 |
break;
|
823 |
case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
824 |
s->rfbi.data[3] = value & 0x0f1f0f1f; |
825 |
break;
|
826 |
case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
827 |
s->rfbi.data[4] = value & 0x0f1f0f1f; |
828 |
break;
|
829 |
case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
830 |
s->rfbi.data[5] = value & 0x0f1f0f1f; |
831 |
break;
|
832 |
|
833 |
case 0x90: /* RFBI_VSYNC_WIDTH */ |
834 |
s->rfbi.vsync = value & 0xffff;
|
835 |
break;
|
836 |
case 0x94: /* RFBI_HSYNC_WIDTH */ |
837 |
s->rfbi.hsync = value & 0xffff;
|
838 |
break;
|
839 |
|
840 |
default:
|
841 |
OMAP_BAD_REG(addr); |
842 |
} |
843 |
} |
844 |
|
845 |
static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
|
846 |
omap_badwidth_read32, |
847 |
omap_badwidth_read32, |
848 |
omap_rfbi_read, |
849 |
}; |
850 |
|
851 |
static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
|
852 |
omap_badwidth_write32, |
853 |
omap_badwidth_write32, |
854 |
omap_rfbi_write, |
855 |
}; |
856 |
|
857 |
static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) |
858 |
{ |
859 |
switch (addr) {
|
860 |
case 0x00: /* REV_ID */ |
861 |
case 0x04: /* STATUS */ |
862 |
case 0x08: /* F_CONTROL */ |
863 |
case 0x10: /* VIDOUT_CTRL */ |
864 |
case 0x14: /* SYNC_CTRL */ |
865 |
case 0x1c: /* LLEN */ |
866 |
case 0x20: /* FLENS */ |
867 |
case 0x24: /* HFLTR_CTRL */ |
868 |
case 0x28: /* CC_CARR_WSS_CARR */ |
869 |
case 0x2c: /* C_PHASE */ |
870 |
case 0x30: /* GAIN_U */ |
871 |
case 0x34: /* GAIN_V */ |
872 |
case 0x38: /* GAIN_Y */ |
873 |
case 0x3c: /* BLACK_LEVEL */ |
874 |
case 0x40: /* BLANK_LEVEL */ |
875 |
case 0x44: /* X_COLOR */ |
876 |
case 0x48: /* M_CONTROL */ |
877 |
case 0x4c: /* BSTAMP_WSS_DATA */ |
878 |
case 0x50: /* S_CARR */ |
879 |
case 0x54: /* LINE21 */ |
880 |
case 0x58: /* LN_SEL */ |
881 |
case 0x5c: /* L21__WC_CTL */ |
882 |
case 0x60: /* HTRIGGER_VTRIGGER */ |
883 |
case 0x64: /* SAVID__EAVID */ |
884 |
case 0x68: /* FLEN__FAL */ |
885 |
case 0x6c: /* LAL__PHASE_RESET */ |
886 |
case 0x70: /* HS_INT_START_STOP_X */ |
887 |
case 0x74: /* HS_EXT_START_STOP_X */ |
888 |
case 0x78: /* VS_INT_START_X */ |
889 |
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
890 |
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
891 |
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
892 |
case 0x88: /* VS_EXT_STOP_Y */ |
893 |
case 0x90: /* AVID_START_STOP_X */ |
894 |
case 0x94: /* AVID_START_STOP_Y */ |
895 |
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
896 |
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
897 |
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
898 |
case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
899 |
case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
900 |
case 0xb8: /* GEN_CTRL */ |
901 |
case 0xc4: /* DAC_TST__DAC_A */ |
902 |
case 0xc8: /* DAC_B__DAC_C */ |
903 |
return 0; |
904 |
|
905 |
default:
|
906 |
break;
|
907 |
} |
908 |
OMAP_BAD_REG(addr); |
909 |
return 0; |
910 |
} |
911 |
|
912 |
static void omap_venc_write(void *opaque, target_phys_addr_t addr, |
913 |
uint32_t value) |
914 |
{ |
915 |
switch (addr) {
|
916 |
case 0x08: /* F_CONTROL */ |
917 |
case 0x10: /* VIDOUT_CTRL */ |
918 |
case 0x14: /* SYNC_CTRL */ |
919 |
case 0x1c: /* LLEN */ |
920 |
case 0x20: /* FLENS */ |
921 |
case 0x24: /* HFLTR_CTRL */ |
922 |
case 0x28: /* CC_CARR_WSS_CARR */ |
923 |
case 0x2c: /* C_PHASE */ |
924 |
case 0x30: /* GAIN_U */ |
925 |
case 0x34: /* GAIN_V */ |
926 |
case 0x38: /* GAIN_Y */ |
927 |
case 0x3c: /* BLACK_LEVEL */ |
928 |
case 0x40: /* BLANK_LEVEL */ |
929 |
case 0x44: /* X_COLOR */ |
930 |
case 0x48: /* M_CONTROL */ |
931 |
case 0x4c: /* BSTAMP_WSS_DATA */ |
932 |
case 0x50: /* S_CARR */ |
933 |
case 0x54: /* LINE21 */ |
934 |
case 0x58: /* LN_SEL */ |
935 |
case 0x5c: /* L21__WC_CTL */ |
936 |
case 0x60: /* HTRIGGER_VTRIGGER */ |
937 |
case 0x64: /* SAVID__EAVID */ |
938 |
case 0x68: /* FLEN__FAL */ |
939 |
case 0x6c: /* LAL__PHASE_RESET */ |
940 |
case 0x70: /* HS_INT_START_STOP_X */ |
941 |
case 0x74: /* HS_EXT_START_STOP_X */ |
942 |
case 0x78: /* VS_INT_START_X */ |
943 |
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
944 |
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
945 |
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
946 |
case 0x88: /* VS_EXT_STOP_Y */ |
947 |
case 0x90: /* AVID_START_STOP_X */ |
948 |
case 0x94: /* AVID_START_STOP_Y */ |
949 |
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
950 |
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
951 |
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
952 |
case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
953 |
case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
954 |
case 0xb8: /* GEN_CTRL */ |
955 |
case 0xc4: /* DAC_TST__DAC_A */ |
956 |
case 0xc8: /* DAC_B__DAC_C */ |
957 |
break;
|
958 |
|
959 |
default:
|
960 |
OMAP_BAD_REG(addr); |
961 |
} |
962 |
} |
963 |
|
964 |
static CPUReadMemoryFunc *omap_venc1_readfn[] = {
|
965 |
omap_badwidth_read32, |
966 |
omap_badwidth_read32, |
967 |
omap_venc_read, |
968 |
}; |
969 |
|
970 |
static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
|
971 |
omap_badwidth_write32, |
972 |
omap_badwidth_write32, |
973 |
omap_venc_write, |
974 |
}; |
975 |
|
976 |
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) |
977 |
{ |
978 |
switch (addr) {
|
979 |
case 0x0a8: /* SBIMERRLOGA */ |
980 |
case 0x0b0: /* SBIMERRLOG */ |
981 |
case 0x190: /* SBIMSTATE */ |
982 |
case 0x198: /* SBTMSTATE_L */ |
983 |
case 0x19c: /* SBTMSTATE_H */ |
984 |
case 0x1a8: /* SBIMCONFIG_L */ |
985 |
case 0x1ac: /* SBIMCONFIG_H */ |
986 |
case 0x1f8: /* SBID_L */ |
987 |
case 0x1fc: /* SBID_H */ |
988 |
return 0; |
989 |
|
990 |
default:
|
991 |
break;
|
992 |
} |
993 |
OMAP_BAD_REG(addr); |
994 |
return 0; |
995 |
} |
996 |
|
997 |
static void omap_im3_write(void *opaque, target_phys_addr_t addr, |
998 |
uint32_t value) |
999 |
{ |
1000 |
switch (addr) {
|
1001 |
case 0x0b0: /* SBIMERRLOG */ |
1002 |
case 0x190: /* SBIMSTATE */ |
1003 |
case 0x198: /* SBTMSTATE_L */ |
1004 |
case 0x19c: /* SBTMSTATE_H */ |
1005 |
case 0x1a8: /* SBIMCONFIG_L */ |
1006 |
case 0x1ac: /* SBIMCONFIG_H */ |
1007 |
break;
|
1008 |
|
1009 |
default:
|
1010 |
OMAP_BAD_REG(addr); |
1011 |
} |
1012 |
} |
1013 |
|
1014 |
static CPUReadMemoryFunc *omap_im3_readfn[] = {
|
1015 |
omap_badwidth_read32, |
1016 |
omap_badwidth_read32, |
1017 |
omap_im3_read, |
1018 |
}; |
1019 |
|
1020 |
static CPUWriteMemoryFunc *omap_im3_writefn[] = {
|
1021 |
omap_badwidth_write32, |
1022 |
omap_badwidth_write32, |
1023 |
omap_im3_write, |
1024 |
}; |
1025 |
|
1026 |
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
1027 |
target_phys_addr_t l3_base, |
1028 |
qemu_irq irq, qemu_irq drq, |
1029 |
omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
1030 |
omap_clk ick1, omap_clk ick2) |
1031 |
{ |
1032 |
int iomemtype[5]; |
1033 |
struct omap_dss_s *s = (struct omap_dss_s *) |
1034 |
qemu_mallocz(sizeof(struct omap_dss_s)); |
1035 |
|
1036 |
s->irq = irq; |
1037 |
s->drq = drq; |
1038 |
omap_dss_reset(s); |
1039 |
|
1040 |
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn, |
1041 |
omap_diss1_writefn, s); |
1042 |
iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn, |
1043 |
omap_disc1_writefn, s); |
1044 |
iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn, |
1045 |
omap_rfbi1_writefn, s); |
1046 |
iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn, |
1047 |
omap_venc1_writefn, s); |
1048 |
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn, |
1049 |
omap_im3_writefn, s); |
1050 |
omap_l4_attach(ta, 0, iomemtype[0]); |
1051 |
omap_l4_attach(ta, 1, iomemtype[1]); |
1052 |
omap_l4_attach(ta, 2, iomemtype[2]); |
1053 |
omap_l4_attach(ta, 3, iomemtype[3]); |
1054 |
cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]); |
1055 |
|
1056 |
#if 0
|
1057 |
s->state = graphic_console_init(omap_update_display,
|
1058 |
omap_invalidate_display, omap_screen_dump, s);
|
1059 |
#endif
|
1060 |
|
1061 |
return s;
|
1062 |
} |
1063 |
|
1064 |
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip) |
1065 |
{ |
1066 |
if (cs < 0 || cs > 1) |
1067 |
cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
|
1068 |
s->rfbi.chip[cs] = chip; |
1069 |
} |